Lines Matching +full:5 +full:vs2
424 * Sign extended from 5 bits: [-0x10, 0x0f].
535 TCGReg vs2, bool vm)
538 (vs2 & 0x1f) << 20 | (vm << 25);
687 * Vector registers uses the same 5 lower bits as GPR registers,
689 * With RVV 1.0, vs2 is the first operand, while rs1/imm is the
693 TCGReg vd, TCGReg vs2, TCGReg vs1)
695 tcg_out32(s, encode_v(opc, vd, vs1, vs2, true));
699 TCGReg vd, TCGReg vs2, TCGReg rs1)
701 tcg_out32(s, encode_v(opc, vd, rs1, vs2, true));
705 TCGReg vd, TCGReg vs2, int32_t imm)
707 tcg_out32(s, encode_vi(opc, vd, imm, vs2, true));
711 TCGReg vd, TCGReg vs2, TCGArg vi1, int c_vi1)
714 tcg_out_opc_vi(s, o_vi, vd, vs2, vi1);
716 tcg_out_opc_vv(s, o_vv, vd, vs2, vi1);
721 TCGReg vs2, int32_t imm)
723 tcg_out32(s, encode_vi(opc, vd, imm, vs2, false));
727 TCGReg vs2, TCGReg vs1)
729 tcg_out32(s, encode_v(opc, vd, vs1, vs2, false));
1556 /* vd[i] == v0.mask[i] ? imm : vs2[i] */
1559 /* vd[i] == v0.mask[i] ? vs1[i] : vs2[i] */
2268 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2269 const_args[4], const_args[5], false, true);
2272 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2273 const_args[4], const_args[5], false, false);
2276 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2277 const_args[4], const_args[5], true, true);
2280 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2281 const_args[4], const_args[5], true, false);
2301 tcg_out_movcond(s, args[5], a0, a1, a2, c2,
2524 tcg_out_cmpsel(s, type, vece, args[5], a0, a1, a2, c2,
2984 0x80 + 24, 5, /* DW_CFA_offset, s8, -40 */