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Searched +full:5 +full:vs1 (Results 1 – 21 of 21) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dvcrypto_helper.c337 rk[5] = rk[1] ^ rk[4];
338 rk[6] = rk[2] ^ rk[5];
342 vd[i * 4 + H4(1)] = rk[5];
379 rk[5] = vs2[i * 4 + H4(1)]; in HELPER()
430 static inline void vsha2ms_e32(uint32_t *vd, uint32_t *vs1, uint32_t *vs2) in vsha2ms_e32() argument
433 res[0] = sig1_sha256(vs1[H4(2)]) + vs2[H4(1)] + sig0_sha256(vd[H4(1)]) + in vsha2ms_e32()
435 res[1] = sig1_sha256(vs1[H4(3)]) + vs2[H4(2)] + sig0_sha256(vd[H4(2)]) + in vsha2ms_e32()
440 sig1_sha256(res[1]) + vs1[H4(0)] + sig0_sha256(vs2[H4(0)]) + vd[H4(3)]; in vsha2ms_e32()
447 static inline void vsha2ms_e64(uint64_t *vd, uint64_t *vs1, uint64_t *vs2) in vsha2ms_e64() argument
450 res[0] = sig1_sha512(vs1[2]) + vs2[1] + sig0_sha512(vd[1]) + vd[0]; in vsha2ms_e64()
[all …]
H A Dvector_helper.c1085 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ in RVVCALL()
1098 ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ in RVVCALL()
1157 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
1169 ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
1293 void HELPER(NAME)(void *vd, void *v0, void *vs1, \
1312 TS1 s1 = *((TS1 *)vs1 + HS1(i)); \
1407 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
1420 ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
1891 static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \
1893 TX1 s1 = *((T1 *)vs1 + HS1(i)); \
[all …]
/openbmc/linux/drivers/pcmcia/
H A Dbcm63xx_pcmcia.c112 * floating, and CD[12] input while only VS1 is floating
120 IN_CD2_VS1H = (1 << 5),
125 /* VS1 float, VS2 float */
128 /* VS1 grounded, VS2 float */
131 /* VS1 grounded, VS2 grounded */
134 /* VS1 tied to CD1, VS2 float */
137 /* VS1 grounded, VS2 tied to CD2 */
140 /* VS1 tied to CD2, VS2 grounded */
143 /* VS1 float, VS2 grounded */
146 /* VS1 float, VS2 tied to CD2 */
[all …]
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dpm8941.dtsi84 <0x0 0x10 5 IRQ_TYPE_EDGE_BOTH>,
224 interrupt-names = "ocp-5vs1", "ocp-5vs2";
233 pm8941_5vs1: 5vs1 {
243 pm8941_5vs2: 5vs2 {
H A Dqcom-msm8974pro-samsung-klte.dts48 gpios = <&pma8084_gpios 5 GPIO_ACTIVE_LOW>;
631 pma8084_5vs1: 5vs1 {};
H A Dqcom-apq8084.dtsi110 thermal-sensors = <&tsens 5>;
461 bits = <5 3>;
618 frame-number = <5>;
848 pma8084_5vs1: 5vs1 {};
/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Dqcom,smd-rpm-regulator.yaml52 lvs3, 5vs1, 5vs2
68 l20, l21, l22, l23, l24, l25, l26, l27, lvs1, lvs2, lvs3, lvs4, 5vs1
110 "^((s|l|lvs|5vs)[0-9]*)|(boost-bypass)|(bob)$":
H A Dmediatek,mt6357-regulator.yaml15 The MT6357 PMIC provides 5 BUCK and 29 LDO.
99 mt6357_vs1_reg: buck-vs1 {
100 regulator-name = "vs1";
H A Dqcom,spmi-regulator.yaml35 "^(5vs[1-2]|(l|s)[1-9][0-9]?|lvs[1-3])$":
157 "^vdd_s[1-5]-supply$": true
197 "^vdd_s[1-5]-supply$": true
235 - description: Over-current protection interrupt for 5V S1
236 - description: Over-current protection interrupt for 5V S2
239 - const: ocp-5vs1
240 - const: ocp-5vs2
324 "^vdd_s[1-5]-supply$": true
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvv.c.inc286 * 5. Vector register numbers accessed by the segment load or store
376 * 3. Source (vs2, vs1) vector register number are multiples of LMUL.
379 static bool vext_check_sss(DisasContext *s, int vd, int vs1, int vs2, int vm)
382 require_align(vs1, s->lmul);
399 * 1. Source (vs2, vs1) vector register number are multiples of LMUL.
402 * register (vs2, vs1) group.
410 static bool vext_check_mss(DisasContext *s, int vd, int vs1, int vs2)
413 require_align(vs1, s->lmul);
414 if (vd != vs1) {
415 ret &= require_noover(vd, 0, vs1, s->lmul);
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/openbmc/linux/arch/powerpc/crypto/
H A Dpoly1305-p10le_64.S17 # p = 2^130 - 5
31 # vs1 = [r1,.....]
35 # vs5 = [r1*5,...]
36 # vs6 = [r2*5,...]
37 # vs7 = [r2*5,...]
38 # vs8 = [r4*5,...]
42 # r0, r4*5, r3*5, r2*5, r1*5;
43 # r1, r0, r4*5, r3*5, r2*5;
44 # r2, r1, r0, r4*5, r3*5;
45 # r3, r2, r1, r0, r4*5;
[all …]
H A Daes-gcm-p10.S49 # vs1 - vs9 - round keys
77 xxlor 19+32, 5, 5
111 # vs1 - vs9 - round keys
155 xxlor 23+32, 5, 5
218 xxlor 19+32, 5, 5
270 vpmsumd 27, 5, 18
329 vpmsumd 27, 5, 18
378 vpmsumd 27, 5, 22
406 vpmsumd 24, 5, 28 # H
536 lxvd2x 5+32, 10, 8 # Hh
[all …]
/openbmc/linux/drivers/regulator/
H A Dmt6358-regulator.c288 0, 1, 2, 4, 5, 9, 11, 13,
296 3, 4, 5, 6, 7, 9, 12,
304 2, 3, 5,
517 MT6358_BUCK("buck_vs1", VS1, 1000000, 2587500, 12500,
595 MT6366_BUCK("buck_vs1", VS1, 1000000, 2587500, 12500,
H A Dqcom_smd-regulator.c811 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
837 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8998_hfsmps, "vdd_s5" },
845 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" },
873 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm660_hfsmps, "vdd_s5" },
879 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm660_ht_nldo, "vdd_l5" },
906 { "l5", QCOM_SMD_RPM_LDOB, 5, &pm660_pldo660, "vdd_l3_l5_l7_l8" },
921 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8226_hfsmps, "vdd_s5" },
926 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8226_nldo, "vdd_l1_l2_l4_l5" },
959 { "s5", QCOM_SMD_RPM_SMPB, 5, &pm8841_ftsmps, "vdd_s5" },
973 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8226_pldo, "vdd_l2_l5" },
[all …]
H A Dqcom_spmi-regulator.c252 SPMI_COMMON_IDX_MODE = 5,
279 #define SPMI_FTSMPS426_MODE_LPM_MASK 5
337 #define SPMI_FTSMPS_STEP_MARGIN_DEN 5
996 * In case of range 1: voltage_sel is a 5 bit value, bits[7-5] set to in spmi_regulator_ult_lo_smps_set_voltage()
1640 SPMI_VREG(BOOST, 5V_BOOST, 0, INF, BOOST, boost, boost, 0),
2229 { "5vs1", 0x8300, "vin_5vs", "ocp-5vs1", },
2230 { "5vs2", 0x8400, "vin_5vs", "ocp-5vs2", },
/openbmc/qemu/tcg/riscv/
H A Dtcg-target.c.inc424 * Sign extended from 5 bits: [-0x10, 0x0f].
687 * Vector registers uses the same 5 lower bits as GPR registers,
693 TCGReg vd, TCGReg vs2, TCGReg vs1)
695 tcg_out32(s, encode_v(opc, vd, vs1, vs2, true));
727 TCGReg vs2, TCGReg vs1)
729 tcg_out32(s, encode_v(opc, vd, vs1, vs2, false));
1559 /* vd[i] == v0.mask[i] ? vs1[i] : vs2[i] */
2268 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2269 const_args[4], const_args[5], false, true);
2272 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
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/openbmc/linux/tools/testing/selftests/powerpc/primitives/asm/
H A Dppc_asm.h80 ZEROIZE_GPRS(5, 12); \
169 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
573 #define cr5 5
627 #define fr5 5
662 #define v5 5
693 #define vs1 1
697 #define vs5 5
764 #define evr5 5
/openbmc/linux/arch/powerpc/include/asm/
H A Dppc_asm.h80 ZEROIZE_GPRS(5, 12); \
169 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
573 #define cr5 5
627 #define fr5 5
662 #define v5 5
693 #define vs1 1
697 #define vs5 5
764 #define evr5 5
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/pxaregs/pxaregs-1.14/
H A Dpxaregs.c57 { "ICR_SCLE", 0x40301690, 5, 1, 'x', " master clock enable " },
75 { "ISR_ALD", 0x40301698, 5, 1, 'x', " arbitration loss detected " },
93 { "PSSR_RDH", 0x40F00004, 5, 0x00000001, 'd', "PM receivers of all input GPIO are disabled" },
103 { "PWER_WE5", 0x40F0000C, 5, 0x00000001, 'd', "PM wake up due to GPIO 5 edge detect enabled" },
122 { "PRER_RE5", 0x40F00010, 5, 0x00000001, 'd', "PM wake up due to GPIO 5 rising edge detect enable…
140 { "PFER_FE5", 0x40F00014, 5, 0x00000001, 'd', "PM wake up due to GPIO 5 falling edge detect enabl…
158 { "PEDR_ED5", 0x40F00018, 5, 0x00000001, 'd', "PM wake up due to edge on GPIO 5 detected" },
181 { "PGSR_SS5", 0x40F00020, 5, 0x00000001, 'd', "PM GPIO pin 5 is driven to 1 during sleep" },
215 { "PGSR_SS37", 0x40F00024, 5, 0x00000001, 'd', "PM GPIO pin 37 is driven to 1 during sleep" },
249 { "PGSR_SS69", 0x40F00028, 5, 0x00000001, 'd', "PM GPIO pin 69 is driven to 1 during sleep" },
[all …]
/openbmc/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_phy.c468 * @device_type: 5 bit device type
546 * @device_type: 5 bit device type
571 * @device_type: 5 bit device type
644 * @device_type: 5 bit device type
697 hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT; in ixgbe_mii_bus_read_generic_c22()
771 hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT; in ixgbe_mii_bus_write_generic_c22()
1121 /* Set or unset auto-negotiation 5G advertisement */ in ixgbe_setup_phy_link_generic()
1276 * Reads the VS1 register to determine if link is up and the current speed for
1590 * 5 SFP_SR/LR_CORE0 - 82599-specific in ixgbe_identify_sfp_module_generic()
/openbmc/linux/tools/perf/pmu-events/arch/powerpc/power8/
H A Dother.json17 …R mode. Threads 0-1 belong to lpar0, threads 2-3 belong to lpar1, threads 4-5 belong to lpar2, and…
1649 "BriefDescription": "VS1 ISU reject",
3041 "BriefDescription": "Cycles thread running at priority level 4 or 5",