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/openbmc/linux/arch/powerpc/kernel/
H A Dcpu_specs_40x.h59 { /* 405GPr */
62 .cpu_name = "405GPr",
85 { /* 405LP */
88 .cpu_name = "405LP",
97 { /* 405EP */
100 .cpu_name = "405EP",
110 { /* 405EX Rev. A/B with Security */
113 .cpu_name = "405EX Rev. A/B",
123 { /* 405EX Rev. C without Security */
126 .cpu_name = "405EX Rev. C",
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dacadia.dts2 * Device Tree Source for AMCC Acadia (405EZ)
32 model = "PowerPC,405EZ";
51 compatible = "ibm,uic-405ez", "ibm,uic";
61 compatible = "ibm,plb-405ez", "ibm,plb3";
68 compatible = "ibm,mcmal-405ez", "ibm,mcmal";
73 /* 405EZ has only 3 interrupts to the UIC, as
84 compatible = "ibm,opb-405ez", "ibm,opb";
113 compatible = "ibm,iic-405ez", "ibm,iic";
120 compatible = "ibm,gpio-405ez";
125 compatible = "ibm,gpio-405ez";
[all …]
H A Dhaleakala.dts2 * Device Tree Source for AMCC Haleakala (405EXr)
32 model = "PowerPC,405EXr";
51 compatible = "ibm,uic-405exr", "ibm,uic";
61 compatible = "ibm,uic-405exr","ibm,uic";
73 compatible = "ibm,uic-405exr","ibm,uic";
85 compatible = "ibm,plb-405exr", "ibm,plb4";
92 compatible = "ibm,sdram-405exr", "ibm,sdram-4xx-ddr2";
100 compatible = "ibm,mcmal-405exr", "ibm,mcmal2";
118 compatible = "ibm,opb-405exr", "ibm,opb";
128 compatible = "ibm,ebc-405exr", "ibm,ebc";
[all …]
H A Dobs600.dts2 * Device Tree Source for PlatHome OpenBlockS 600 (405EX)
37 model = "PowerPC,405EX";
56 compatible = "ibm,uic-405ex", "ibm,uic";
66 compatible = "ibm,uic-405ex","ibm,uic";
78 compatible = "ibm,uic-405ex","ibm,uic";
99 compatible = "ibm,plb-405ex", "ibm,plb4";
106 compatible = "ibm,sdram-405ex", "ibm,sdram-4xx-ddr2";
121 compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
139 compatible = "ibm,opb-405ex", "ibm,opb";
149 compatible = "ibm,ebc-405ex", "ibm,ebc";
[all …]
H A Dmakalu.dts2 * Device Tree Source for AMCC Makalu (405EX)
33 model = "PowerPC,405EX";
52 compatible = "ibm,uic-405ex", "ibm,uic";
62 compatible = "ibm,uic-405ex","ibm,uic";
74 compatible = "ibm,uic-405ex","ibm,uic";
86 compatible = "ibm,plb-405ex", "ibm,plb4";
93 compatible = "ibm,sdram-405ex", "ibm,sdram-4xx-ddr2";
101 compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
119 compatible = "ibm,opb-405ex", "ibm,opb";
129 compatible = "ibm,ebc-405ex", "ibm,ebc";
[all …]
H A Dkilauea.dts2 * Device Tree Source for AMCC Kilauea (405EX)
33 model = "PowerPC,405EX";
52 compatible = "ibm,uic-405ex", "ibm,uic";
62 compatible = "ibm,uic-405ex","ibm,uic";
74 compatible = "ibm,uic-405ex","ibm,uic";
95 compatible = "ibm,plb-405ex", "ibm,plb4";
102 compatible = "ibm,sdram-405ex", "ibm,sdram-4xx-ddr2";
117 compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
135 compatible = "ibm,opb-405ex", "ibm,opb";
145 compatible = "ibm,ebc-405ex", "ibm,ebc";
[all …]
H A Dhotfoot.dts33 model = "PowerPC,405EP";
69 compatible = "ibm,sdram-405ep";
74 compatible = "ibm,mcmal-405ep", "ibm,mcmal";
88 compatible = "ibm,opb-405ep", "ibm,opb";
122 compatible = "ibm,iic-405ep", "ibm,iic";
162 compatible = "ibm,emac-405ep", "ibm,emac";
183 compatible = "ibm,emac-405ep", "ibm,emac";
204 compatible = "ibm,ebc-405ep", "ibm,ebc";
/openbmc/qemu/target/ppc/
H A Dcpu-models.c70 /* PowerPC 405 family */
71 /* PowerPC 405 cores */
72 POWERPC_DEF("405d2", CPU_POWERPC_405D2, 405,
73 "PowerPC 405 D2")
74 POWERPC_DEF("405d4", CPU_POWERPC_405D4, 405,
75 "PowerPC 405 D4")
76 /* PowerPC 405 microcontrollers */
77 POWERPC_DEF("405cra", CPU_POWERPC_405CRa, 405,
78 "PowerPC 405 CRa")
79 POWERPC_DEF("405crb", CPU_POWERPC_405CRb, 405,
[all …]
H A Dcpu-models.h42 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
43 /* PowerPC 405 family */
44 /* PowerPC 405 cores */
47 /* PowerPC 405 microcontrollers */
65 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
/openbmc/linux/arch/powerpc/platforms/40x/
H A DKconfig6 select 405EZ
8 This option enables support for the AMCC 405EZ Acadia evaluation board.
21 select 405EX
32 select 405EX
42 select 405EX
53 config 405EX
58 config 405EZ
/openbmc/u-boot/doc/
H A DREADME.scrapyard128 CPCI405 ppc4xx 405gp 5f1459dc 2015-01-13 Matthias Fuchs <matthias.fuchs@…
129 CPCI405DT ppc4xx 405gpr 5f1459dc 2015-01-13 Matthias Fuchs <matthias.fuchs@…
130 CPCI405AB ppc4xx 405gpr 5f1459dc 2015-01-13 Matthias Fuchs <matthias.fuchs@…
131 G2000 ppc4xx 405ep 5f8f6294 2015-01-13 Matthias Fuchs <matthias.fuchs@…
132 WUH405 ppc4xx 405ep fc88a5bf 2015-01-13 Matthias Fuchs <matthias.fuchs@…
133 VOH405 ppc4xx 405ep 807db88b 2015-01-13 Matthias Fuchs <matthias.fuchs@…
134 PMC405 ppc4xx 405gp d5263304 2015-01-13 Matthias Fuchs <matthias.fuchs@…
135 PCI405 ppc4xx 405gp dbe7bb0d 2015-01-13 Matthias Fuchs <matthias.fuchs@…
136 OCRTC ppc4xx 405gpr cc6e715f 2015-01-13 Matthias Fuchs <matthias.fuchs@…
137 HUB405 ppc4xx 405ep e434d5d7 2015-01-13 Matthias Fuchs <matthias.fuchs@…
[all …]
H A DREADME.bedbug5 A specific implementation is made for the AMCC 405 processor but other flavors
25 Added code to handle the debug exception (0x2000) on the 405.
27 is treated as critical on the 405.
/openbmc/qemu/tests/functional/
H A Dtest_ppc_405.py3 # Test that the U-Boot firmware boots on ppc 405 machines and check the console
29 exec_command_and_wait_for_pattern(self, 'reset', 'AMCC PowerPC 405EP')
/openbmc/linux/Documentation/admin-guide/gpio/
H A Dgpio-mockup.rst25 Example: gpio_mockup_ranges=-1,8,-1,16,405,409
29 to 405 while for two first chips it will be assigned automatically.
/openbmc/linux/arch/powerpc/boot/
H A Ddcr.h156 /* 405GP Clocking/Power Management/Chip Control regs */
162 /* 405EP Clocking/Power Management/Chip Control regs */
167 /* 440GX/405EX Clock Control reg */
H A DMakefile55 $(obj)/4xx.o: BOOTTARGETFLAGS += -mcpu=405
57 $(obj)/cuboot-hotfoot.o: BOOTTARGETFLAGS += -mcpu=405
60 $(obj)/cuboot-acadia.o: BOOTTARGETFLAGS += -mcpu=405
61 $(obj)/treeboot-iss4xx.o: BOOTTARGETFLAGS += -mcpu=405
62 $(obj)/treeboot-currituck.o: BOOTTARGETFLAGS += -mcpu=405
63 $(obj)/treeboot-akebono.o: BOOTTARGETFLAGS += -mcpu=405
/openbmc/openbmc/meta-security/meta-tpm/recipes-tpm2/tpm2-tss-engine/files/
H A D0002-Fix-mismatch-of-OpenSSL-function-signatures-that-cau.patch45 @@ -405,7 +405,7 @@ ecdsa_ec_key_sign(const unsigned char *dgst, int dgst_len, const BIGNUM *inv,
/openbmc/linux/drivers/net/ethernet/ibm/emac/
H A Dmal.h26 * We call MAL 1 the version in 405GP, 405GPR, 405EP, 440EP, 440GR and
/openbmc/linux/drivers/edac/
H A Dppc4xx_edac.c26 * 405EX[r], 440SP, 440SPe, 460EX, 460GT and 460SX.
28 * As realized in the 405EX[r], this controller features:
71 * realization in the 405EX[r] on the AMCC Kilauea and Haleakala
84 * - IBM SDRAM (405GP, 405CR and 405EP) "ibm,sdram-4xx"
817 * the 405EX[r] is 16-/32-bit and the others are 32-/64-bit with the
1221 * the AMCC PPC 405EX[r]. Reject anything else. in ppc4xx_edac_probe()
1224 if (!of_device_is_compatible(np, "ibm,sdram-405ex") && in ppc4xx_edac_probe()
1225 !of_device_is_compatible(np, "ibm,sdram-405exr")) { in ppc4xx_edac_probe()
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-benchmark/libhugetlbfs/files/
H A D0006-include-stddef.h-for-ptrdiff_t.patch14 index 405c566..0edccd2 100644
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/device/
H A Dpci.c211 { 0x1462, 0xaa51, "GeForce 405" },
212 { 0x1462, 0xaa58, "GeForce 405" },
213 { 0x1462, 0xac71, "GeForce 405" },
214 { 0x1462, 0xac82, "GeForce 405" },
215 { 0x1642, 0x3980, "GeForce 405" },
216 { 0x17aa, 0x3950, "GeForce 405M" },
217 { 0x17aa, 0x397d, "GeForce 405M" },
218 { 0x1b0a, 0x90b4, "GeForce 405" },
219 { 0x1bfd, 0x0003, "GeForce 405" },
220 { 0x1bfd, 0x8006, "GeForce 405" },
[all …]
/openbmc/openbmc-test-automation/lib/
H A Drest_response_code.robot27 ${HTTP_METHOD_NOT_ALLOWED} 405
/openbmc/linux/arch/powerpc/platforms/
H A DKconfig.cputype197 config 405_CPU
267 default "405" if 405_CPU
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dprocessor.h894 #define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A/B without Security */
895 #define PVR_405EX1_RA 0x12911477 /* 405EX rev A/B with Security */
896 #define PVR_405EXR1_RC 0x1291147B /* 405EXr rev C with Security */
897 #define PVR_405EXR2_RC 0x12911479 /* 405EXr rev C without Security */
898 #define PVR_405EX1_RC 0x1291147F /* 405EX rev C with Security */
899 #define PVR_405EX2_RC 0x1291147D /* 405EX rev C without Security */
900 #define PVR_405EXR1_RD 0x12911472 /* 405EXr rev D with Security */
901 #define PVR_405EXR2_RD 0x12911470 /* 405EXr rev D without Security */
902 #define PVR_405EX1_RD 0x12911475 /* 405EX rev D with Security */
903 #define PVR_405EX2_RD 0x12911473 /* 405EX rev D without Security */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Drenesas,sci.yaml100 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,

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