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/openbmc/linux/drivers/clk/mvebu/
H A Dmv98dx3236.c25 * 0 = 400 MHz 400 MHz 800 MHz
26 * 2 = 667 MHz 667 MHz 2000 MHz
27 * 3 = 800 MHz 800 MHz 1600 MHz
34 * 1 = 667 MHz 667 MHz 2000 MHz
35 * 2 = 400 MHz 400 MHz 400 MHz
36 * 3 = 800 MHz 800 MHz 800 MHz
37 * 5 = 800 MHz 400 MHz 800 MHz
46 /* Tclk = 200MHz, no SaR dependency */ in mv98dx3236_get_tclk_freq()
H A Darmada-375.c29 * 6 = 400 MHz 400 MHz 200 MHz
30 * 15 = 600 MHz 600 MHz 300 MHz
31 * 21 = 800 MHz 534 MHz 400 MHz
32 * 25 = 1000 MHz 500 MHz 500 MHz
36 * 0 = 166 MHz
37 * 1 = 200 MHz
/openbmc/u-boot/board/freescale/mpc8572ds/
H A Dddr.c27 * all clocks from 400MT/s to 800MT/s, verified with Kingston KVR800D2D8P6/2G.
29 * from 400MT/s to 800MT/s, verified with Micron MT18HTF25672AY-800E1.
37 * ranks| mhz|adjst| | delay|
40 {2, 400, 8, 9, 5, 0},
45 {1, 400, 6, 9, 3, 0},
56 * ranks| mhz|adjst| | delay|
59 {2, 400, 8, 9, 5, 0},
64 {1, 400, 6, 9, 3, 0},
80 * ranks| mhz|adjst| | delay|
83 {2, 400, 4, 9, 3, 0},
[all …]
/openbmc/u-boot/board/k+p/kp_imx53/
H A Dkp_imx53.c112 /* Set VDDGP to 1.110V for 800 MHz on SW1 */ in power_init()
132 * CPU clock set to 800MHz and DDR to 400MHz in setup_clocks()
136 printf("CPU: Switch CPU clock to 800MHZ failed\n"); in setup_clocks()
138 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); in setup_clocks()
139 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); in setup_clocks()
141 printf("CPU: Switch DDR clock to 400MHz failed\n"); in setup_clocks()
177 udelay(400); in eth_phy_reset()
/openbmc/linux/drivers/clk/spear/
H A Dspear1340_clock.c164 /* PCLK 24MHz */
165 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
166 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
167 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
168 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
169 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
170 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
172 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
177 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
178 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
[all …]
/openbmc/u-boot/drivers/i2c/
H A Daspeed_i2c_global.c27 * APB clk : 100Mhz
31 * 0x3c : 100.8Khz : 3.225Mhz : 4.96us
32 * 0x3d : 99.2Khz : 3.174Mhz : 5.04us
33 * 0x3e : 97.65Khz : 3.125Mhz : 5.12us
34 * 0x40 : 97.75Khz : 3.03Mhz : 5.28us
35 * 0x41 : 99.5Khz : 2.98Mhz : 5.36us (default)
36 * I2CG10[15:8] base clk2 for Fast-mode (400Khz) min tBuf 1.3us
37 * 0x12 : 400Khz : 10Mhz : 1.6us
38 * I2CG10[7:0] base clk1 for Fast-mode Plus (1Mhz) min tBuf 0.5us
39 * 0x08 : 1Mhz : 20Mhz : 0.8us
/openbmc/u-boot/drivers/ddr/imx/imx8m/
H A Dddrphy_utils.c110 dram_pll_init(MHZ(800)); in ddrphy_init_set_dfi_clk()
114 dram_pll_init(MHZ(750)); in ddrphy_init_set_dfi_clk()
118 dram_pll_init(MHZ(600)); in ddrphy_init_set_dfi_clk()
122 dram_pll_init(MHZ(400)); in ddrphy_init_set_dfi_clk()
126 dram_pll_init(MHZ(167)); in ddrphy_init_set_dfi_clk()
129 case 400: in ddrphy_init_set_dfi_clk()
130 dram_enable_bypass(MHZ(400)); in ddrphy_init_set_dfi_clk()
133 dram_enable_bypass(MHZ(100)); in ddrphy_init_set_dfi_clk()
/openbmc/u-boot/arch/mips/mach-ath79/ar934x/
H A Dclk.c20 * XTAL [MHz] 2^(18 - 1)
21 * PLL [MHz] = ------------ * ----------------------
33 /* Index 0 is for XTAL=25MHz , Index 1 is for XTAL=40MHz */
48 { 400, 200, 200, { 1, 1, 1, { 32, 20 } }, { 1, 1, 2, { 32, 20 } } },
49 { 400, 400, 200, { 0, 1, 1, { 32, 20 } }, { 0, 1, 1, { 32, 20 } } },
50 { 500, 400, 200, { 1, 1, 0, { 20, 12 } }, { 0, 1, 1, { 32, 20 } } },
51 { 533, 400, 200, { 1, 1, 0, { 21, 13 } }, { 0, 1, 1, { 32, 20 } } },
54 { 566, 400, 200, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 16, 10 } } },
65 { 600, 400, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 32, 20 } } },
74 { 700, 400, 200, { 3, 1, 0, { 28, 17 } }, { 0, 1, 1, { 32, 20 } } },
[all …]
/openbmc/linux/drivers/i3c/master/mipi-i3c-hci/
H A Dxfer_mode_rate.h48 #define XFERRATE_I3C_SDR0 0x00 /* 12.5 MHz */
49 #define XFERRATE_I3C_SDR1 0x01 /* 8 MHz */
50 #define XFERRATE_I3C_SDR2 0x02 /* 6 MHz */
51 #define XFERRATE_I3C_SDR3 0x03 /* 4 MHz */
52 #define XFERRATE_I3C_SDR4 0x04 /* 2 MHz */
53 #define XFERRATE_I3C_SDR_FM_FMP 0x05 /* 400 KHz / 1 MHz */
57 #define XFERRATE_I2C_FM 0x00 /* 400 KHz */
58 #define XFERRATE_I2C_FMP 0x01 /* 1 MHz */
/openbmc/u-boot/board/boundary/nitrogen6x/
H A Dddr-setup.cfg18 * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
20 * MX6DL ddr is limited to 800 MHz(400 MHz clock)
22 * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
/openbmc/u-boot/board/toradex/apalis_imx6/
H A Dddr-setup.cfg19 * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
21 * MX6DL ddr is limited to 800 MHz(400 MHz clock)
23 * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
/openbmc/u-boot/board/toradex/colibri_imx6/
H A Dddr-setup.cfg19 * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
21 * MX6DL ddr is limited to 800 MHz(400 MHz clock)
23 * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
/openbmc/linux/drivers/cpufreq/
H A Dpmac32-cpufreq.c502 * frequency, it claims it to be around 84Mhz on some models while in pmac_cpufreq_init_MacRISC3()
503 * it appears to be approx. 101Mhz on all. Let's hack around here... in pmac_cpufreq_init_MacRISC3()
605 * - Titanium PowerBook 1Ghz (PMU based, 667Mhz & 1Ghz)
606 * - Titanium PowerBook 800 (PMU based, 667Mhz & 800Mhz)
607 * - Titanium PowerBook 400 (PMU based, 300Mhz & 400Mhz)
608 * - Titanium PowerBook 500 (PMU based, 300Mhz & 500Mhz)
609 * - iBook2 500/600 (PMU based, 400Mhz & 500/600Mhz)
610 * - iBook2 700 (CPU based, 400Mhz & 700Mhz, support low voltage)
661 /* Else check for TiPb 400 & 500 */ in pmac_cpufreq_setup()
663 /* We only know about the 400 MHz and the 500Mhz model in pmac_cpufreq_setup()
[all …]
/openbmc/u-boot/board/freescale/t102xqds/
H A Dt1024_sd_rcw.cfg1 # single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
2 # Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
H A Dt1024_nand_rcw.cfg1 # single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
2 # Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
H A Dt1024_spi_rcw.cfg1 # single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
2 # Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
/openbmc/u-boot/arch/arm/mach-omap2/am33xx/
H A Dclock_am33xx.c67 { /* 19.2 MHz */
75 { /* 24 MHz */
83 { /* 25 MHz */
91 { /* 26 MHz */
96 {400, 12, 1, -1, -1, -1, -1}, /* OPP TB */
102 {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
103 {125, 2, -1, -1, 10, 8, 4}, /* 24 MHz */
104 {40, 0, -1, -1, 10, 8, 4}, /* 25 MHz */
105 {500, 12, -1, -1, 10, 8, 4} /* 26 MHz */
109 {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */
[all …]
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt8365-apmixedsys.c15 #define MT8365_PLL_FMAX (3800UL * MHZ)
16 #define MT8365_PLL_FMIN (1500UL * MHZ)
57 { .div = 1, .freq = 1500 * MHZ },
58 { .div = 2, .freq = 750 * MHZ },
59 { .div = 3, .freq = 375 * MHZ },
66 { .div = 1, .freq = 1600 * MHZ },
67 { .div = 2, .freq = 800 * MHZ },
68 { .div = 3, .freq = 400 * MHZ },
69 { .div = 4, .freq = 200 * MHZ },
75 { .div = 1, .freq = 1600 * MHZ },
[all …]
/openbmc/linux/arch/m68k/include/uapi/asm/
H A Dbootinfo-hp300.h20 * HP9000/300 and /400 models (BI_HP300_MODEL)
25 #define HP_320 0 /* 16MHz 68020+HP MMU+16K external cache */
26 #define HP_330 1 /* 16MHz 68020+68851 MMU */
27 #define HP_340 2 /* 16MHz 68030 */
28 #define HP_345 3 /* 50MHz 68030+32K external cache */
29 #define HP_350 4 /* 25MHz 68020+HP MMU+32K external cache */
30 #define HP_360 5 /* 25MHz 68030 */
31 #define HP_370 6 /* 33MHz 68030+64K external cache */
32 #define HP_375 7 /* 50MHz 68030+32K external cache */
33 #define HP_380 8 /* 25MHz 68040 */
[all …]
/openbmc/u-boot/board/freescale/bsc9131rdb/
H A DREADME21 ECC, up to 400-MHz clock/800 MHz data rate
76 Core MHz/CCB MHz/DDR(MT/s)
78 2. 800/400/667
92 1. NAND Flash with sysclk 66MHz(J16 on RDB closed, default)
94 2. NAND Flash with sysclk 100MHz(J16 on RDB open)
96 3. SPI Flash with sysclk 66MHz(J16 on RDB closed, default)
98 4. SPI Flash with sysclk 100MHz(J16 on RDB open)
/openbmc/linux/drivers/memory/
H A Djedec_ddr_data.c33 /* Speed bin 400(200 MHz) */
54 /* Speed bin 533(266 MHz) */
75 /* Speed bin 800(400 MHz) */
96 /* Speed bin 1066(533 MHz) */
/openbmc/u-boot/arch/arm/mach-omap2/omap4/
H A Dhw_data.c36 * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
40 {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
41 {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
42 {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
43 {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
44 {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
45 {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
46 {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
50 * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
55 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
[all …]
/openbmc/linux/drivers/staging/media/atomisp/pci/
H A Datomisp_internal.h53 /* MRFLD with 0x1178: ISP freq can burst to 457MHz */
55 /* MRFLD with 0x1179: max ISP freq limited to 400MHz */
57 /* MRFLD with 0x117a: max ISP freq is 400MHz and max freq at Vmin is 200MHz */
/openbmc/u-boot/drivers/mmc/
H A Dbcmstb_sdhci.c15 * capability is 100 MHz. The divisor that is eventually written to
19 * This define used to be set to 52000000 (52 MHz), the desired
21 * actually running at 100 MHz (seemingly without issue), which is
24 * Now, by setting this to 0 (auto-detect), 100 MHz will be read from
27 * in-spec 52 MHz value.
32 * sets it to 100 MHz divided by SDHCI_MAX_DIV_SPEC_300, or 48,875 Hz,
35 * (400 kHz) to prevent this.
/openbmc/u-boot/board/siemens/draco/
H A Dboard.c43 /* Default@303MHz-i0 */
48 "default name @303MHz \0",
61 #elif DDR_PLL_FREQ == 400
62 /* Default@400MHz-i0 */
67 "default name @400MHz \0",
81 printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ); in print_ddr3_timings()
114 printf("max freq: \t%d MHz\n", dpll_mpu_opp100.m); in print_chip_data()

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