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/openbmc/u-boot/arch/arm/include/asm/arch-vf610/
H A Dcrm_regs.h61 u32 reserved_0x014[3];
63 u32 reserved_0x024[3];
65 u32 reserved_0x034[3];
67 u32 reserved_0x044[3];
69 u32 reserved_0x054[3];
71 u32 reserved_0x064[3];
73 u32 reserved_0x074[3];
75 u32 reserved_0x084[3];
77 u32 reserved_0x094[3];
79 u32 reserved_0x0A4[3];
[all …]
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Ddp.h205 #define VIDEO_BIST_MASK (0x1 << 3)
213 #define TX_TERMINAL_CTRL_45_OHM (0x3 << 4)
214 #define SWING_A_30PER_G_INCREASE (0x1 << 3)
215 #define SWING_A_30PER_G_NORMAL (0x0 << 3)
219 #define SEL_24M (0x1 << 3)
220 #define TX_DVDD_BIT_1_0000V (0x3 << 0)
225 #define DRIVE_DVDD_BIT_1_0000V (0x3 << 5)
228 #define SEL_CURRENT_DEFAULT (0x0 << 3)
232 #define VCO_BIT_400_MICRO (0x3 << 0)
240 #define AUX_TERMINAL_CTRL_52_OHM (0x3 << 4)
[all …]
/openbmc/linux/drivers/net/ethernet/qlogic/qed/
H A Dqed_hsi.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
147 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_MASK 0x3
158 __le16 reserved[3];
188 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3
190 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3
206 __le16 reserved[3];
240 __le32 reserved1[3];
256 u8 reserved[3];
329 #define CORE_TX_BD_DATA_IP_CSUM_SHIFT 3
359 #define CORE_TX_BD_TX_DST_MASK 0x3
[all …]
/openbmc/linux/arch/x86/crypto/
H A Dserpent-sse2-x86_64-asm_64.S41 #define S0_1(x0, x1, x2, x3, x4) \ argument
42 movdqa x3, x4; \
43 por x0, x3; \
47 pxor x1, x3; \
51 #define S0_2(x0, x1, x2, x3, x4) \ argument
52 pxor x3, x0; \
56 pxor x2, x3; \
61 #define S1_1(x0, x1, x2, x3, x4) \ argument
64 pxor x3, x0; \
65 pxor RNOT, x3; \
[all …]
H A Dserpent-sse2-i586-asm_32.S42 #define K(x0, x1, x2, x3, x4, i) \ argument
49 get_key(i, 3, x4); \
50 pxor x4, x3;
52 #define LK(x0, x1, x2, x3, x4, i) \ argument
59 pslld $3, x2; \
60 psrld $(32 - 3), x4; \
68 pslld $3, x4; \
69 pxor x2, x3; \
70 pxor x4, x3; \
71 movdqa x3, x4; \
[all …]
H A Dserpent-avx2-asm_64.S21 .byte 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
51 #define S0_1(x0, x1, x2, x3, x4) \ argument
52 vpor x0, x3, tp; \
53 vpxor x3, x0, x0; \
54 vpxor x2, x3, x4; \
56 vpxor x1, tp, x3; \
60 #define S0_2(x0, x1, x2, x3, x4) \ argument
61 vpxor x3, x0, x0; \
65 vpxor x2, x3, x3; \
70 #define S1_1(x0, x1, x2, x3, x4) \ argument
[all …]
H A Dserpent-avx-x86_64-asm_64.S20 .byte 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
51 #define S0_1(x0, x1, x2, x3, x4) \ argument
52 vpor x0, x3, tp; \
53 vpxor x3, x0, x0; \
54 vpxor x2, x3, x4; \
56 vpxor x1, tp, x3; \
60 #define S0_2(x0, x1, x2, x3, x4) \ argument
61 vpxor x3, x0, x0; \
65 vpxor x2, x3, x3; \
70 #define S1_1(x0, x1, x2, x3, x4) \ argument
[all …]
/openbmc/linux/crypto/
H A Dserpent_generic.c27 #define loadkeys(x0, x1, x2, x3, i) \ argument
28 ({ x0 = k[i]; x1 = k[i+1]; x2 = k[i+2]; x3 = k[i+3]; })
30 #define storekeys(x0, x1, x2, x3, i) \ argument
31 ({ k[i] = x0; k[i+1] = x1; k[i+2] = x2; k[i+3] = x3; })
33 #define store_and_load_keys(x0, x1, x2, x3, s, l) \ argument
34 ({ storekeys(x0, x1, x2, x3, s); loadkeys(x0, x1, x2, x3, l); })
36 #define K(x0, x1, x2, x3, i) ({ \ argument
37 x3 ^= k[4*(i)+3]; x2 ^= k[4*(i)+2]; \
41 #define LK(x0, x1, x2, x3, x4, i) ({ \ argument
43 x2 = rol32(x2, 3); x1 ^= x0; x4 = x0 << 3; \
[all …]
/openbmc/linux/sound/soc/codecs/
H A Drt5677.h354 #define RT5677_MICBIAS1_OVTH_MASK (0x3 << 9)
363 #define RT5677_SLB_ADC4_MASK (0x3 << 6)
365 #define RT5677_SLB_ADC3_MASK (0x3 << 4)
367 #define RT5677_SLB_ADC2_MASK (0x3 << 2)
369 #define RT5677_SLB_ADC1_MASK (0x3 << 0)
388 /* Analog DAC1/2/3 Source Control (0x15) */
389 #define RT5677_ANA_DAC3_SRC_SEL_MASK (0x3 << 4)
391 #define RT5677_ANA_DAC1_2_SRC_SEL_MASK (0x3 << 0)
407 #define RT5677_M_DAC3_R_VOL (0x1 << 3)
408 #define RT5677_M_DAC3_R_VOL_SFT 3
[all …]
H A Dmt6359.h267 #define RG_AUDACCDETVIN1PULLLOW_SFT 3
269 #define RG_AUDACCDETVIN1PULLLOW_MASK_SFT (0x1 << 3)
436 #define RG_EINT0CEN_SFT 3
438 #define RG_EINT0CEN_MASK_SFT (0x1 << 3)
515 #define ACCDET_DSN_CBS_MASK 0x3
516 #define ACCDET_DSN_CBS_MASK_SFT (0x3 << 0)
520 #define ACCDET_DSN_BIX_MASK 0x3
521 #define ACCDET_DSN_BIX_MASK_SFT (0x3 << 2)
570 #define RG_AUDACCDETRSV_MASK 0x3
571 #define RG_AUDACCDETRSV_MASK_SFT (0x3 << 13)
[all …]
H A Dtscs454.h18 #define R_IRQMASK VIRT_ADDR(0x0, 0x3)
70 #define R_HSDSTAT VIRT_ADDR(0x1, 0x3)
102 #define R_SUBCTL VIRT_ADDR(0x2, 0x3)
126 #define R_SPKEQFILT VIRT_ADDR(0x3, 0x1)
127 #define R_SPKCRWDL VIRT_ADDR(0x3, 0x2)
128 #define R_SPKCRWDM VIRT_ADDR(0x3, 0x3)
129 #define R_SPKCRWDH VIRT_ADDR(0x3, 0x4)
130 #define R_SPKCRRDL VIRT_ADDR(0x3, 0x5)
131 #define R_SPKCRRDM VIRT_ADDR(0x3, 0x6)
132 #define R_SPKCRRDH VIRT_ADDR(0x3, 0x7)
[all …]
/openbmc/linux/drivers/clk/mmp/
H A Dclk-of-pxa168.c86 {PXA168_CLK_PLL1_6, "pll1_6", "pll1_2", 1, 3, 0},
95 {PXA168_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0},
97 {PXA168_CLK_PLL1_2_3_16, "pll1_2_3_16", "pll1_2", 3, 16, 0},
163 …arent_names, ARRAY_SIZE(twsi_parent_names), CLK_SET_RATE_PARENT, APBC_TWSI0, 4, 3, 0, &twsi0_lock},
164 …arent_names, ARRAY_SIZE(twsi_parent_names), CLK_SET_RATE_PARENT, APBC_TWSI1, 4, 3, 0, &twsi1_lock},
165 …{0, "kpc_mux", kpc_parent_names, ARRAY_SIZE(kpc_parent_names), CLK_SET_RATE_PARENT, APBC_KPC, 4, 3…
166 …m_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM0, 4, 3, 0, &pwm0_lock},
167 …m_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM1, 4, 3, 0, &pwm1_lock},
168 …m_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM2, 4, 3, 0, &pwm2_lock},
169 …m_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM3, 4, 3, 0, &pwm3_lock},
[all …]
H A Dclk-of-pxa910.c69 {PXA910_CLK_PLL1_6, "pll1_6", "pll1_2", 1, 3, 0},
76 {PXA910_CLK_PLL1_13_1_5, "pll1_13_1_5", "pll1_13", 2, 3, 0},
77 {PXA910_CLK_PLL1_2_1_5, "pll1_2_1_5", "pll1_2", 2, 3, 0},
78 {PXA910_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0},
128 …arent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
129 …arent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
130 …p_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
131 …p_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
132 …nt_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TIMER0, 4, 3, 0, &timer0_lock},
133 …nt_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TIMER1, 4, 3, 0, &timer1_lock},
[all …]
/openbmc/u-boot/drivers/sound/
H A Drt5677.h361 #define RT5677_MICBIAS1_OVTH_MASK (0x3 << 9)
370 #define RT5677_SLB_ADC4_MASK (0x3 << 6)
372 #define RT5677_SLB_ADC3_MASK (0x3 << 4)
374 #define RT5677_SLB_ADC2_MASK (0x3 << 2)
376 #define RT5677_SLB_ADC1_MASK (0x3 << 0)
391 /* Analog DAC1/2/3 Source Control (0x15) */
392 #define RT5677_ANA_DAC3_SRC_SEL_MASK (0x3 << 4)
394 #define RT5677_ANA_DAC1_2_SRC_SEL_MASK (0x3 << 0)
410 #define RT5677_M_DAC3_R_VOL (0x1 << 3)
411 #define RT5677_M_DAC3_R_VOL_SFT 3
[all …]
/openbmc/u-boot/doc/device-tree-bindings/pinctrl/
H A Dmarvell,mvebu-pinctrl.txt38 max-func = <3>;
40 * SPI0 [0-3]
44 /* 0 1 2 3 4 5 6 7 8 9 */
45 pin-func = < 3 3 3 3 3 3 0 0 0 0
46 0 3 0 0 0 0 0 0 0 3>;
76 /* 0 1 2 3 4 5 6 7 8 9 */
102 /* 0 1 2 3 4 5 6 7 8 9 */
103 pin-func = < 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3
104 0x3 0x3 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
/openbmc/linux/drivers/pinctrl/sunxi/
H A Dpinctrl-sun20i-d1.c22 SUNXI_FUNCTION(0x3, "ir"), /* TX */
33 SUNXI_FUNCTION(0x3, "i2s2_dout"), /* DOUT3 */
44 SUNXI_FUNCTION(0x3, "i2s2_dout"), /* DOUT2 */
51 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
55 SUNXI_FUNCTION(0x3, "i2s2_dout"), /* DOUT1 */
61 SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 3)),
66 SUNXI_FUNCTION(0x3, "i2s2_dout"), /* DOUT0 */
77 SUNXI_FUNCTION(0x3, "i2s2"), /* BCLK */
88 SUNXI_FUNCTION(0x3, "i2s2"), /* LRCK */
99 SUNXI_FUNCTION(0x3, "i2s2"), /* MCLK */
[all …]
H A Dpinctrl-sun6i-a31.c25 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
33 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
41 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
45 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
49 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
52 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
57 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
65 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
73 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
81 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/
H A Dcache.S32 mov x3, #0x3ff
33 and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */
39 /* x3 <- number of cache ways - 1 */
44 mov x6, x3 /* x6 <- working copy of #ways */
133 mrs x3, ctr_el0
134 lsr x3, x3, #16
135 and x3, x3, #0xf
137 lsl x2, x2, x3 /* cache line size */
140 sub x3, x2, #1
141 bic x0, x0, x3
[all …]
/openbmc/qemu/tests/tcg/i386/
H A Dtest-i386-fyl2x.c33 …{ 0x2.0a40b4bd6349d53p+14380L, -0x3.612a1cec52e70388p-14116L, -0xb.dd9637a24570d1ap-14104L, -0xb.d…
37 …{ 0x3.71cca195c06ba4d4p-6312L, -0xb.14b747fa4cc13d1p+5052L, 0x1.112301748a1cc83p+5068L, 0x1.112301…
46 …{ 0x3.0acd5bcfe0779bd4p+13040L, -0xe.d3cd27fc1c72a99p+11224L, -0x2.f35c6ed58511949p+11240L, -0x2.f…
48 …{ 0x8.97f4540aa7735bap+13532L, -0x3.b7afc1088aafbb28p-9804L, -0xc.48d1793ca776382p-9792L, -0xc.48d…
52 …{ 0x3.c980e98228764804p-5832L, 0x9.5de74e6eb71dccfp+1992L, -0xd.5513ed4865b07fep+2004L, -0xd.5513e…
58 …{ 0x2.7699390ee7b13a7cp+8364L, -0x1.d8cb9730c96f499p+432L, -0x3.c598297e793d4e98p+444L, -0x3.c5982…
69 …{ 0xd.32c71819b8fe7abp-1688L, -0x6.3d33ce38ee554b58p-14512L, 0x2.90c54596d3bf22ecp-14500L, 0x2.90c…
75 …{ 0x1.7bf51909429d7df2p-520L, -0x3.3d489a77c9f992fcp+5672L, 0x6.92a309adfd41fffp+5680L, 0x6.92a309…
81 …{ 0x5.f224f48169e0aea8p+4500L, -0x2.3e6bba4532dcfb74p-4984L, -0x2.77702ff129d7eb24p-4972L, -0x2.77…
82 …{ 0xf.ce42d087ed87c6dp-1636L, -0x3.b45d9ada75fad714p+4704L, 0x1.79de5728a407b37ap+4716L, 0x1.79de5…
[all …]
H A Dtest-i386-fyl2xp1.c28 …{ 0x1.31edb79669dd58b4p-4L, 0x6.c25439d8a5ce071p+14380L, 0xb.3d0da52c1f58af3p+14376L, 0xb.3d0da52c…
34 …{ 0x3.311f29ec8b38ef74p-4L, -0x3.9865a5505c3ae018p+8924L, -0xf.188d6a2bba06e17p+8920L, -0xf.188d6a…
39 …{ -0x4.64109ab4700cf108p-4L, 0x6.b8d96cb8e5f2d648p+6524L, -0x3.1c6e7c0e4e7a72cp+6524L, -0x3.1c6e7c…
40 …{ 0x3.e104f8db9c02bf08p-4L, -0x9.7b905723db3fe54p+10116L, -0x2.f83eb6c0529e814p+10116L, -0x2.f83eb…
41 …{ -0x3.906c6b45a9367874p-4L, -0x3.b4f349ff071caa64p-1868L, 0x1.5901debf0c548972p-1868L, 0x1.5901de…
43 …{ -0x1.422d05691d16c3c2p-4L, -0x3.b7afc1088aafbb28p+8056L, 0x7.07a7a145b32d0108p+8052L, 0x7.07a7a1…
44 …{ 0x3.005497260bfe3efcp-4L, 0x2.70b5fc4ea650b9d4p+13164L, 0x9.af1b9b78be96p+13160L, 0x9.af1b9b78be…
45 …{ -0x3.06e1d8ce558315f4p-4L, 0xd.35a31147278a276p+13452L, -0x3.ff1a81342b225bf4p+13452L, -0x3.ff1a…
49 …{ -0x3.f7c63bee23b61aep-4L, -0x1.a4746c335dbffc62p+13532L, 0xa.ce1e8b95a3cf783p+13528L, 0xa.ce1e8b…
51 …{ -0x4.0c0f16fccf171958p-4L, -0x3.809f02e6f0a4a7ccp-632L, 0x1.793819991e50c69p-632L, 0x1.793819991…
[all …]
H A Dtest-i386-fpatan.c11 { -__builtin_infl(), -1.0L, -0x3.243f6a8885a308d4p+0L, -0x3.243f6a8885a308dp+0L },
12 { -__builtin_infl(), -0.0L, -0x3.243f6a8885a308d4p+0L, -0x3.243f6a8885a308dp+0L },
13 { -__builtin_infl(), 0.0L, 0x3.243f6a8885a308dp+0L, 0x3.243f6a8885a308d4p+0L },
14 { -__builtin_infl(), 1.0L, 0x3.243f6a8885a308dp+0L, 0x3.243f6a8885a308d4p+0L },
17 { -1.0L, -0.0L, -0x3.243f6a8885a308d4p+0L, -0x3.243f6a8885a308dp+0L },
18 { -1.0L, 0.0L, 0x3.243f6a8885a308dp+0L, 0x3.243f6a8885a308d4p+0L },
22 { -0.0L, -0.0L, -0x3.243f6a8885a308d4p+0L, -0x3.243f6a8885a308dp+0L },
23 { -0.0L, 0.0L, 0x3.243f6a8885a308dp+0L, 0x3.243f6a8885a308d4p+0L },
44 …{ 0x5.51ee0c58f7fbf45p-4L, -0x3.a11abadbd605d354p-4L, -0x9.942ec5a1e6d706ap-4L, -0x9.942ec5a1e6d70…
48 …{ -0x8.3e49377820195c8p-4L, 0x7.ece8699d62a9f76p-4L, 0x2.6037dbebdbb2fd48p+0L, 0x2.6037dbebdbb2fd4…
[all …]
/openbmc/linux/drivers/usb/dwc2/
H A Dhw.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
32 #define GOTGCTL_VBVALOVAL BIT(3)
56 #define GAHBCFG_HBSTLEN_INCR4 3
90 #define GUSBCFG_PHYIF16 BIT(3)
91 #define GUSBCFG_PHYIF8 (0 << 3)
107 #define GRSTCTL_IN_TKNQ_FLSH BIT(3)
143 #define GINTSTS_SOF BIT(3)
157 #define GRXSTS_PKTSTS_OUTDONE 3
158 #define GRXSTS_PKTSTS_HCHIN_XFER_COMP 3
165 #define GRXSTS_DPID_MASK (0x3 << 15)
[all …]
/openbmc/qemu/include/hw/usb/
H A Ddwc2-regs.h1 /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */
20 * 3. The names of the above-listed copyright holders may not be used
83 #define GAHBCFG_HBSTLEN_INCR4 3
117 #define GUSBCFG_PHYIF16 BIT(3)
118 #define GUSBCFG_PHYIF8 (0 << 3)
133 #define GRSTCTL_IN_TKNQ_FLSH BIT(3)
169 #define GINTSTS_SOF BIT(3)
183 #define GRXSTS_PKTSTS_OUTDONE 3
184 #define GRXSTS_PKTSTS_HCHIN_XFER_COMP 3
191 #define GRXSTS_DPID_MASK (0x3 << 15)
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/
H A Dcnic_defs.h33 #define L5CM_RAMROD_CMD_ID_TCP_CONNECT (L5CM_RAMROD_CMD_ID_BASE + 3)
96 #define L4_KCQ_RAMROD_COMPLETION (0x1<<3) /* Everest only */
97 #define L4_KCQ_RAMROD_COMPLETION_SHIFT 3
110 #define L4_KCQ_RAMROD_COMPLETION (0x1<<3) /* Everest only */
111 #define L4_KCQ_RAMROD_COMPLETION_SHIFT 3
208 #define L4_KWQ_CONNECT_REQ1_RSRV (0x1F<<3)
209 #define L4_KWQ_CONNECT_REQ1_RSRV_SHIFT 3
218 #define L4_KWQ_CONNECT_REQ1_RSRV (0x1F<<3)
219 #define L4_KWQ_CONNECT_REQ1_RSRV_SHIFT 3
242 u8 rsrv1[3];
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx5/
H A Dcrm_regs.h91 #define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
92 #define MXC_CCM_CCSR_STEP_SEL(v) (((v) & 0x3) << 7)
93 #define MXC_CCM_CCSR_STEP_SEL_RD(r) (((r) >> 7) & 0x3)
95 #define MXC_CCM_CCSR_PLL2_DIV_PODF_MASK (0x3 << 5)
96 #define MXC_CCM_CCSR_PLL2_DIV_PODF(v) (((v) & 0x3) << 5)
97 #define MXC_CCM_CCSR_PLL2_DIV_PODF_RD(r) (((r) >> 5) & 0x3)
98 #define MXC_CCM_CCSR_PLL3_DIV_PODF_OFFSET 3
99 #define MXC_CCM_CCSR_PLL3_DIV_PODF_MASK (0x3 << 3)
100 #define MXC_CCM_CCSR_PLL3_DIV_PODF(v) (((v) & 0x3) << 3)
101 #define MXC_CCM_CCSR_PLL3_DIV_PODF_RD(r) (((r) >> 3) & 0x3)
[all …]

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