11f4d4ed6SAlexander Lobakin /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 3e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 4fe40a830SPrabhakar Kushwaha * Copyright (c) 2019-2021 Marvell International Ltd. 5fe56b9e6SYuval Mintz */ 6fe56b9e6SYuval Mintz 7fe56b9e6SYuval Mintz #ifndef _QED_HSI_H 8fe56b9e6SYuval Mintz #define _QED_HSI_H 9fe56b9e6SYuval Mintz 10fe56b9e6SYuval Mintz #include <linux/types.h> 11fe56b9e6SYuval Mintz #include <linux/io.h> 12fe56b9e6SYuval Mintz #include <linux/bitops.h> 13fe56b9e6SYuval Mintz #include <linux/delay.h> 14fe56b9e6SYuval Mintz #include <linux/kernel.h> 15fe56b9e6SYuval Mintz #include <linux/list.h> 16fe56b9e6SYuval Mintz #include <linux/slab.h> 17fe56b9e6SYuval Mintz #include <linux/qed/common_hsi.h> 187a9b6b8fSYuval Mintz #include <linux/qed/storage_common.h> 197a9b6b8fSYuval Mintz #include <linux/qed/tcp_common.h> 201e128c81SArun Easi #include <linux/qed/fcoe_common.h> 2125c089d7SYuval Mintz #include <linux/qed/eth_common.h> 227a9b6b8fSYuval Mintz #include <linux/qed/iscsi_common.h> 23897e87a1SShai Malin #include <linux/qed/nvmetcp_common.h> 2467b40dccSKalderon, Michal #include <linux/qed/iwarp_common.h> 257a9b6b8fSYuval Mintz #include <linux/qed/rdma_common.h> 267a9b6b8fSYuval Mintz #include <linux/qed/roce_common.h> 271e128c81SArun Easi #include <linux/qed/qed_fcoe_if.h> 28fe56b9e6SYuval Mintz 29fe56b9e6SYuval Mintz struct qed_hwfn; 30fe56b9e6SYuval Mintz struct qed_ptt; 31fe56b9e6SYuval Mintz 32a2e7699eSTomer Tayar /* Opcodes for the event ring */ 33fe56b9e6SYuval Mintz enum common_event_opcode { 34fe56b9e6SYuval Mintz COMMON_EVENT_PF_START, 35fe56b9e6SYuval Mintz COMMON_EVENT_PF_STOP, 361408cc1fSYuval Mintz COMMON_EVENT_VF_START, 370b55e27dSYuval Mintz COMMON_EVENT_VF_STOP, 3837bff2b9SYuval Mintz COMMON_EVENT_VF_PF_CHANNEL, 39351a4dedSYuval Mintz COMMON_EVENT_VF_FLR, 40351a4dedSYuval Mintz COMMON_EVENT_PF_UPDATE, 41fe40a830SPrabhakar Kushwaha COMMON_EVENT_FW_ERROR, 42351a4dedSYuval Mintz COMMON_EVENT_RL_UPDATE, 43fc48b7a6SYuval Mintz COMMON_EVENT_EMPTY, 44fe56b9e6SYuval Mintz MAX_COMMON_EVENT_OPCODE 45fe56b9e6SYuval Mintz }; 46fe56b9e6SYuval Mintz 47fe56b9e6SYuval Mintz /* Common Ramrod Command IDs */ 48fe56b9e6SYuval Mintz enum common_ramrod_cmd_id { 49fe56b9e6SYuval Mintz COMMON_RAMROD_UNUSED, 50351a4dedSYuval Mintz COMMON_RAMROD_PF_START, 51351a4dedSYuval Mintz COMMON_RAMROD_PF_STOP, 521408cc1fSYuval Mintz COMMON_RAMROD_VF_START, 530b55e27dSYuval Mintz COMMON_RAMROD_VF_STOP, 54464f6645SManish Chopra COMMON_RAMROD_PF_UPDATE, 55351a4dedSYuval Mintz COMMON_RAMROD_RL_UPDATE, 56fc48b7a6SYuval Mintz COMMON_RAMROD_EMPTY, 57fe56b9e6SYuval Mintz MAX_COMMON_RAMROD_CMD_ID 58fe56b9e6SYuval Mintz }; 59fe56b9e6SYuval Mintz 60a2e7699eSTomer Tayar /* How ll2 should deal with packet upon errors */ 61a2e7699eSTomer Tayar enum core_error_handle { 62a2e7699eSTomer Tayar LL2_DROP_PACKET, 63a2e7699eSTomer Tayar LL2_DO_NOTHING, 64a2e7699eSTomer Tayar LL2_ASSERT, 65a2e7699eSTomer Tayar MAX_CORE_ERROR_HANDLE 66a2e7699eSTomer Tayar }; 67a2e7699eSTomer Tayar 68a2e7699eSTomer Tayar /* Opcodes for the event ring */ 69a2e7699eSTomer Tayar enum core_event_opcode { 70a2e7699eSTomer Tayar CORE_EVENT_TX_QUEUE_START, 71a2e7699eSTomer Tayar CORE_EVENT_TX_QUEUE_STOP, 72a2e7699eSTomer Tayar CORE_EVENT_RX_QUEUE_START, 73a2e7699eSTomer Tayar CORE_EVENT_RX_QUEUE_STOP, 74a2e7699eSTomer Tayar CORE_EVENT_RX_QUEUE_FLUSH, 75da090917STomer Tayar CORE_EVENT_TX_QUEUE_UPDATE, 76997af5dfSMichal Kalderon CORE_EVENT_QUEUE_STATS_QUERY, 77a2e7699eSTomer Tayar MAX_CORE_EVENT_OPCODE 78a2e7699eSTomer Tayar }; 79a2e7699eSTomer Tayar 80a2e7699eSTomer Tayar /* The L4 pseudo checksum mode for Core */ 81a2e7699eSTomer Tayar enum core_l4_pseudo_checksum_mode { 82a2e7699eSTomer Tayar CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH, 83a2e7699eSTomer Tayar CORE_L4_PSEUDO_CSUM_ZERO_LENGTH, 84a2e7699eSTomer Tayar MAX_CORE_L4_PSEUDO_CHECKSUM_MODE 85a2e7699eSTomer Tayar }; 86a2e7699eSTomer Tayar 87fe40a830SPrabhakar Kushwaha /* LL2 SP error code */ 88fe40a830SPrabhakar Kushwaha enum core_ll2_error_code { 89fe40a830SPrabhakar Kushwaha LL2_OK = 0, 90fe40a830SPrabhakar Kushwaha LL2_ERROR, 91fe40a830SPrabhakar Kushwaha MAX_CORE_LL2_ERROR_CODE 92fe40a830SPrabhakar Kushwaha }; 93fe40a830SPrabhakar Kushwaha 94a2e7699eSTomer Tayar /* Light-L2 RX Producers in Tstorm RAM */ 95a2e7699eSTomer Tayar struct core_ll2_port_stats { 96a2e7699eSTomer Tayar struct regpair gsi_invalid_hdr; 97a2e7699eSTomer Tayar struct regpair gsi_invalid_pkt_length; 98a2e7699eSTomer Tayar struct regpair gsi_unsupported_pkt_typ; 99a2e7699eSTomer Tayar struct regpair gsi_crcchksm_error; 100a2e7699eSTomer Tayar }; 101a2e7699eSTomer Tayar 102997af5dfSMichal Kalderon /* LL2 TX Per Queue Stats */ 103a2e7699eSTomer Tayar struct core_ll2_pstorm_per_queue_stat { 104a2e7699eSTomer Tayar struct regpair sent_ucast_bytes; 105a2e7699eSTomer Tayar struct regpair sent_mcast_bytes; 106a2e7699eSTomer Tayar struct regpair sent_bcast_bytes; 107a2e7699eSTomer Tayar struct regpair sent_ucast_pkts; 108a2e7699eSTomer Tayar struct regpair sent_mcast_pkts; 109a2e7699eSTomer Tayar struct regpair sent_bcast_pkts; 110997af5dfSMichal Kalderon struct regpair error_drop_pkts; 111a2e7699eSTomer Tayar }; 112a2e7699eSTomer Tayar 113a2e7699eSTomer Tayar /* Light-L2 RX Producers in Tstorm RAM */ 114a2e7699eSTomer Tayar struct core_ll2_rx_prod { 115a2e7699eSTomer Tayar __le16 bd_prod; 116a2e7699eSTomer Tayar __le16 cqe_prod; 117a2e7699eSTomer Tayar }; 118a2e7699eSTomer Tayar 119a2e7699eSTomer Tayar struct core_ll2_tstorm_per_queue_stat { 120a2e7699eSTomer Tayar struct regpair packet_too_big_discard; 121a2e7699eSTomer Tayar struct regpair no_buff_discard; 122a2e7699eSTomer Tayar }; 123a2e7699eSTomer Tayar 124a2e7699eSTomer Tayar struct core_ll2_ustorm_per_queue_stat { 125a2e7699eSTomer Tayar struct regpair rcv_ucast_bytes; 126a2e7699eSTomer Tayar struct regpair rcv_mcast_bytes; 127a2e7699eSTomer Tayar struct regpair rcv_bcast_bytes; 128a2e7699eSTomer Tayar struct regpair rcv_ucast_pkts; 129a2e7699eSTomer Tayar struct regpair rcv_mcast_pkts; 130a2e7699eSTomer Tayar struct regpair rcv_bcast_pkts; 131a2e7699eSTomer Tayar }; 132a2e7699eSTomer Tayar 133fe40a830SPrabhakar Kushwaha struct core_ll2_rx_per_queue_stat { 134fe40a830SPrabhakar Kushwaha struct core_ll2_tstorm_per_queue_stat tstorm_stat; 135fe40a830SPrabhakar Kushwaha struct core_ll2_ustorm_per_queue_stat ustorm_stat; 136fe40a830SPrabhakar Kushwaha }; 137fe40a830SPrabhakar Kushwaha 138fe40a830SPrabhakar Kushwaha struct core_ll2_tx_per_queue_stat { 139fe40a830SPrabhakar Kushwaha struct core_ll2_pstorm_per_queue_stat pstorm_stat; 140fe40a830SPrabhakar Kushwaha }; 141fe40a830SPrabhakar Kushwaha 142997af5dfSMichal Kalderon /* Structure for doorbell data, in PWM mode, for RX producers update. */ 143997af5dfSMichal Kalderon struct core_pwm_prod_update_data { 144997af5dfSMichal Kalderon __le16 icid; /* internal CID */ 145997af5dfSMichal Kalderon u8 reserved0; 146997af5dfSMichal Kalderon u8 params; 147997af5dfSMichal Kalderon #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_MASK 0x3 148997af5dfSMichal Kalderon #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_SHIFT 0 149997af5dfSMichal Kalderon #define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_MASK 0x3F /* Set 0 */ 150997af5dfSMichal Kalderon #define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_SHIFT 2 151997af5dfSMichal Kalderon struct core_ll2_rx_prod prod; /* Producers */ 152997af5dfSMichal Kalderon }; 153997af5dfSMichal Kalderon 154fe40a830SPrabhakar Kushwaha /* Ramrod data for rx/tx queue statistics query ramrod */ 155fe40a830SPrabhakar Kushwaha struct core_queue_stats_query_ramrod_data { 156fe40a830SPrabhakar Kushwaha u8 rx_stat; 157fe40a830SPrabhakar Kushwaha u8 tx_stat; 158fe40a830SPrabhakar Kushwaha __le16 reserved[3]; 159fe40a830SPrabhakar Kushwaha struct regpair rx_stat_addr; 160fe40a830SPrabhakar Kushwaha struct regpair tx_stat_addr; 161fe40a830SPrabhakar Kushwaha }; 162fe40a830SPrabhakar Kushwaha 163a2e7699eSTomer Tayar /* Core Ramrod Command IDs (light L2) */ 164a2e7699eSTomer Tayar enum core_ramrod_cmd_id { 165a2e7699eSTomer Tayar CORE_RAMROD_UNUSED, 166a2e7699eSTomer Tayar CORE_RAMROD_RX_QUEUE_START, 167a2e7699eSTomer Tayar CORE_RAMROD_TX_QUEUE_START, 168a2e7699eSTomer Tayar CORE_RAMROD_RX_QUEUE_STOP, 169a2e7699eSTomer Tayar CORE_RAMROD_TX_QUEUE_STOP, 170a2e7699eSTomer Tayar CORE_RAMROD_RX_QUEUE_FLUSH, 171da090917STomer Tayar CORE_RAMROD_TX_QUEUE_UPDATE, 172997af5dfSMichal Kalderon CORE_RAMROD_QUEUE_STATS_QUERY, 173a2e7699eSTomer Tayar MAX_CORE_RAMROD_CMD_ID 174a2e7699eSTomer Tayar }; 175a2e7699eSTomer Tayar 176a2e7699eSTomer Tayar /* Core RX CQE Type for Light L2 */ 177a2e7699eSTomer Tayar enum core_roce_flavor_type { 178a2e7699eSTomer Tayar CORE_ROCE, 179a2e7699eSTomer Tayar CORE_RROCE, 180a2e7699eSTomer Tayar MAX_CORE_ROCE_FLAVOR_TYPE 181a2e7699eSTomer Tayar }; 182a2e7699eSTomer Tayar 183a2e7699eSTomer Tayar /* Specifies how ll2 should deal with packets errors: packet_too_big and 184a2e7699eSTomer Tayar * no_buff. 185a2e7699eSTomer Tayar */ 186a2e7699eSTomer Tayar struct core_rx_action_on_error { 187a2e7699eSTomer Tayar u8 error_type; 188a2e7699eSTomer Tayar #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3 189a2e7699eSTomer Tayar #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0 190a2e7699eSTomer Tayar #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3 191a2e7699eSTomer Tayar #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT 2 192a2e7699eSTomer Tayar #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF 193a2e7699eSTomer Tayar #define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT 4 194a2e7699eSTomer Tayar }; 195a2e7699eSTomer Tayar 196a2e7699eSTomer Tayar /* Core RX BD for Light L2 */ 197a2e7699eSTomer Tayar struct core_rx_bd { 198a2e7699eSTomer Tayar struct regpair addr; 199a2e7699eSTomer Tayar __le16 reserved[4]; 200a2e7699eSTomer Tayar }; 201a2e7699eSTomer Tayar 202a2e7699eSTomer Tayar /* Core RX CM offload BD for Light L2 */ 203a2e7699eSTomer Tayar struct core_rx_bd_with_buff_len { 204a2e7699eSTomer Tayar struct regpair addr; 205a2e7699eSTomer Tayar __le16 buff_length; 206a2e7699eSTomer Tayar __le16 reserved[3]; 207a2e7699eSTomer Tayar }; 208a2e7699eSTomer Tayar 209a2e7699eSTomer Tayar /* Core RX CM offload BD for Light L2 */ 210a2e7699eSTomer Tayar union core_rx_bd_union { 211a2e7699eSTomer Tayar struct core_rx_bd rx_bd; 212a2e7699eSTomer Tayar struct core_rx_bd_with_buff_len rx_bd_with_len; 213a2e7699eSTomer Tayar }; 214a2e7699eSTomer Tayar 215a2e7699eSTomer Tayar /* Opaque Data for Light L2 RX CQE */ 216a2e7699eSTomer Tayar struct core_rx_cqe_opaque_data { 217a2e7699eSTomer Tayar __le32 data[2]; 218a2e7699eSTomer Tayar }; 219a2e7699eSTomer Tayar 220a2e7699eSTomer Tayar /* Core RX CQE Type for Light L2 */ 221a2e7699eSTomer Tayar enum core_rx_cqe_type { 222a2e7699eSTomer Tayar CORE_RX_CQE_ILLEGAL_TYPE, 223a2e7699eSTomer Tayar CORE_RX_CQE_TYPE_REGULAR, 224a2e7699eSTomer Tayar CORE_RX_CQE_TYPE_GSI_OFFLOAD, 225a2e7699eSTomer Tayar CORE_RX_CQE_TYPE_SLOW_PATH, 226a2e7699eSTomer Tayar MAX_CORE_RX_CQE_TYPE 227a2e7699eSTomer Tayar }; 228a2e7699eSTomer Tayar 229a2e7699eSTomer Tayar /* Core RX CQE for Light L2 */ 230a2e7699eSTomer Tayar struct core_rx_fast_path_cqe { 231a2e7699eSTomer Tayar u8 type; 232a2e7699eSTomer Tayar u8 placement_offset; 233a2e7699eSTomer Tayar struct parsing_and_err_flags parse_flags; 234a2e7699eSTomer Tayar __le16 packet_length; 235a2e7699eSTomer Tayar __le16 vlan; 236a2e7699eSTomer Tayar struct core_rx_cqe_opaque_data opaque_data; 237a2e7699eSTomer Tayar struct parsing_err_flags err_flags; 238fe40a830SPrabhakar Kushwaha u8 packet_source; 239fe40a830SPrabhakar Kushwaha u8 reserved0; 240a2e7699eSTomer Tayar __le32 reserved1[3]; 241a2e7699eSTomer Tayar }; 242a2e7699eSTomer Tayar 243a2e7699eSTomer Tayar /* Core Rx CM offload CQE */ 244a2e7699eSTomer Tayar struct core_rx_gsi_offload_cqe { 245a2e7699eSTomer Tayar u8 type; 246a2e7699eSTomer Tayar u8 data_length_error; 247a2e7699eSTomer Tayar struct parsing_and_err_flags parse_flags; 248a2e7699eSTomer Tayar __le16 data_length; 249a2e7699eSTomer Tayar __le16 vlan; 250a2e7699eSTomer Tayar __le32 src_mac_addrhi; 251a2e7699eSTomer Tayar __le16 src_mac_addrlo; 252a2e7699eSTomer Tayar __le16 qp_id; 253da090917STomer Tayar __le32 src_qp; 2540500a70dSMichal Kalderon struct core_rx_cqe_opaque_data opaque_data; 255fe40a830SPrabhakar Kushwaha u8 packet_source; 256fe40a830SPrabhakar Kushwaha u8 reserved[3]; 257a2e7699eSTomer Tayar }; 258a2e7699eSTomer Tayar 259a2e7699eSTomer Tayar /* Core RX CQE for Light L2 */ 260a2e7699eSTomer Tayar struct core_rx_slow_path_cqe { 261a2e7699eSTomer Tayar u8 type; 262a2e7699eSTomer Tayar u8 ramrod_cmd_id; 263a2e7699eSTomer Tayar __le16 echo; 264a2e7699eSTomer Tayar struct core_rx_cqe_opaque_data opaque_data; 265a2e7699eSTomer Tayar __le32 reserved1[5]; 266a2e7699eSTomer Tayar }; 267a2e7699eSTomer Tayar 268a2e7699eSTomer Tayar /* Core RX CM offload BD for Light L2 */ 269a2e7699eSTomer Tayar union core_rx_cqe_union { 270a2e7699eSTomer Tayar struct core_rx_fast_path_cqe rx_cqe_fp; 271a2e7699eSTomer Tayar struct core_rx_gsi_offload_cqe rx_cqe_gsi; 272a2e7699eSTomer Tayar struct core_rx_slow_path_cqe rx_cqe_sp; 273a2e7699eSTomer Tayar }; 274a2e7699eSTomer Tayar 275fe40a830SPrabhakar Kushwaha /* RX packet source. */ 276fe40a830SPrabhakar Kushwaha enum core_rx_pkt_source { 277fe40a830SPrabhakar Kushwaha CORE_RX_PKT_SOURCE_NETWORK = 0, 278fe40a830SPrabhakar Kushwaha CORE_RX_PKT_SOURCE_LB, 279fe40a830SPrabhakar Kushwaha CORE_RX_PKT_SOURCE_TX, 280fe40a830SPrabhakar Kushwaha CORE_RX_PKT_SOURCE_LL2_TX, 281fe40a830SPrabhakar Kushwaha MAX_CORE_RX_PKT_SOURCE 282fe40a830SPrabhakar Kushwaha }; 283fe40a830SPrabhakar Kushwaha 284a2e7699eSTomer Tayar /* Ramrod data for rx queue start ramrod */ 285a2e7699eSTomer Tayar struct core_rx_start_ramrod_data { 286a2e7699eSTomer Tayar struct regpair bd_base; 287a2e7699eSTomer Tayar struct regpair cqe_pbl_addr; 288a2e7699eSTomer Tayar __le16 mtu; 289a2e7699eSTomer Tayar __le16 sb_id; 290a2e7699eSTomer Tayar u8 sb_index; 291a2e7699eSTomer Tayar u8 complete_cqe_flg; 292a2e7699eSTomer Tayar u8 complete_event_flg; 293a2e7699eSTomer Tayar u8 drop_ttl0_flg; 294a2e7699eSTomer Tayar __le16 num_of_pbl_pages; 295da090917STomer Tayar u8 inner_vlan_stripping_en; 296da090917STomer Tayar u8 report_outer_vlan; 297a2e7699eSTomer Tayar u8 queue_id; 298a2e7699eSTomer Tayar u8 main_func_queue; 299a2e7699eSTomer Tayar u8 mf_si_bcast_accept_all; 300a2e7699eSTomer Tayar u8 mf_si_mcast_accept_all; 301a2e7699eSTomer Tayar struct core_rx_action_on_error action_on_error; 302a2e7699eSTomer Tayar u8 gsi_offload_flag; 303997af5dfSMichal Kalderon u8 vport_id_valid; 304997af5dfSMichal Kalderon u8 vport_id; 305997af5dfSMichal Kalderon u8 zero_prod_flg; 306a3f72307SDenis Bolotin u8 wipe_inner_vlan_pri_en; 307997af5dfSMichal Kalderon u8 reserved[2]; 308a2e7699eSTomer Tayar }; 309a2e7699eSTomer Tayar 310a2e7699eSTomer Tayar /* Ramrod data for rx queue stop ramrod */ 311a2e7699eSTomer Tayar struct core_rx_stop_ramrod_data { 312a2e7699eSTomer Tayar u8 complete_cqe_flg; 313a2e7699eSTomer Tayar u8 complete_event_flg; 314a2e7699eSTomer Tayar u8 queue_id; 315a2e7699eSTomer Tayar u8 reserved1; 316a2e7699eSTomer Tayar __le16 reserved2[2]; 317a2e7699eSTomer Tayar }; 318a2e7699eSTomer Tayar 319a2e7699eSTomer Tayar /* Flags for Core TX BD */ 320a2e7699eSTomer Tayar struct core_tx_bd_data { 321a2e7699eSTomer Tayar __le16 as_bitfield; 322a2e7699eSTomer Tayar #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1 323a2e7699eSTomer Tayar #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0 324a2e7699eSTomer Tayar #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1 325a2e7699eSTomer Tayar #define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT 1 326a2e7699eSTomer Tayar #define CORE_TX_BD_DATA_START_BD_MASK 0x1 327a2e7699eSTomer Tayar #define CORE_TX_BD_DATA_START_BD_SHIFT 2 328a2e7699eSTomer Tayar #define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1 329a2e7699eSTomer Tayar #define CORE_TX_BD_DATA_IP_CSUM_SHIFT 3 330a2e7699eSTomer Tayar #define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1 331a2e7699eSTomer Tayar #define CORE_TX_BD_DATA_L4_CSUM_SHIFT 4 332a2e7699eSTomer Tayar #define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1 333a2e7699eSTomer Tayar #define CORE_TX_BD_DATA_IPV6_EXT_SHIFT 5 334a2e7699eSTomer Tayar #define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1 335a2e7699eSTomer Tayar #define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT 6 336a2e7699eSTomer Tayar #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK 0x1 337a2e7699eSTomer Tayar #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT 7 338a2e7699eSTomer Tayar #define CORE_TX_BD_DATA_NBDS_MASK 0xF 339a2e7699eSTomer Tayar #define CORE_TX_BD_DATA_NBDS_SHIFT 8 340a2e7699eSTomer Tayar #define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1 341a2e7699eSTomer Tayar #define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT 12 342a2e7699eSTomer Tayar #define CORE_TX_BD_DATA_IP_LEN_MASK 0x1 343a2e7699eSTomer Tayar #define CORE_TX_BD_DATA_IP_LEN_SHIFT 13 344da090917STomer Tayar #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_MASK 0x1 345da090917STomer Tayar #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_SHIFT 14 346da090917STomer Tayar #define CORE_TX_BD_DATA_RESERVED0_MASK 0x1 347da090917STomer Tayar #define CORE_TX_BD_DATA_RESERVED0_SHIFT 15 348a2e7699eSTomer Tayar }; 349a2e7699eSTomer Tayar 350a2e7699eSTomer Tayar /* Core TX BD for Light L2 */ 351a2e7699eSTomer Tayar struct core_tx_bd { 352a2e7699eSTomer Tayar struct regpair addr; 353a2e7699eSTomer Tayar __le16 nbytes; 354a2e7699eSTomer Tayar __le16 nw_vlan_or_lb_echo; 355a2e7699eSTomer Tayar struct core_tx_bd_data bd_data; 356a2e7699eSTomer Tayar __le16 bitfield1; 357a2e7699eSTomer Tayar #define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF 358a2e7699eSTomer Tayar #define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0 359a2e7699eSTomer Tayar #define CORE_TX_BD_TX_DST_MASK 0x3 360a2e7699eSTomer Tayar #define CORE_TX_BD_TX_DST_SHIFT 14 361a2e7699eSTomer Tayar }; 362a2e7699eSTomer Tayar 363a2e7699eSTomer Tayar /* Light L2 TX Destination */ 364a2e7699eSTomer Tayar enum core_tx_dest { 365a2e7699eSTomer Tayar CORE_TX_DEST_NW, 366a2e7699eSTomer Tayar CORE_TX_DEST_LB, 367a2e7699eSTomer Tayar CORE_TX_DEST_RESERVED, 368a2e7699eSTomer Tayar CORE_TX_DEST_DROP, 369a2e7699eSTomer Tayar MAX_CORE_TX_DEST 370a2e7699eSTomer Tayar }; 371a2e7699eSTomer Tayar 372a2e7699eSTomer Tayar /* Ramrod data for tx queue start ramrod */ 373a2e7699eSTomer Tayar struct core_tx_start_ramrod_data { 374a2e7699eSTomer Tayar struct regpair pbl_base_addr; 375a2e7699eSTomer Tayar __le16 mtu; 376a2e7699eSTomer Tayar __le16 sb_id; 377a2e7699eSTomer Tayar u8 sb_index; 378a2e7699eSTomer Tayar u8 stats_en; 379a2e7699eSTomer Tayar u8 stats_id; 380a2e7699eSTomer Tayar u8 conn_type; 381a2e7699eSTomer Tayar __le16 pbl_size; 382a2e7699eSTomer Tayar __le16 qm_pq_id; 383a2e7699eSTomer Tayar u8 gsi_offload_flag; 384997af5dfSMichal Kalderon u8 ctx_stats_en; 385997af5dfSMichal Kalderon u8 vport_id_valid; 386a3f72307SDenis Bolotin u8 vport_id; 387997af5dfSMichal Kalderon u8 enforce_security_flag; 388997af5dfSMichal Kalderon u8 reserved[7]; 389a2e7699eSTomer Tayar }; 390a2e7699eSTomer Tayar 391a2e7699eSTomer Tayar /* Ramrod data for tx queue stop ramrod */ 392a2e7699eSTomer Tayar struct core_tx_stop_ramrod_data { 393a2e7699eSTomer Tayar __le32 reserved0[2]; 394a2e7699eSTomer Tayar }; 395a2e7699eSTomer Tayar 396da090917STomer Tayar /* Ramrod data for tx queue update ramrod */ 397da090917STomer Tayar struct core_tx_update_ramrod_data { 398da090917STomer Tayar u8 update_qm_pq_id_flg; 399da090917STomer Tayar u8 reserved0; 400da090917STomer Tayar __le16 qm_pq_id; 401fe40a830SPrabhakar Kushwaha __le32 reserved1[1]; 402da090917STomer Tayar }; 403da090917STomer Tayar 404a2e7699eSTomer Tayar /* Enum flag for what type of dcb data to update */ 405a2e7699eSTomer Tayar enum dcb_dscp_update_mode { 406a2e7699eSTomer Tayar DONT_UPDATE_DCB_DSCP, 407a2e7699eSTomer Tayar UPDATE_DCB, 408a2e7699eSTomer Tayar UPDATE_DSCP, 409a2e7699eSTomer Tayar UPDATE_DCB_DSCP, 410a2e7699eSTomer Tayar MAX_DCB_DSCP_UPDATE_MODE 411a2e7699eSTomer Tayar }; 412a2e7699eSTomer Tayar 413fe56b9e6SYuval Mintz /* The core storm context for the Ystorm */ 414fe56b9e6SYuval Mintz struct ystorm_core_conn_st_ctx { 415fe56b9e6SYuval Mintz __le32 reserved[4]; 416fe56b9e6SYuval Mintz }; 417fe56b9e6SYuval Mintz 418fe56b9e6SYuval Mintz /* The core storm context for the Pstorm */ 419fe56b9e6SYuval Mintz struct pstorm_core_conn_st_ctx { 4200500a70dSMichal Kalderon __le32 reserved[20]; 421fe56b9e6SYuval Mintz }; 422fe56b9e6SYuval Mintz 423fe56b9e6SYuval Mintz /* Core Slowpath Connection storm context of Xstorm */ 424fe56b9e6SYuval Mintz struct xstorm_core_conn_st_ctx { 425fe40a830SPrabhakar Kushwaha struct regpair spq_base_addr; 426fe40a830SPrabhakar Kushwaha __le32 reserved0[2]; 427351a4dedSYuval Mintz __le16 spq_cons; 428fe40a830SPrabhakar Kushwaha __le16 reserved1[111]; 429fe56b9e6SYuval Mintz }; 430fe56b9e6SYuval Mintz 431fb09a1edSShai Malin struct xstorm_core_conn_ag_ctx { 432351a4dedSYuval Mintz u8 reserved0; 433da090917STomer Tayar u8 state; 434fe56b9e6SYuval Mintz u8 flags0; 435fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 436fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 437fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1 438fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1 439fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1 440fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2 441fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 442fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 443fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1 444fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4 445fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1 446fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5 447fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1 448fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6 449fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1 450fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7 451fe56b9e6SYuval Mintz u8 flags1; 452fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1 453fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0 454fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1 455fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1 456fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1 457fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2 458fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1 459fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3 460fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1 461fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4 462fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1 463fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5 464fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 465fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 466fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 467fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 468fe56b9e6SYuval Mintz u8 flags2; 469fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 470fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0 471fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 472fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2 473fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 474fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4 475fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 476fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6 477fe56b9e6SYuval Mintz u8 flags3; 478fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 479fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0 480fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 481fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2 482fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 483fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4 484fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 485fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6 486fe56b9e6SYuval Mintz u8 flags4; 487fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 488fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0 489fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 490fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2 491fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 492fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4 493fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3 494fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6 495fe56b9e6SYuval Mintz u8 flags5; 496fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3 497fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0 498fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3 499fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2 500fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3 501fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4 502fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3 503fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6 504fe56b9e6SYuval Mintz u8 flags6; 505fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3 506fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0 507fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3 508fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2 509fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3 510fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4 511fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 512fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 513fe56b9e6SYuval Mintz u8 flags7; 514fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 515fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 516fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3 517fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2 518fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 519fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 520fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 521fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6 522fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 523fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7 524fe56b9e6SYuval Mintz u8 flags8; 525fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 526fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0 527fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 528fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1 529fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 530fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2 531fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 532fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3 533fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 534fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4 535fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 536fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5 537fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 538fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6 539fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 540fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7 541fe56b9e6SYuval Mintz u8 flags9; 542fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 543fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0 544fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1 545fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1 546fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1 547fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2 548fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1 549fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3 550fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1 551fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4 552fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1 553fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5 554fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1 555fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6 556fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1 557fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7 558fe56b9e6SYuval Mintz u8 flags10; 559fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 560fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 561fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 562fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 563fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 564fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 565fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1 566fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3 567fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 568fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 569fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1 570fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5 571fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1 572fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6 573fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1 574fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7 575fe56b9e6SYuval Mintz u8 flags11; 576fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1 577fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0 578fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1 579fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1 580fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 581fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 582fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 583fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3 584fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 585fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4 586fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 587fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5 588fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 589fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 590fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1 591fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7 592fe56b9e6SYuval Mintz u8 flags12; 593fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1 594fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0 595fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1 596fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1 597fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 598fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 599fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 600fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 601fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1 602fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4 603fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1 604fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5 605fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1 606fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6 607fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1 608fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7 609fe56b9e6SYuval Mintz u8 flags13; 610fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1 611fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0 612fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1 613fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1 614fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 615fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 616fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 617fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 618fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 619fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 620fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 621fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 622fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 623fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 624fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 625fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 626fe56b9e6SYuval Mintz u8 flags14; 627fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1 628fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0 629fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1 630fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1 631fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1 632fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2 633fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1 634fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3 635fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1 636fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4 637fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1 638fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5 639fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3 640fb09a1edSShai Malin #define XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6 641351a4dedSYuval Mintz u8 byte2; 642351a4dedSYuval Mintz __le16 physical_q0; 643351a4dedSYuval Mintz __le16 consolid_prod; 644351a4dedSYuval Mintz __le16 reserved16; 645351a4dedSYuval Mintz __le16 tx_bd_cons; 646351a4dedSYuval Mintz __le16 tx_bd_or_spq_prod; 64750bc60cbSMichal Kalderon __le16 updated_qm_pq_id; 648351a4dedSYuval Mintz __le16 conn_dpi; 649351a4dedSYuval Mintz u8 byte3; 650351a4dedSYuval Mintz u8 byte4; 651351a4dedSYuval Mintz u8 byte5; 652351a4dedSYuval Mintz u8 byte6; 653351a4dedSYuval Mintz __le32 reg0; 654351a4dedSYuval Mintz __le32 reg1; 655351a4dedSYuval Mintz __le32 reg2; 656351a4dedSYuval Mintz __le32 reg3; 657351a4dedSYuval Mintz __le32 reg4; 658351a4dedSYuval Mintz __le32 reg5; 659351a4dedSYuval Mintz __le32 reg6; 660351a4dedSYuval Mintz __le16 word7; 661351a4dedSYuval Mintz __le16 word8; 662351a4dedSYuval Mintz __le16 word9; 663351a4dedSYuval Mintz __le16 word10; 664351a4dedSYuval Mintz __le32 reg7; 665351a4dedSYuval Mintz __le32 reg8; 666351a4dedSYuval Mintz __le32 reg9; 667351a4dedSYuval Mintz u8 byte7; 668351a4dedSYuval Mintz u8 byte8; 669351a4dedSYuval Mintz u8 byte9; 670351a4dedSYuval Mintz u8 byte10; 671351a4dedSYuval Mintz u8 byte11; 672351a4dedSYuval Mintz u8 byte12; 673351a4dedSYuval Mintz u8 byte13; 674351a4dedSYuval Mintz u8 byte14; 675351a4dedSYuval Mintz u8 byte15; 6767b6859fbSMintz, Yuval u8 e5_reserved; 677351a4dedSYuval Mintz __le16 word11; 678351a4dedSYuval Mintz __le32 reg10; 679351a4dedSYuval Mintz __le32 reg11; 680351a4dedSYuval Mintz __le32 reg12; 681351a4dedSYuval Mintz __le32 reg13; 682351a4dedSYuval Mintz __le32 reg14; 683351a4dedSYuval Mintz __le32 reg15; 684351a4dedSYuval Mintz __le32 reg16; 685351a4dedSYuval Mintz __le32 reg17; 686351a4dedSYuval Mintz __le32 reg18; 687351a4dedSYuval Mintz __le32 reg19; 688351a4dedSYuval Mintz __le16 word12; 689351a4dedSYuval Mintz __le16 word13; 690351a4dedSYuval Mintz __le16 word14; 691351a4dedSYuval Mintz __le16 word15; 692fe56b9e6SYuval Mintz }; 693fe56b9e6SYuval Mintz 694fb09a1edSShai Malin struct tstorm_core_conn_ag_ctx { 695351a4dedSYuval Mintz u8 byte0; 696351a4dedSYuval Mintz u8 byte1; 697fc48b7a6SYuval Mintz u8 flags0; 698fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 699fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 700fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 701fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 702fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1 703fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2 704fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1 705fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3 706fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1 707fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4 708fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1 709fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5 710fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 711fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6 712fc48b7a6SYuval Mintz u8 flags1; 713fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 714fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0 715fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 716fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2 717fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 718fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4 719fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 720fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6 721fc48b7a6SYuval Mintz u8 flags2; 722fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 723fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0 724fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 725fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2 726fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 727fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4 728fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 729fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6 730fc48b7a6SYuval Mintz u8 flags3; 731fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 732fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0 733fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 734fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2 735fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 736fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4 737fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 738fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5 739fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 740fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6 741fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 742fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7 743fc48b7a6SYuval Mintz u8 flags4; 744fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 745fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0 746fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 747fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1 748fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 749fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2 750fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 751fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3 752fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 753fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4 754fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 755fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5 756fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 757fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6 758fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 759fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7 760fc48b7a6SYuval Mintz u8 flags5; 761fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 762fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0 763fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 764fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1 765fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 766fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2 767fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 768fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3 769fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 770fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4 771fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 772fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5 773fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 774fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6 775fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 776fb09a1edSShai Malin #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7 777351a4dedSYuval Mintz __le32 reg0; 778351a4dedSYuval Mintz __le32 reg1; 779351a4dedSYuval Mintz __le32 reg2; 780351a4dedSYuval Mintz __le32 reg3; 781351a4dedSYuval Mintz __le32 reg4; 782351a4dedSYuval Mintz __le32 reg5; 783351a4dedSYuval Mintz __le32 reg6; 784351a4dedSYuval Mintz __le32 reg7; 785351a4dedSYuval Mintz __le32 reg8; 786351a4dedSYuval Mintz u8 byte2; 787351a4dedSYuval Mintz u8 byte3; 788351a4dedSYuval Mintz __le16 word0; 789351a4dedSYuval Mintz u8 byte4; 790351a4dedSYuval Mintz u8 byte5; 791351a4dedSYuval Mintz __le16 word1; 792351a4dedSYuval Mintz __le16 word2; 793351a4dedSYuval Mintz __le16 word3; 794997af5dfSMichal Kalderon __le32 ll2_rx_prod; 795351a4dedSYuval Mintz __le32 reg10; 796fc48b7a6SYuval Mintz }; 797fc48b7a6SYuval Mintz 798fb09a1edSShai Malin struct ustorm_core_conn_ag_ctx { 799351a4dedSYuval Mintz u8 reserved; 800351a4dedSYuval Mintz u8 byte1; 801fc48b7a6SYuval Mintz u8 flags0; 802fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 803fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 804fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 805fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 806fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 807fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 808fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 809fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 810fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 811fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 812fc48b7a6SYuval Mintz u8 flags1; 813fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 814fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0 815fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 816fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2 817fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 818fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4 819fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 820fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6 821fc48b7a6SYuval Mintz u8 flags2; 822fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 823fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 824fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 825fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 826fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 827fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 828fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 829fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3 830fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 831fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4 832fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 833fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5 834fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 835fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6 836fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 837fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7 838fc48b7a6SYuval Mintz u8 flags3; 839fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 840fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0 841fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 842fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1 843fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 844fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2 845fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 846fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3 847fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 848fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4 849fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 850fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5 851fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 852fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6 853fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 854fb09a1edSShai Malin #define USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7 855351a4dedSYuval Mintz u8 byte2; 856351a4dedSYuval Mintz u8 byte3; 857351a4dedSYuval Mintz __le16 word0; 858351a4dedSYuval Mintz __le16 word1; 859351a4dedSYuval Mintz __le32 rx_producers; 860351a4dedSYuval Mintz __le32 reg1; 861351a4dedSYuval Mintz __le32 reg2; 862351a4dedSYuval Mintz __le32 reg3; 863351a4dedSYuval Mintz __le16 word2; 864351a4dedSYuval Mintz __le16 word3; 865fc48b7a6SYuval Mintz }; 866fc48b7a6SYuval Mintz 867fe56b9e6SYuval Mintz /* The core storm context for the Mstorm */ 868fe56b9e6SYuval Mintz struct mstorm_core_conn_st_ctx { 8690500a70dSMichal Kalderon __le32 reserved[40]; 870fe56b9e6SYuval Mintz }; 871fe56b9e6SYuval Mintz 872fe56b9e6SYuval Mintz /* The core storm context for the Ustorm */ 873fe56b9e6SYuval Mintz struct ustorm_core_conn_st_ctx { 8740500a70dSMichal Kalderon __le32 reserved[20]; 875fe56b9e6SYuval Mintz }; 876fe56b9e6SYuval Mintz 877997af5dfSMichal Kalderon /* The core storm context for the Tstorm */ 878997af5dfSMichal Kalderon struct tstorm_core_conn_st_ctx { 879997af5dfSMichal Kalderon __le32 reserved[4]; 880997af5dfSMichal Kalderon }; 881997af5dfSMichal Kalderon 882fe56b9e6SYuval Mintz /* core connection context */ 883fb09a1edSShai Malin struct core_conn_context { 884fe56b9e6SYuval Mintz struct ystorm_core_conn_st_ctx ystorm_st_context; 885351a4dedSYuval Mintz struct regpair ystorm_st_padding[2]; 886fe56b9e6SYuval Mintz struct pstorm_core_conn_st_ctx pstorm_st_context; 887fe56b9e6SYuval Mintz struct regpair pstorm_st_padding[2]; 888fe56b9e6SYuval Mintz struct xstorm_core_conn_st_ctx xstorm_st_context; 889fb09a1edSShai Malin struct xstorm_core_conn_ag_ctx xstorm_ag_context; 890fb09a1edSShai Malin struct tstorm_core_conn_ag_ctx tstorm_ag_context; 891fb09a1edSShai Malin struct ustorm_core_conn_ag_ctx ustorm_ag_context; 892fe56b9e6SYuval Mintz struct mstorm_core_conn_st_ctx mstorm_st_context; 893fe56b9e6SYuval Mintz struct ustorm_core_conn_st_ctx ustorm_st_context; 894351a4dedSYuval Mintz struct regpair ustorm_st_padding[2]; 895997af5dfSMichal Kalderon struct tstorm_core_conn_st_ctx tstorm_st_context; 896997af5dfSMichal Kalderon struct regpair tstorm_st_padding[2]; 897351a4dedSYuval Mintz }; 898351a4dedSYuval Mintz 899351a4dedSYuval Mintz struct eth_mstorm_per_pf_stat { 900351a4dedSYuval Mintz struct regpair gre_discard_pkts; 901351a4dedSYuval Mintz struct regpair vxlan_discard_pkts; 902351a4dedSYuval Mintz struct regpair geneve_discard_pkts; 903351a4dedSYuval Mintz struct regpair lb_discard_pkts; 904fe56b9e6SYuval Mintz }; 905fe56b9e6SYuval Mintz 9069df2ed04SManish Chopra struct eth_mstorm_per_queue_stat { 9079df2ed04SManish Chopra struct regpair ttl0_discard; 9089df2ed04SManish Chopra struct regpair packet_too_big_discard; 9099df2ed04SManish Chopra struct regpair no_buff_discard; 9109df2ed04SManish Chopra struct regpair not_active_discard; 9119df2ed04SManish Chopra struct regpair tpa_coalesced_pkts; 9129df2ed04SManish Chopra struct regpair tpa_coalesced_events; 9139df2ed04SManish Chopra struct regpair tpa_aborts_num; 9149df2ed04SManish Chopra struct regpair tpa_coalesced_bytes; 9159df2ed04SManish Chopra }; 9169df2ed04SManish Chopra 917351a4dedSYuval Mintz /* Ethernet TX Per PF */ 918351a4dedSYuval Mintz struct eth_pstorm_per_pf_stat { 919351a4dedSYuval Mintz struct regpair sent_lb_ucast_bytes; 920351a4dedSYuval Mintz struct regpair sent_lb_mcast_bytes; 921351a4dedSYuval Mintz struct regpair sent_lb_bcast_bytes; 922351a4dedSYuval Mintz struct regpair sent_lb_ucast_pkts; 923351a4dedSYuval Mintz struct regpair sent_lb_mcast_pkts; 924351a4dedSYuval Mintz struct regpair sent_lb_bcast_pkts; 925351a4dedSYuval Mintz struct regpair sent_gre_bytes; 926351a4dedSYuval Mintz struct regpair sent_vxlan_bytes; 927351a4dedSYuval Mintz struct regpair sent_geneve_bytes; 9280500a70dSMichal Kalderon struct regpair sent_mpls_bytes; 9290500a70dSMichal Kalderon struct regpair sent_gre_mpls_bytes; 9300500a70dSMichal Kalderon struct regpair sent_udp_mpls_bytes; 931351a4dedSYuval Mintz struct regpair sent_gre_pkts; 932351a4dedSYuval Mintz struct regpair sent_vxlan_pkts; 933351a4dedSYuval Mintz struct regpair sent_geneve_pkts; 9340500a70dSMichal Kalderon struct regpair sent_mpls_pkts; 9350500a70dSMichal Kalderon struct regpair sent_gre_mpls_pkts; 9360500a70dSMichal Kalderon struct regpair sent_udp_mpls_pkts; 937351a4dedSYuval Mintz struct regpair gre_drop_pkts; 938351a4dedSYuval Mintz struct regpair vxlan_drop_pkts; 939351a4dedSYuval Mintz struct regpair geneve_drop_pkts; 9400500a70dSMichal Kalderon struct regpair mpls_drop_pkts; 9410500a70dSMichal Kalderon struct regpair gre_mpls_drop_pkts; 9420500a70dSMichal Kalderon struct regpair udp_mpls_drop_pkts; 943351a4dedSYuval Mintz }; 944351a4dedSYuval Mintz 945351a4dedSYuval Mintz /* Ethernet TX Per Queue Stats */ 9469df2ed04SManish Chopra struct eth_pstorm_per_queue_stat { 9479df2ed04SManish Chopra struct regpair sent_ucast_bytes; 9489df2ed04SManish Chopra struct regpair sent_mcast_bytes; 9499df2ed04SManish Chopra struct regpair sent_bcast_bytes; 9509df2ed04SManish Chopra struct regpair sent_ucast_pkts; 9519df2ed04SManish Chopra struct regpair sent_mcast_pkts; 9529df2ed04SManish Chopra struct regpair sent_bcast_pkts; 9539df2ed04SManish Chopra struct regpair error_drop_pkts; 9549df2ed04SManish Chopra }; 9559df2ed04SManish Chopra 956351a4dedSYuval Mintz /* ETH Rx producers data */ 957351a4dedSYuval Mintz struct eth_rx_rate_limit { 958351a4dedSYuval Mintz __le16 mult; 959351a4dedSYuval Mintz __le16 cnst; 960351a4dedSYuval Mintz u8 add_sub_cnst; 961351a4dedSYuval Mintz u8 reserved0; 962351a4dedSYuval Mintz __le16 reserved1; 963351a4dedSYuval Mintz }; 964351a4dedSYuval Mintz 965a3f72307SDenis Bolotin /* Update RSS indirection table entry command */ 966a3f72307SDenis Bolotin struct eth_tstorm_rss_update_data { 967a3f72307SDenis Bolotin u8 vport_id; 968a3f72307SDenis Bolotin u8 ind_table_index; 969a3f72307SDenis Bolotin __le16 ind_table_value; 970a3f72307SDenis Bolotin __le16 reserved1; 971fe40a830SPrabhakar Kushwaha u8 reserved; 972fe40a830SPrabhakar Kushwaha u8 valid; 973a3f72307SDenis Bolotin }; 974a3f72307SDenis Bolotin 975351a4dedSYuval Mintz struct eth_ustorm_per_pf_stat { 976351a4dedSYuval Mintz struct regpair rcv_lb_ucast_bytes; 977351a4dedSYuval Mintz struct regpair rcv_lb_mcast_bytes; 978351a4dedSYuval Mintz struct regpair rcv_lb_bcast_bytes; 979351a4dedSYuval Mintz struct regpair rcv_lb_ucast_pkts; 980351a4dedSYuval Mintz struct regpair rcv_lb_mcast_pkts; 981351a4dedSYuval Mintz struct regpair rcv_lb_bcast_pkts; 982351a4dedSYuval Mintz struct regpair rcv_gre_bytes; 983351a4dedSYuval Mintz struct regpair rcv_vxlan_bytes; 984351a4dedSYuval Mintz struct regpair rcv_geneve_bytes; 985351a4dedSYuval Mintz struct regpair rcv_gre_pkts; 986351a4dedSYuval Mintz struct regpair rcv_vxlan_pkts; 987351a4dedSYuval Mintz struct regpair rcv_geneve_pkts; 988351a4dedSYuval Mintz }; 989351a4dedSYuval Mintz 9909df2ed04SManish Chopra struct eth_ustorm_per_queue_stat { 9919df2ed04SManish Chopra struct regpair rcv_ucast_bytes; 9929df2ed04SManish Chopra struct regpair rcv_mcast_bytes; 9939df2ed04SManish Chopra struct regpair rcv_bcast_bytes; 9949df2ed04SManish Chopra struct regpair rcv_ucast_pkts; 9959df2ed04SManish Chopra struct regpair rcv_mcast_pkts; 9969df2ed04SManish Chopra struct regpair rcv_bcast_pkts; 9979df2ed04SManish Chopra }; 9989df2ed04SManish Chopra 999a2e7699eSTomer Tayar /* Event Ring VF-PF Channel data */ 1000a2e7699eSTomer Tayar struct vf_pf_channel_eqe_data { 1001a2e7699eSTomer Tayar struct regpair msg_addr; 1002a2e7699eSTomer Tayar }; 1003a2e7699eSTomer Tayar 1004a2e7699eSTomer Tayar /* Event Ring initial cleanup data */ 1005a2e7699eSTomer Tayar struct initial_cleanup_eqe_data { 1006a2e7699eSTomer Tayar u8 vf_id; 1007a2e7699eSTomer Tayar u8 reserved[7]; 1008a2e7699eSTomer Tayar }; 1009a2e7699eSTomer Tayar 1010fe40a830SPrabhakar Kushwaha /* FW error data */ 1011fe40a830SPrabhakar Kushwaha struct fw_err_data { 1012fe40a830SPrabhakar Kushwaha u8 recovery_scope; 1013fe40a830SPrabhakar Kushwaha u8 err_id; 1014fe40a830SPrabhakar Kushwaha __le16 entity_id; 1015fe40a830SPrabhakar Kushwaha u8 reserved[4]; 1016fe40a830SPrabhakar Kushwaha }; 1017fe40a830SPrabhakar Kushwaha 1018a2e7699eSTomer Tayar /* Event Data Union */ 1019a2e7699eSTomer Tayar union event_ring_data { 1020a2e7699eSTomer Tayar u8 bytes[8]; 1021a2e7699eSTomer Tayar struct vf_pf_channel_eqe_data vf_pf_channel; 1022a2e7699eSTomer Tayar struct iscsi_eqe_data iscsi_info; 1023da090917STomer Tayar struct iscsi_connect_done_results iscsi_conn_done_info; 1024a2e7699eSTomer Tayar union rdma_eqe_data rdma_data; 1025a2e7699eSTomer Tayar struct initial_cleanup_eqe_data vf_init_cleanup; 1026fe40a830SPrabhakar Kushwaha struct fw_err_data err_data; 1027a2e7699eSTomer Tayar }; 1028a2e7699eSTomer Tayar 1029a2e7699eSTomer Tayar /* Event Ring Entry */ 1030a2e7699eSTomer Tayar struct event_ring_entry { 1031a2e7699eSTomer Tayar u8 protocol_id; 1032a2e7699eSTomer Tayar u8 opcode; 10330500a70dSMichal Kalderon u8 reserved0; 10340500a70dSMichal Kalderon u8 vf_id; 1035a2e7699eSTomer Tayar __le16 echo; 1036a2e7699eSTomer Tayar u8 fw_return_code; 1037a2e7699eSTomer Tayar u8 flags; 1038a2e7699eSTomer Tayar #define EVENT_RING_ENTRY_ASYNC_MASK 0x1 1039a2e7699eSTomer Tayar #define EVENT_RING_ENTRY_ASYNC_SHIFT 0 1040a2e7699eSTomer Tayar #define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F 1041a2e7699eSTomer Tayar #define EVENT_RING_ENTRY_RESERVED1_SHIFT 1 1042a2e7699eSTomer Tayar union event_ring_data data; 1043a2e7699eSTomer Tayar }; 1044a2e7699eSTomer Tayar 1045fe56b9e6SYuval Mintz /* Event Ring Next Page Address */ 1046fe56b9e6SYuval Mintz struct event_ring_next_addr { 1047351a4dedSYuval Mintz struct regpair addr; 1048351a4dedSYuval Mintz __le32 reserved[2]; 1049fe56b9e6SYuval Mintz }; 1050fe56b9e6SYuval Mintz 1051351a4dedSYuval Mintz /* Event Ring Element */ 1052fe56b9e6SYuval Mintz union event_ring_element { 1053351a4dedSYuval Mintz struct event_ring_entry entry; 1054fe56b9e6SYuval Mintz struct event_ring_next_addr next_addr; 1055fe56b9e6SYuval Mintz }; 1056fe56b9e6SYuval Mintz 1057a2e7699eSTomer Tayar /* Ports mode */ 1058be086e7cSMintz, Yuval enum fw_flow_ctrl_mode { 1059be086e7cSMintz, Yuval flow_ctrl_pause, 1060be086e7cSMintz, Yuval flow_ctrl_pfc, 1061be086e7cSMintz, Yuval MAX_FW_FLOW_CTRL_MODE 1062be086e7cSMintz, Yuval }; 1063be086e7cSMintz, Yuval 1064da090917STomer Tayar /* GFT profile type */ 1065da090917STomer Tayar enum gft_profile_type { 1066da090917STomer Tayar GFT_PROFILE_TYPE_4_TUPLE, 1067da090917STomer Tayar GFT_PROFILE_TYPE_L4_DST_PORT, 106850bc60cbSMichal Kalderon GFT_PROFILE_TYPE_IP_DST_ADDR, 106950bc60cbSMichal Kalderon GFT_PROFILE_TYPE_IP_SRC_ADDR, 107050bc60cbSMichal Kalderon GFT_PROFILE_TYPE_TUNNEL_TYPE, 1071da090917STomer Tayar MAX_GFT_PROFILE_TYPE 1072da090917STomer Tayar }; 1073da090917STomer Tayar 1074351a4dedSYuval Mintz /* Major and Minor hsi Versions */ 1075351a4dedSYuval Mintz struct hsi_fp_ver_struct { 1076351a4dedSYuval Mintz u8 minor_ver_arr[2]; 1077351a4dedSYuval Mintz u8 major_ver_arr[2]; 1078351a4dedSYuval Mintz }; 1079351a4dedSYuval Mintz 1080fe40a830SPrabhakar Kushwaha /* Integration Phase */ 1081fe40a830SPrabhakar Kushwaha enum integ_phase { 1082fe40a830SPrabhakar Kushwaha INTEG_PHASE_BB_A0_LATEST = 3, 1083fe40a830SPrabhakar Kushwaha INTEG_PHASE_BB_B0_NO_MCP = 10, 1084fe40a830SPrabhakar Kushwaha INTEG_PHASE_BB_B0_WITH_MCP = 11, 1085fe40a830SPrabhakar Kushwaha MAX_INTEG_PHASE 1086fe40a830SPrabhakar Kushwaha }; 1087fe40a830SPrabhakar Kushwaha 1088fe40a830SPrabhakar Kushwaha /* Ports mode */ 10897b6859fbSMintz, Yuval enum iwarp_ll2_tx_queues { 10907b6859fbSMintz, Yuval IWARP_LL2_IN_ORDER_TX_QUEUE = 1, 10917b6859fbSMintz, Yuval IWARP_LL2_ALIGNED_TX_QUEUE, 10927b6859fbSMintz, Yuval IWARP_LL2_ALIGNED_RIGHT_TRIMMED_TX_QUEUE, 10937b6859fbSMintz, Yuval IWARP_LL2_ERROR, 10947b6859fbSMintz, Yuval MAX_IWARP_LL2_TX_QUEUES 10957b6859fbSMintz, Yuval }; 10967b6859fbSMintz, Yuval 1097fe40a830SPrabhakar Kushwaha /* Function error ID */ 1098fe40a830SPrabhakar Kushwaha enum func_err_id { 1099fe40a830SPrabhakar Kushwaha FUNC_NO_ERROR, 110005fafbfbSYuval Mintz VF_PF_CHANNEL_NOT_READY, 110105fafbfbSYuval Mintz VF_ZONE_MSG_NOT_VALID, 110205fafbfbSYuval Mintz VF_ZONE_FUNC_NOT_ENABLED, 110305fafbfbSYuval Mintz ETH_PACKET_TOO_SMALL, 110405fafbfbSYuval Mintz ETH_ILLEGAL_VLAN_MODE, 110505fafbfbSYuval Mintz ETH_MTU_VIOLATION, 110605fafbfbSYuval Mintz ETH_ILLEGAL_INBAND_TAGS, 110705fafbfbSYuval Mintz ETH_VLAN_INSERT_AND_INBAND_VLAN, 110805fafbfbSYuval Mintz ETH_ILLEGAL_NBDS, 110905fafbfbSYuval Mintz ETH_FIRST_BD_WO_SOP, 111005fafbfbSYuval Mintz ETH_INSUFFICIENT_BDS, 111105fafbfbSYuval Mintz ETH_ILLEGAL_LSO_HDR_NBDS, 111205fafbfbSYuval Mintz ETH_ILLEGAL_LSO_MSS, 111305fafbfbSYuval Mintz ETH_ZERO_SIZE_BD, 111405fafbfbSYuval Mintz ETH_ILLEGAL_LSO_HDR_LEN, 111505fafbfbSYuval Mintz ETH_INSUFFICIENT_PAYLOAD, 111605fafbfbSYuval Mintz ETH_EDPM_OUT_OF_SYNC, 111705fafbfbSYuval Mintz ETH_TUNN_IPV6_EXT_NBD_ERR, 111805fafbfbSYuval Mintz ETH_CONTROL_PACKET_VIOLATION, 1119be086e7cSMintz, Yuval ETH_ANTI_SPOOFING_ERR, 1120da090917STomer Tayar ETH_PACKET_SIZE_TOO_LARGE, 11210500a70dSMichal Kalderon CORE_ILLEGAL_VLAN_MODE, 11220500a70dSMichal Kalderon CORE_ILLEGAL_NBDS, 11230500a70dSMichal Kalderon CORE_FIRST_BD_WO_SOP, 11240500a70dSMichal Kalderon CORE_INSUFFICIENT_BDS, 11250500a70dSMichal Kalderon CORE_PACKET_TOO_SMALL, 11260500a70dSMichal Kalderon CORE_ILLEGAL_INBAND_TAGS, 11270500a70dSMichal Kalderon CORE_VLAN_INSERT_AND_INBAND_VLAN, 11280500a70dSMichal Kalderon CORE_MTU_VIOLATION, 11290500a70dSMichal Kalderon CORE_CONTROL_PACKET_VIOLATION, 11300500a70dSMichal Kalderon CORE_ANTI_SPOOFING_ERR, 11310500a70dSMichal Kalderon CORE_PACKET_SIZE_TOO_LARGE, 11320500a70dSMichal Kalderon CORE_ILLEGAL_BD_FLAGS, 11330500a70dSMichal Kalderon CORE_GSI_PACKET_VIOLATION, 1134fe40a830SPrabhakar Kushwaha MAX_FUNC_ERR_ID 1135fe40a830SPrabhakar Kushwaha }; 1136fe40a830SPrabhakar Kushwaha 1137fe40a830SPrabhakar Kushwaha /* FW error handling mode */ 1138fe40a830SPrabhakar Kushwaha enum fw_err_mode { 1139fe40a830SPrabhakar Kushwaha FW_ERR_FATAL_ASSERT, 1140fe40a830SPrabhakar Kushwaha FW_ERR_DRV_REPORT, 1141fe40a830SPrabhakar Kushwaha MAX_FW_ERR_MODE 1142fe40a830SPrabhakar Kushwaha }; 1143fe40a830SPrabhakar Kushwaha 1144fe40a830SPrabhakar Kushwaha /* FW error recovery scope */ 1145fe40a830SPrabhakar Kushwaha enum fw_err_recovery_scope { 1146fe40a830SPrabhakar Kushwaha ERR_SCOPE_INVALID, 1147fe40a830SPrabhakar Kushwaha ERR_SCOPE_TX_Q, 1148fe40a830SPrabhakar Kushwaha ERR_SCOPE_RX_Q, 1149fe40a830SPrabhakar Kushwaha ERR_SCOPE_QP, 1150fe40a830SPrabhakar Kushwaha ERR_SCOPE_VPORT, 1151fe40a830SPrabhakar Kushwaha ERR_SCOPE_FUNC, 1152fe40a830SPrabhakar Kushwaha ERR_SCOPE_PORT, 1153fe40a830SPrabhakar Kushwaha ERR_SCOPE_ENGINE, 1154fe40a830SPrabhakar Kushwaha MAX_FW_ERR_RECOVERY_SCOPE 115505fafbfbSYuval Mintz }; 115605fafbfbSYuval Mintz 1157a2e7699eSTomer Tayar /* Mstorm non-triggering VF zone */ 11581408cc1fSYuval Mintz struct mstorm_non_trigger_vf_zone { 11591408cc1fSYuval Mintz struct eth_mstorm_per_queue_stat eth_queue_stat; 1160484563e2SPrabhakar Kushwaha struct eth_rx_prod_data eth_rx_queue_producers[ETH_MAX_RXQ_VF_QUAD]; 11611408cc1fSYuval Mintz }; 11621408cc1fSYuval Mintz 1163351a4dedSYuval Mintz /* Mstorm VF zone */ 11641408cc1fSYuval Mintz struct mstorm_vf_zone { 11651408cc1fSYuval Mintz struct mstorm_non_trigger_vf_zone non_trigger; 11661408cc1fSYuval Mintz }; 11671408cc1fSYuval Mintz 1168da090917STomer Tayar /* vlan header including TPID and TCI fields */ 1169da090917STomer Tayar struct vlan_header { 1170da090917STomer Tayar __le16 tpid; 1171da090917STomer Tayar __le16 tci; 1172da090917STomer Tayar }; 1173da090917STomer Tayar 1174da090917STomer Tayar /* outer tag configurations */ 1175da090917STomer Tayar struct outer_tag_config_struct { 1176da090917STomer Tayar u8 enable_stag_pri_change; 1177da090917STomer Tayar u8 pri_map_valid; 1178da090917STomer Tayar u8 reserved[2]; 1179da090917STomer Tayar struct vlan_header outer_tag; 1180da090917STomer Tayar u8 inner_to_outer_pri_map[8]; 1181da090917STomer Tayar }; 1182da090917STomer Tayar 1183351a4dedSYuval Mintz /* personality per PF */ 1184fe56b9e6SYuval Mintz enum personality_type { 1185fc48b7a6SYuval Mintz BAD_PERSONALITY_TYP, 11861bd4f571SOmkar Kulkarni PERSONALITY_TCP_ULP, 11871e128c81SArun Easi PERSONALITY_FCOE, 1188351a4dedSYuval Mintz PERSONALITY_RDMA_AND_ETH, 11897b6859fbSMintz, Yuval PERSONALITY_RDMA, 1190fc48b7a6SYuval Mintz PERSONALITY_CORE, 1191351a4dedSYuval Mintz PERSONALITY_ETH, 1192a2e7699eSTomer Tayar PERSONALITY_RESERVED, 1193fe56b9e6SYuval Mintz MAX_PERSONALITY_TYPE 1194fe56b9e6SYuval Mintz }; 1195fe56b9e6SYuval Mintz 1196351a4dedSYuval Mintz /* tunnel configuration */ 1197fe56b9e6SYuval Mintz struct pf_start_tunnel_config { 1198fe56b9e6SYuval Mintz u8 set_vxlan_udp_port_flg; 1199fe56b9e6SYuval Mintz u8 set_geneve_udp_port_flg; 1200d52c89f1SMichal Kalderon u8 set_no_inner_l2_vxlan_udp_port_flg; 1201351a4dedSYuval Mintz u8 tunnel_clss_vxlan; 1202fe56b9e6SYuval Mintz u8 tunnel_clss_l2geneve; 1203fe56b9e6SYuval Mintz u8 tunnel_clss_ipgeneve; 1204fe56b9e6SYuval Mintz u8 tunnel_clss_l2gre; 1205fe56b9e6SYuval Mintz u8 tunnel_clss_ipgre; 1206351a4dedSYuval Mintz __le16 vxlan_udp_port; 1207351a4dedSYuval Mintz __le16 geneve_udp_port; 1208d52c89f1SMichal Kalderon __le16 no_inner_l2_vxlan_udp_port; 1209d52c89f1SMichal Kalderon __le16 reserved[3]; 1210fe56b9e6SYuval Mintz }; 1211fe56b9e6SYuval Mintz 1212fe56b9e6SYuval Mintz /* Ramrod data for PF start ramrod */ 1213fe56b9e6SYuval Mintz struct pf_start_ramrod_data { 1214fe56b9e6SYuval Mintz struct regpair event_ring_pbl_addr; 1215fe40a830SPrabhakar Kushwaha struct regpair consolid_q_pbl_base_addr; 1216fe56b9e6SYuval Mintz struct pf_start_tunnel_config tunnel_config; 1217fe56b9e6SYuval Mintz __le16 event_ring_sb_id; 1218fe56b9e6SYuval Mintz u8 base_vf_id; 1219fe56b9e6SYuval Mintz u8 num_vfs; 1220fe56b9e6SYuval Mintz u8 event_ring_num_pages; 1221fe56b9e6SYuval Mintz u8 event_ring_sb_index; 1222fe56b9e6SYuval Mintz u8 path_id; 1223fe56b9e6SYuval Mintz u8 warning_as_error; 1224fe56b9e6SYuval Mintz u8 dont_log_ramrods; 1225fe56b9e6SYuval Mintz u8 personality; 1226fe56b9e6SYuval Mintz __le16 log_type_mask; 1227351a4dedSYuval Mintz u8 mf_mode; 1228351a4dedSYuval Mintz u8 integ_phase; 1229fe56b9e6SYuval Mintz u8 allow_npar_tx_switching; 1230da090917STomer Tayar u8 reserved0; 1231351a4dedSYuval Mintz struct hsi_fp_ver_struct hsi_fp_ver; 1232da090917STomer Tayar struct outer_tag_config_struct outer_tag_config; 1233fe40a830SPrabhakar Kushwaha u8 pf_fp_err_mode; 1234fe40a830SPrabhakar Kushwaha u8 consolid_q_num_pages; 1235fe40a830SPrabhakar Kushwaha u8 reserved[6]; 1236fe56b9e6SYuval Mintz }; 1237fe56b9e6SYuval Mintz 1238a2e7699eSTomer Tayar /* Data for port update ramrod */ 123939651abdSSudarsana Reddy Kalluru struct protocol_dcb_data { 124039651abdSSudarsana Reddy Kalluru u8 dcb_enable_flag; 1241da090917STomer Tayar u8 dscp_enable_flag; 124239651abdSSudarsana Reddy Kalluru u8 dcb_priority; 124339651abdSSudarsana Reddy Kalluru u8 dcb_tc; 1244da090917STomer Tayar u8 dscp_val; 124550bc60cbSMichal Kalderon u8 dcb_dont_add_vlan0; 124639651abdSSudarsana Reddy Kalluru }; 124739651abdSSudarsana Reddy Kalluru 1248a2e7699eSTomer Tayar /* Update tunnel configuration */ 1249464f6645SManish Chopra struct pf_update_tunnel_config { 1250464f6645SManish Chopra u8 update_rx_pf_clss; 125105fafbfbSYuval Mintz u8 update_rx_def_ucast_clss; 125205fafbfbSYuval Mintz u8 update_rx_def_non_ucast_clss; 1253464f6645SManish Chopra u8 set_vxlan_udp_port_flg; 1254464f6645SManish Chopra u8 set_geneve_udp_port_flg; 1255d52c89f1SMichal Kalderon u8 set_no_inner_l2_vxlan_udp_port_flg; 1256464f6645SManish Chopra u8 tunnel_clss_vxlan; 1257464f6645SManish Chopra u8 tunnel_clss_l2geneve; 1258464f6645SManish Chopra u8 tunnel_clss_ipgeneve; 1259464f6645SManish Chopra u8 tunnel_clss_l2gre; 1260464f6645SManish Chopra u8 tunnel_clss_ipgre; 1261d52c89f1SMichal Kalderon u8 reserved; 1262464f6645SManish Chopra __le16 vxlan_udp_port; 1263464f6645SManish Chopra __le16 geneve_udp_port; 1264d52c89f1SMichal Kalderon __le16 no_inner_l2_vxlan_udp_port; 1265d52c89f1SMichal Kalderon __le16 reserved1[3]; 1266464f6645SManish Chopra }; 1267464f6645SManish Chopra 1268a2e7699eSTomer Tayar /* Data for port update ramrod */ 1269464f6645SManish Chopra struct pf_update_ramrod_data { 12707b6859fbSMintz, Yuval u8 update_eth_dcb_data_mode; 12717b6859fbSMintz, Yuval u8 update_fcoe_dcb_data_mode; 12727b6859fbSMintz, Yuval u8 update_iscsi_dcb_data_mode; 12737b6859fbSMintz, Yuval u8 update_roce_dcb_data_mode; 12747b6859fbSMintz, Yuval u8 update_rroce_dcb_data_mode; 12757b6859fbSMintz, Yuval u8 update_iwarp_dcb_data_mode; 127639651abdSSudarsana Reddy Kalluru u8 update_mf_vlan_flag; 1277da090917STomer Tayar u8 update_enable_stag_pri_change; 127839651abdSSudarsana Reddy Kalluru struct protocol_dcb_data eth_dcb_data; 127939651abdSSudarsana Reddy Kalluru struct protocol_dcb_data fcoe_dcb_data; 128039651abdSSudarsana Reddy Kalluru struct protocol_dcb_data iscsi_dcb_data; 128139651abdSSudarsana Reddy Kalluru struct protocol_dcb_data roce_dcb_data; 128205fafbfbSYuval Mintz struct protocol_dcb_data rroce_dcb_data; 1283351a4dedSYuval Mintz struct protocol_dcb_data iwarp_dcb_data; 1284351a4dedSYuval Mintz __le16 mf_vlan; 1285da090917STomer Tayar u8 enable_stag_pri_change; 1286da090917STomer Tayar u8 reserved; 1287464f6645SManish Chopra struct pf_update_tunnel_config tunnel_config; 1288464f6645SManish Chopra }; 1289464f6645SManish Chopra 1290351a4dedSYuval Mintz /* Ports mode */ 1291351a4dedSYuval Mintz enum ports_mode { 1292351a4dedSYuval Mintz ENGX2_PORTX1, 1293351a4dedSYuval Mintz ENGX2_PORTX2, 1294351a4dedSYuval Mintz ENGX1_PORTX1, 1295351a4dedSYuval Mintz ENGX1_PORTX2, 1296351a4dedSYuval Mintz ENGX1_PORTX4, 1297351a4dedSYuval Mintz MAX_PORTS_MODE 1298351a4dedSYuval Mintz }; 1299351a4dedSYuval Mintz 1300fe40a830SPrabhakar Kushwaha /* Protocol-common error code */ 1301fe40a830SPrabhakar Kushwaha enum protocol_common_error_code { 1302fe40a830SPrabhakar Kushwaha COMMON_ERR_CODE_OK = 0, 1303fe40a830SPrabhakar Kushwaha COMMON_ERR_CODE_ERROR, 1304fe40a830SPrabhakar Kushwaha MAX_PROTOCOL_COMMON_ERROR_CODE 1305fe40a830SPrabhakar Kushwaha }; 1306fe40a830SPrabhakar Kushwaha 1307351a4dedSYuval Mintz /* use to index in hsi_fp_[major|minor]_ver_arr per protocol */ 1308351a4dedSYuval Mintz enum protocol_version_array_key { 1309351a4dedSYuval Mintz ETH_VER_KEY = 0, 1310351a4dedSYuval Mintz ROCE_VER_KEY, 1311351a4dedSYuval Mintz MAX_PROTOCOL_VERSION_ARRAY_KEY 1312351a4dedSYuval Mintz }; 1313351a4dedSYuval Mintz 1314a2e7699eSTomer Tayar /* RDMA TX Stats */ 131505fafbfbSYuval Mintz struct rdma_sent_stats { 131605fafbfbSYuval Mintz struct regpair sent_bytes; 131705fafbfbSYuval Mintz struct regpair sent_pkts; 131805fafbfbSYuval Mintz }; 131905fafbfbSYuval Mintz 1320a2e7699eSTomer Tayar /* Pstorm non-triggering VF zone */ 1321351a4dedSYuval Mintz struct pstorm_non_trigger_vf_zone { 1322351a4dedSYuval Mintz struct eth_pstorm_per_queue_stat eth_queue_stat; 132305fafbfbSYuval Mintz struct rdma_sent_stats rdma_stats; 1324351a4dedSYuval Mintz }; 1325351a4dedSYuval Mintz 1326351a4dedSYuval Mintz /* Pstorm VF zone */ 1327351a4dedSYuval Mintz struct pstorm_vf_zone { 1328351a4dedSYuval Mintz struct pstorm_non_trigger_vf_zone non_trigger; 1329351a4dedSYuval Mintz struct regpair reserved[7]; 1330351a4dedSYuval Mintz }; 1331351a4dedSYuval Mintz 1332351a4dedSYuval Mintz /* Ramrod Header of SPQE */ 1333351a4dedSYuval Mintz struct ramrod_header { 1334351a4dedSYuval Mintz __le32 cid; 1335351a4dedSYuval Mintz u8 cmd_id; 1336351a4dedSYuval Mintz u8 protocol_id; 1337351a4dedSYuval Mintz __le16 echo; 1338351a4dedSYuval Mintz }; 1339351a4dedSYuval Mintz 1340a2e7699eSTomer Tayar /* RDMA RX Stats */ 134105fafbfbSYuval Mintz struct rdma_rcv_stats { 134205fafbfbSYuval Mintz struct regpair rcv_bytes; 134305fafbfbSYuval Mintz struct regpair rcv_pkts; 134405fafbfbSYuval Mintz }; 134505fafbfbSYuval Mintz 1346da090917STomer Tayar /* Data for update QCN/DCQCN RL ramrod */ 1347da090917STomer Tayar struct rl_update_ramrod_data { 1348da090917STomer Tayar u8 qcn_update_param_flg; 1349da090917STomer Tayar u8 dcqcn_update_param_flg; 1350da090917STomer Tayar u8 rl_init_flg; 1351da090917STomer Tayar u8 rl_start_flg; 1352da090917STomer Tayar u8 rl_stop_flg; 1353da090917STomer Tayar u8 rl_id_first; 1354da090917STomer Tayar u8 rl_id_last; 1355da090917STomer Tayar u8 rl_dc_qcn_flg; 1356a3f72307SDenis Bolotin u8 dcqcn_reset_alpha_on_idle; 1357a3f72307SDenis Bolotin u8 rl_bc_stage_th; 1358a3f72307SDenis Bolotin u8 rl_timer_stage_th; 1359a3f72307SDenis Bolotin u8 reserved1; 1360da090917STomer Tayar __le32 rl_bc_rate; 1361da090917STomer Tayar __le16 rl_max_rate; 1362da090917STomer Tayar __le16 rl_r_ai; 1363da090917STomer Tayar __le16 rl_r_hai; 1364da090917STomer Tayar __le16 dcqcn_g; 1365da090917STomer Tayar __le32 dcqcn_k_us; 1366da090917STomer Tayar __le32 dcqcn_timeuot_us; 1367da090917STomer Tayar __le32 qcn_timeuot_us; 1368a3f72307SDenis Bolotin __le32 reserved2; 1369da090917STomer Tayar }; 1370da090917STomer Tayar 1371a2e7699eSTomer Tayar /* Slowpath Element (SPQE) */ 1372351a4dedSYuval Mintz struct slow_path_element { 1373351a4dedSYuval Mintz struct ramrod_header hdr; 1374351a4dedSYuval Mintz struct regpair data_ptr; 1375351a4dedSYuval Mintz }; 1376351a4dedSYuval Mintz 1377351a4dedSYuval Mintz /* Tstorm non-triggering VF zone */ 1378351a4dedSYuval Mintz struct tstorm_non_trigger_vf_zone { 137905fafbfbSYuval Mintz struct rdma_rcv_stats rdma_stats; 1380351a4dedSYuval Mintz }; 1381351a4dedSYuval Mintz 1382351a4dedSYuval Mintz struct tstorm_per_port_stat { 1383351a4dedSYuval Mintz struct regpair trunc_error_discard; 1384351a4dedSYuval Mintz struct regpair mac_error_discard; 1385351a4dedSYuval Mintz struct regpair mftag_filter_discard; 1386351a4dedSYuval Mintz struct regpair eth_mac_filter_discard; 138705fafbfbSYuval Mintz struct regpair ll2_mac_filter_discard; 138805fafbfbSYuval Mintz struct regpair ll2_conn_disabled_discard; 138905fafbfbSYuval Mintz struct regpair iscsi_irregular_pkt; 1390be086e7cSMintz, Yuval struct regpair fcoe_irregular_pkt; 139105fafbfbSYuval Mintz struct regpair roce_irregular_pkt; 13927b6859fbSMintz, Yuval struct regpair iwarp_irregular_pkt; 1393351a4dedSYuval Mintz struct regpair eth_irregular_pkt; 1394da090917STomer Tayar struct regpair toe_irregular_pkt; 139505fafbfbSYuval Mintz struct regpair preroce_irregular_pkt; 1396351a4dedSYuval Mintz struct regpair eth_gre_tunn_filter_discard; 1397351a4dedSYuval Mintz struct regpair eth_vxlan_tunn_filter_discard; 1398351a4dedSYuval Mintz struct regpair eth_geneve_tunn_filter_discard; 1399da090917STomer Tayar struct regpair eth_gft_drop_pkt; 1400351a4dedSYuval Mintz }; 1401351a4dedSYuval Mintz 1402351a4dedSYuval Mintz /* Tstorm VF zone */ 1403351a4dedSYuval Mintz struct tstorm_vf_zone { 1404351a4dedSYuval Mintz struct tstorm_non_trigger_vf_zone non_trigger; 1405351a4dedSYuval Mintz }; 1406351a4dedSYuval Mintz 1407464f6645SManish Chopra /* Tunnel classification scheme */ 1408464f6645SManish Chopra enum tunnel_clss { 1409464f6645SManish Chopra TUNNEL_CLSS_MAC_VLAN = 0, 1410464f6645SManish Chopra TUNNEL_CLSS_MAC_VNI, 1411464f6645SManish Chopra TUNNEL_CLSS_INNER_MAC_VLAN, 1412464f6645SManish Chopra TUNNEL_CLSS_INNER_MAC_VNI, 1413351a4dedSYuval Mintz TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE, 1414464f6645SManish Chopra MAX_TUNNEL_CLSS 1415464f6645SManish Chopra }; 1416464f6645SManish Chopra 1417351a4dedSYuval Mintz /* Ustorm non-triggering VF zone */ 14181408cc1fSYuval Mintz struct ustorm_non_trigger_vf_zone { 14191408cc1fSYuval Mintz struct eth_ustorm_per_queue_stat eth_queue_stat; 14201408cc1fSYuval Mintz struct regpair vf_pf_msg_addr; 14211408cc1fSYuval Mintz }; 14221408cc1fSYuval Mintz 1423351a4dedSYuval Mintz /* Ustorm triggering VF zone */ 14241408cc1fSYuval Mintz struct ustorm_trigger_vf_zone { 14251408cc1fSYuval Mintz u8 vf_pf_msg_valid; 14261408cc1fSYuval Mintz u8 reserved[7]; 14271408cc1fSYuval Mintz }; 14281408cc1fSYuval Mintz 1429351a4dedSYuval Mintz /* Ustorm VF zone */ 14301408cc1fSYuval Mintz struct ustorm_vf_zone { 14311408cc1fSYuval Mintz struct ustorm_non_trigger_vf_zone non_trigger; 14321408cc1fSYuval Mintz struct ustorm_trigger_vf_zone trigger; 14331408cc1fSYuval Mintz }; 14341408cc1fSYuval Mintz 1435351a4dedSYuval Mintz /* VF-PF channel data */ 1436351a4dedSYuval Mintz struct vf_pf_channel_data { 1437351a4dedSYuval Mintz __le32 ready; 1438351a4dedSYuval Mintz u8 valid; 1439351a4dedSYuval Mintz u8 reserved0; 1440351a4dedSYuval Mintz __le16 reserved1; 1441351a4dedSYuval Mintz }; 1442351a4dedSYuval Mintz 1443351a4dedSYuval Mintz /* Ramrod data for VF start ramrod */ 14441408cc1fSYuval Mintz struct vf_start_ramrod_data { 14451408cc1fSYuval Mintz u8 vf_id; 14461408cc1fSYuval Mintz u8 enable_flr_ack; 14471408cc1fSYuval Mintz __le16 opaque_fid; 14481408cc1fSYuval Mintz u8 personality; 1449351a4dedSYuval Mintz u8 reserved[7]; 1450351a4dedSYuval Mintz struct hsi_fp_ver_struct hsi_fp_ver; 1451351a4dedSYuval Mintz 14521408cc1fSYuval Mintz }; 14531408cc1fSYuval Mintz 1454351a4dedSYuval Mintz /* Ramrod data for VF start ramrod */ 14550b55e27dSYuval Mintz struct vf_stop_ramrod_data { 14560b55e27dSYuval Mintz u8 vf_id; 14570b55e27dSYuval Mintz u8 reserved0; 14580b55e27dSYuval Mintz __le16 reserved1; 14590b55e27dSYuval Mintz __le32 reserved2; 14600b55e27dSYuval Mintz }; 14610b55e27dSYuval Mintz 1462a2e7699eSTomer Tayar /* VF zone size mode */ 146305fafbfbSYuval Mintz enum vf_zone_size_mode { 146405fafbfbSYuval Mintz VF_ZONE_SIZE_MODE_DEFAULT, 146505fafbfbSYuval Mintz VF_ZONE_SIZE_MODE_DOUBLE, 146605fafbfbSYuval Mintz VF_ZONE_SIZE_MODE_QUAD, 146705fafbfbSYuval Mintz MAX_VF_ZONE_SIZE_MODE 146805fafbfbSYuval Mintz }; 146905fafbfbSYuval Mintz 14700500a70dSMichal Kalderon /* Xstorm non-triggering VF zone */ 14710500a70dSMichal Kalderon struct xstorm_non_trigger_vf_zone { 14720500a70dSMichal Kalderon struct regpair non_edpm_ack_pkts; 14730500a70dSMichal Kalderon }; 14740500a70dSMichal Kalderon 14750500a70dSMichal Kalderon /* Tstorm VF zone */ 14760500a70dSMichal Kalderon struct xstorm_vf_zone { 14770500a70dSMichal Kalderon struct xstorm_non_trigger_vf_zone non_trigger; 14780500a70dSMichal Kalderon }; 14790500a70dSMichal Kalderon 1480a2e7699eSTomer Tayar /* Attentions status block */ 1481fe56b9e6SYuval Mintz struct atten_status_block { 1482fe56b9e6SYuval Mintz __le32 atten_bits; 1483fe56b9e6SYuval Mintz __le32 atten_ack; 1484fe56b9e6SYuval Mintz __le16 reserved0; 1485351a4dedSYuval Mintz __le16 sb_index; 1486fe56b9e6SYuval Mintz __le32 reserved1; 1487fe56b9e6SYuval Mintz }; 1488fe56b9e6SYuval Mintz 1489351a4dedSYuval Mintz /* DMAE command */ 1490fe56b9e6SYuval Mintz struct dmae_cmd { 1491fe56b9e6SYuval Mintz __le32 opcode; 1492fe56b9e6SYuval Mintz #define DMAE_CMD_SRC_MASK 0x1 1493fe56b9e6SYuval Mintz #define DMAE_CMD_SRC_SHIFT 0 1494fe56b9e6SYuval Mintz #define DMAE_CMD_DST_MASK 0x3 1495fe56b9e6SYuval Mintz #define DMAE_CMD_DST_SHIFT 1 1496fe56b9e6SYuval Mintz #define DMAE_CMD_C_DST_MASK 0x1 1497fe56b9e6SYuval Mintz #define DMAE_CMD_C_DST_SHIFT 3 1498fe56b9e6SYuval Mintz #define DMAE_CMD_CRC_RESET_MASK 0x1 1499fe56b9e6SYuval Mintz #define DMAE_CMD_CRC_RESET_SHIFT 4 1500fe56b9e6SYuval Mintz #define DMAE_CMD_SRC_ADDR_RESET_MASK 0x1 1501fe56b9e6SYuval Mintz #define DMAE_CMD_SRC_ADDR_RESET_SHIFT 5 1502fe56b9e6SYuval Mintz #define DMAE_CMD_DST_ADDR_RESET_MASK 0x1 1503fe56b9e6SYuval Mintz #define DMAE_CMD_DST_ADDR_RESET_SHIFT 6 1504fe56b9e6SYuval Mintz #define DMAE_CMD_COMP_FUNC_MASK 0x1 1505fe56b9e6SYuval Mintz #define DMAE_CMD_COMP_FUNC_SHIFT 7 1506fe56b9e6SYuval Mintz #define DMAE_CMD_COMP_WORD_EN_MASK 0x1 1507fe56b9e6SYuval Mintz #define DMAE_CMD_COMP_WORD_EN_SHIFT 8 1508fe56b9e6SYuval Mintz #define DMAE_CMD_COMP_CRC_EN_MASK 0x1 1509fe56b9e6SYuval Mintz #define DMAE_CMD_COMP_CRC_EN_SHIFT 9 1510fe56b9e6SYuval Mintz #define DMAE_CMD_COMP_CRC_OFFSET_MASK 0x7 1511fe56b9e6SYuval Mintz #define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10 1512fe56b9e6SYuval Mintz #define DMAE_CMD_RESERVED1_MASK 0x1 1513fe56b9e6SYuval Mintz #define DMAE_CMD_RESERVED1_SHIFT 13 1514fe56b9e6SYuval Mintz #define DMAE_CMD_ENDIANITY_MODE_MASK 0x3 1515fe56b9e6SYuval Mintz #define DMAE_CMD_ENDIANITY_MODE_SHIFT 14 1516fe56b9e6SYuval Mintz #define DMAE_CMD_ERR_HANDLING_MASK 0x3 1517fe56b9e6SYuval Mintz #define DMAE_CMD_ERR_HANDLING_SHIFT 16 1518fe56b9e6SYuval Mintz #define DMAE_CMD_PORT_ID_MASK 0x3 1519fe56b9e6SYuval Mintz #define DMAE_CMD_PORT_ID_SHIFT 18 1520fe56b9e6SYuval Mintz #define DMAE_CMD_SRC_PF_ID_MASK 0xF 1521fe56b9e6SYuval Mintz #define DMAE_CMD_SRC_PF_ID_SHIFT 20 1522fe56b9e6SYuval Mintz #define DMAE_CMD_DST_PF_ID_MASK 0xF 1523fe56b9e6SYuval Mintz #define DMAE_CMD_DST_PF_ID_SHIFT 24 1524fe56b9e6SYuval Mintz #define DMAE_CMD_SRC_VF_ID_VALID_MASK 0x1 1525fe56b9e6SYuval Mintz #define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28 1526fe56b9e6SYuval Mintz #define DMAE_CMD_DST_VF_ID_VALID_MASK 0x1 1527fe56b9e6SYuval Mintz #define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29 1528fe56b9e6SYuval Mintz #define DMAE_CMD_RESERVED2_MASK 0x3 1529fe56b9e6SYuval Mintz #define DMAE_CMD_RESERVED2_SHIFT 30 1530fe56b9e6SYuval Mintz __le32 src_addr_lo; 1531fe56b9e6SYuval Mintz __le32 src_addr_hi; 1532fe56b9e6SYuval Mintz __le32 dst_addr_lo; 1533fe56b9e6SYuval Mintz __le32 dst_addr_hi; 1534351a4dedSYuval Mintz __le16 length_dw; 1535fe56b9e6SYuval Mintz __le16 opcode_b; 1536351a4dedSYuval Mintz #define DMAE_CMD_SRC_VF_ID_MASK 0xFF 1537fe56b9e6SYuval Mintz #define DMAE_CMD_SRC_VF_ID_SHIFT 0 1538351a4dedSYuval Mintz #define DMAE_CMD_DST_VF_ID_MASK 0xFF 1539fe56b9e6SYuval Mintz #define DMAE_CMD_DST_VF_ID_SHIFT 8 1540351a4dedSYuval Mintz __le32 comp_addr_lo; 1541fe56b9e6SYuval Mintz __le32 comp_addr_hi; 1542351a4dedSYuval Mintz __le32 comp_val; 1543351a4dedSYuval Mintz __le32 crc32; 1544351a4dedSYuval Mintz __le32 crc_32_c; 1545351a4dedSYuval Mintz __le16 crc16; 1546351a4dedSYuval Mintz __le16 crc16_c; 1547351a4dedSYuval Mintz __le16 crc10; 1548804c5702SMichal Kalderon __le16 error_bit_reserved; 1549804c5702SMichal Kalderon #define DMAE_CMD_ERROR_BIT_MASK 0x1 1550804c5702SMichal Kalderon #define DMAE_CMD_ERROR_BIT_SHIFT 0 1551804c5702SMichal Kalderon #define DMAE_CMD_RESERVED_MASK 0x7FFF 1552804c5702SMichal Kalderon #define DMAE_CMD_RESERVED_SHIFT 1 1553351a4dedSYuval Mintz __le16 xsum16; 1554351a4dedSYuval Mintz __le16 xsum8; 1555fe56b9e6SYuval Mintz }; 1556fe56b9e6SYuval Mintz 1557351a4dedSYuval Mintz enum dmae_cmd_comp_crc_en_enum { 1558351a4dedSYuval Mintz dmae_cmd_comp_crc_disabled, 1559351a4dedSYuval Mintz dmae_cmd_comp_crc_enabled, 1560351a4dedSYuval Mintz MAX_DMAE_CMD_COMP_CRC_EN_ENUM 1561351a4dedSYuval Mintz }; 1562351a4dedSYuval Mintz 1563351a4dedSYuval Mintz enum dmae_cmd_comp_func_enum { 1564351a4dedSYuval Mintz dmae_cmd_comp_func_to_src, 1565351a4dedSYuval Mintz dmae_cmd_comp_func_to_dst, 1566351a4dedSYuval Mintz MAX_DMAE_CMD_COMP_FUNC_ENUM 1567351a4dedSYuval Mintz }; 1568351a4dedSYuval Mintz 1569351a4dedSYuval Mintz enum dmae_cmd_comp_word_en_enum { 1570351a4dedSYuval Mintz dmae_cmd_comp_word_disabled, 1571351a4dedSYuval Mintz dmae_cmd_comp_word_enabled, 1572351a4dedSYuval Mintz MAX_DMAE_CMD_COMP_WORD_EN_ENUM 1573351a4dedSYuval Mintz }; 1574351a4dedSYuval Mintz 1575351a4dedSYuval Mintz enum dmae_cmd_c_dst_enum { 1576351a4dedSYuval Mintz dmae_cmd_c_dst_pcie, 1577351a4dedSYuval Mintz dmae_cmd_c_dst_grc, 1578351a4dedSYuval Mintz MAX_DMAE_CMD_C_DST_ENUM 1579351a4dedSYuval Mintz }; 1580351a4dedSYuval Mintz 1581351a4dedSYuval Mintz enum dmae_cmd_dst_enum { 1582351a4dedSYuval Mintz dmae_cmd_dst_none_0, 1583351a4dedSYuval Mintz dmae_cmd_dst_pcie, 1584351a4dedSYuval Mintz dmae_cmd_dst_grc, 1585351a4dedSYuval Mintz dmae_cmd_dst_none_3, 1586351a4dedSYuval Mintz MAX_DMAE_CMD_DST_ENUM 1587351a4dedSYuval Mintz }; 1588351a4dedSYuval Mintz 1589351a4dedSYuval Mintz enum dmae_cmd_error_handling_enum { 1590351a4dedSYuval Mintz dmae_cmd_error_handling_send_regular_comp, 1591351a4dedSYuval Mintz dmae_cmd_error_handling_send_comp_with_err, 1592351a4dedSYuval Mintz dmae_cmd_error_handling_dont_send_comp, 1593351a4dedSYuval Mintz MAX_DMAE_CMD_ERROR_HANDLING_ENUM 1594351a4dedSYuval Mintz }; 1595351a4dedSYuval Mintz 1596351a4dedSYuval Mintz enum dmae_cmd_src_enum { 1597351a4dedSYuval Mintz dmae_cmd_src_pcie, 1598351a4dedSYuval Mintz dmae_cmd_src_grc, 1599351a4dedSYuval Mintz MAX_DMAE_CMD_SRC_ENUM 1600351a4dedSYuval Mintz }; 1601351a4dedSYuval Mintz 1602fb09a1edSShai Malin struct mstorm_core_conn_ag_ctx { 16037b6859fbSMintz, Yuval u8 byte0; 16047b6859fbSMintz, Yuval u8 byte1; 16057b6859fbSMintz, Yuval u8 flags0; 1606fb09a1edSShai Malin #define MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 1607fb09a1edSShai Malin #define MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 1608fb09a1edSShai Malin #define MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 1609fb09a1edSShai Malin #define MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 1610fb09a1edSShai Malin #define MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 1611fb09a1edSShai Malin #define MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 1612fb09a1edSShai Malin #define MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 1613fb09a1edSShai Malin #define MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 1614fb09a1edSShai Malin #define MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 1615fb09a1edSShai Malin #define MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 16167b6859fbSMintz, Yuval u8 flags1; 1617fb09a1edSShai Malin #define MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 1618fb09a1edSShai Malin #define MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 1619fb09a1edSShai Malin #define MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 1620fb09a1edSShai Malin #define MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 1621fb09a1edSShai Malin #define MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 1622fb09a1edSShai Malin #define MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 1623fb09a1edSShai Malin #define MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 1624fb09a1edSShai Malin #define MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3 1625fb09a1edSShai Malin #define MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 1626fb09a1edSShai Malin #define MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4 1627fb09a1edSShai Malin #define MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 1628fb09a1edSShai Malin #define MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5 1629fb09a1edSShai Malin #define MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 1630fb09a1edSShai Malin #define MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6 1631fb09a1edSShai Malin #define MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 1632fb09a1edSShai Malin #define MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7 16337b6859fbSMintz, Yuval __le16 word0; 16347b6859fbSMintz, Yuval __le16 word1; 16357b6859fbSMintz, Yuval __le32 reg0; 16367b6859fbSMintz, Yuval __le32 reg1; 16377b6859fbSMintz, Yuval }; 16387b6859fbSMintz, Yuval 1639fb09a1edSShai Malin struct ystorm_core_conn_ag_ctx { 16407b6859fbSMintz, Yuval u8 byte0; 16417b6859fbSMintz, Yuval u8 byte1; 16427b6859fbSMintz, Yuval u8 flags0; 1643fb09a1edSShai Malin #define YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 1644fb09a1edSShai Malin #define YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 1645fb09a1edSShai Malin #define YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 1646fb09a1edSShai Malin #define YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 1647fb09a1edSShai Malin #define YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 1648fb09a1edSShai Malin #define YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 1649fb09a1edSShai Malin #define YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 1650fb09a1edSShai Malin #define YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 1651fb09a1edSShai Malin #define YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 1652fb09a1edSShai Malin #define YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 16537b6859fbSMintz, Yuval u8 flags1; 1654fb09a1edSShai Malin #define YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 1655fb09a1edSShai Malin #define YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 1656fb09a1edSShai Malin #define YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 1657fb09a1edSShai Malin #define YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 1658fb09a1edSShai Malin #define YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 1659fb09a1edSShai Malin #define YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 1660fb09a1edSShai Malin #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 1661fb09a1edSShai Malin #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3 1662fb09a1edSShai Malin #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 1663fb09a1edSShai Malin #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4 1664fb09a1edSShai Malin #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 1665fb09a1edSShai Malin #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5 1666fb09a1edSShai Malin #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 1667fb09a1edSShai Malin #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6 1668fb09a1edSShai Malin #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 1669fb09a1edSShai Malin #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7 16707b6859fbSMintz, Yuval u8 byte2; 16717b6859fbSMintz, Yuval u8 byte3; 16727b6859fbSMintz, Yuval __le16 word0; 16737b6859fbSMintz, Yuval __le32 reg0; 16747b6859fbSMintz, Yuval __le32 reg1; 16757b6859fbSMintz, Yuval __le16 word1; 16767b6859fbSMintz, Yuval __le16 word2; 16777b6859fbSMintz, Yuval __le16 word3; 16787b6859fbSMintz, Yuval __le16 word4; 16797b6859fbSMintz, Yuval __le32 reg2; 16807b6859fbSMintz, Yuval __le32 reg3; 16817b6859fbSMintz, Yuval }; 16827b6859fbSMintz, Yuval 1683804c5702SMichal Kalderon /* DMAE parameters */ 1684804c5702SMichal Kalderon struct qed_dmae_params { 1685804c5702SMichal Kalderon u32 flags; 1686804c5702SMichal Kalderon /* If QED_DMAE_PARAMS_RW_REPL_SRC flag is set and the 1687804c5702SMichal Kalderon * source is a block of length DMAE_MAX_RW_SIZE and the 1688804c5702SMichal Kalderon * destination is larger, the source block will be duplicated as 1689804c5702SMichal Kalderon * many times as required to fill the destination block. This is 1690804c5702SMichal Kalderon * used mostly to write a zeroed buffer to destination address 1691804c5702SMichal Kalderon * using DMA 1692804c5702SMichal Kalderon */ 1693804c5702SMichal Kalderon #define QED_DMAE_PARAMS_RW_REPL_SRC_MASK 0x1 1694804c5702SMichal Kalderon #define QED_DMAE_PARAMS_RW_REPL_SRC_SHIFT 0 1695804c5702SMichal Kalderon #define QED_DMAE_PARAMS_SRC_VF_VALID_MASK 0x1 1696804c5702SMichal Kalderon #define QED_DMAE_PARAMS_SRC_VF_VALID_SHIFT 1 1697804c5702SMichal Kalderon #define QED_DMAE_PARAMS_DST_VF_VALID_MASK 0x1 1698804c5702SMichal Kalderon #define QED_DMAE_PARAMS_DST_VF_VALID_SHIFT 2 1699804c5702SMichal Kalderon #define QED_DMAE_PARAMS_COMPLETION_DST_MASK 0x1 1700804c5702SMichal Kalderon #define QED_DMAE_PARAMS_COMPLETION_DST_SHIFT 3 1701804c5702SMichal Kalderon #define QED_DMAE_PARAMS_PORT_VALID_MASK 0x1 1702804c5702SMichal Kalderon #define QED_DMAE_PARAMS_PORT_VALID_SHIFT 4 1703804c5702SMichal Kalderon #define QED_DMAE_PARAMS_SRC_PF_VALID_MASK 0x1 1704804c5702SMichal Kalderon #define QED_DMAE_PARAMS_SRC_PF_VALID_SHIFT 5 1705804c5702SMichal Kalderon #define QED_DMAE_PARAMS_DST_PF_VALID_MASK 0x1 1706804c5702SMichal Kalderon #define QED_DMAE_PARAMS_DST_PF_VALID_SHIFT 6 1707804c5702SMichal Kalderon #define QED_DMAE_PARAMS_RESERVED_MASK 0x1FFFFFF 1708804c5702SMichal Kalderon #define QED_DMAE_PARAMS_RESERVED_SHIFT 7 1709804c5702SMichal Kalderon u8 src_vfid; 1710804c5702SMichal Kalderon u8 dst_vfid; 1711804c5702SMichal Kalderon u8 port_id; 1712804c5702SMichal Kalderon u8 src_pfid; 1713804c5702SMichal Kalderon u8 dst_pfid; 1714804c5702SMichal Kalderon u8 reserved1; 1715804c5702SMichal Kalderon __le16 reserved2; 1716804c5702SMichal Kalderon }; 1717804c5702SMichal Kalderon 1718351a4dedSYuval Mintz /* IGU cleanup command */ 1719fe56b9e6SYuval Mintz struct igu_cleanup { 1720fe56b9e6SYuval Mintz __le32 sb_id_and_flags; 1721fe56b9e6SYuval Mintz #define IGU_CLEANUP_RESERVED0_MASK 0x7FFFFFF 1722fe56b9e6SYuval Mintz #define IGU_CLEANUP_RESERVED0_SHIFT 0 1723351a4dedSYuval Mintz #define IGU_CLEANUP_CLEANUP_SET_MASK 0x1 1724fe56b9e6SYuval Mintz #define IGU_CLEANUP_CLEANUP_SET_SHIFT 27 1725fe56b9e6SYuval Mintz #define IGU_CLEANUP_CLEANUP_TYPE_MASK 0x7 1726fe56b9e6SYuval Mintz #define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28 1727fe56b9e6SYuval Mintz #define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1 1728fe56b9e6SYuval Mintz #define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31 1729fe56b9e6SYuval Mintz __le32 reserved1; 1730fe56b9e6SYuval Mintz }; 1731fe56b9e6SYuval Mintz 1732351a4dedSYuval Mintz /* IGU firmware driver command */ 1733fe56b9e6SYuval Mintz union igu_command { 1734fe56b9e6SYuval Mintz struct igu_prod_cons_update prod_cons_update; 1735fe56b9e6SYuval Mintz struct igu_cleanup cleanup; 1736fe56b9e6SYuval Mintz }; 1737fe56b9e6SYuval Mintz 1738351a4dedSYuval Mintz /* IGU firmware driver command */ 1739fe56b9e6SYuval Mintz struct igu_command_reg_ctrl { 1740fe56b9e6SYuval Mintz __le16 opaque_fid; 1741fe56b9e6SYuval Mintz __le16 igu_command_reg_ctrl_fields; 1742fe56b9e6SYuval Mintz #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK 0xFFF 1743fe56b9e6SYuval Mintz #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0 1744fe56b9e6SYuval Mintz #define IGU_COMMAND_REG_CTRL_RESERVED_MASK 0x7 1745fe56b9e6SYuval Mintz #define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT 12 1746fe56b9e6SYuval Mintz #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK 0x1 1747fe56b9e6SYuval Mintz #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15 1748fe56b9e6SYuval Mintz }; 1749fe56b9e6SYuval Mintz 1750351a4dedSYuval Mintz /* IGU mapping line structure */ 1751fe56b9e6SYuval Mintz struct igu_mapping_line { 1752fe56b9e6SYuval Mintz __le32 igu_mapping_line_fields; 1753fe56b9e6SYuval Mintz #define IGU_MAPPING_LINE_VALID_MASK 0x1 1754fe56b9e6SYuval Mintz #define IGU_MAPPING_LINE_VALID_SHIFT 0 1755fe56b9e6SYuval Mintz #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK 0xFF 1756fe56b9e6SYuval Mintz #define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT 1 1757fe56b9e6SYuval Mintz #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK 0xFF 1758fe56b9e6SYuval Mintz #define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT 9 1759351a4dedSYuval Mintz #define IGU_MAPPING_LINE_PF_VALID_MASK 0x1 1760fe56b9e6SYuval Mintz #define IGU_MAPPING_LINE_PF_VALID_SHIFT 17 1761fe56b9e6SYuval Mintz #define IGU_MAPPING_LINE_IPS_GROUP_MASK 0x3F 1762fe56b9e6SYuval Mintz #define IGU_MAPPING_LINE_IPS_GROUP_SHIFT 18 1763fe56b9e6SYuval Mintz #define IGU_MAPPING_LINE_RESERVED_MASK 0xFF 1764fe56b9e6SYuval Mintz #define IGU_MAPPING_LINE_RESERVED_SHIFT 24 1765fe56b9e6SYuval Mintz }; 1766fe56b9e6SYuval Mintz 1767351a4dedSYuval Mintz /* IGU MSIX line structure */ 1768fe56b9e6SYuval Mintz struct igu_msix_vector { 1769fe56b9e6SYuval Mintz struct regpair address; 1770fe56b9e6SYuval Mintz __le32 data; 1771fe56b9e6SYuval Mintz __le32 msix_vector_fields; 1772fe56b9e6SYuval Mintz #define IGU_MSIX_VECTOR_MASK_BIT_MASK 0x1 1773fe56b9e6SYuval Mintz #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT 0 1774fe56b9e6SYuval Mintz #define IGU_MSIX_VECTOR_RESERVED0_MASK 0x7FFF 1775fe56b9e6SYuval Mintz #define IGU_MSIX_VECTOR_RESERVED0_SHIFT 1 1776fe56b9e6SYuval Mintz #define IGU_MSIX_VECTOR_STEERING_TAG_MASK 0xFF 1777fe56b9e6SYuval Mintz #define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT 16 1778fe56b9e6SYuval Mintz #define IGU_MSIX_VECTOR_RESERVED1_MASK 0xFF 1779fe56b9e6SYuval Mintz #define IGU_MSIX_VECTOR_RESERVED1_SHIFT 24 1780fe56b9e6SYuval Mintz }; 1781fe40a830SPrabhakar Kushwaha 1782fe56b9e6SYuval Mintz /* per encapsulation type enabling flags */ 1783fe56b9e6SYuval Mintz struct prs_reg_encapsulation_type_en { 1784fe56b9e6SYuval Mintz u8 flags; 1785fe56b9e6SYuval Mintz #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK 0x1 1786fe56b9e6SYuval Mintz #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT 0 1787fe56b9e6SYuval Mintz #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK 0x1 1788fe56b9e6SYuval Mintz #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT 1 1789fe56b9e6SYuval Mintz #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK 0x1 1790fe56b9e6SYuval Mintz #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT 2 1791fe56b9e6SYuval Mintz #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK 0x1 1792fe56b9e6SYuval Mintz #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT 3 1793fe56b9e6SYuval Mintz #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK 0x1 1794fe56b9e6SYuval Mintz #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT 4 1795fe56b9e6SYuval Mintz #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK 0x1 1796fe56b9e6SYuval Mintz #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT 5 1797fe56b9e6SYuval Mintz #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3 1798fe56b9e6SYuval Mintz #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT 6 1799fe56b9e6SYuval Mintz }; 1800fe56b9e6SYuval Mintz 1801fe56b9e6SYuval Mintz enum pxp_tph_st_hint { 1802351a4dedSYuval Mintz TPH_ST_HINT_BIDIR, 1803351a4dedSYuval Mintz TPH_ST_HINT_REQUESTER, 1804fe56b9e6SYuval Mintz TPH_ST_HINT_TARGET, 1805fe56b9e6SYuval Mintz TPH_ST_HINT_TARGET_PRIO, 1806fe56b9e6SYuval Mintz MAX_PXP_TPH_ST_HINT 1807fe56b9e6SYuval Mintz }; 1808fe56b9e6SYuval Mintz 1809fe56b9e6SYuval Mintz /* QM hardware structure of enable bypass credit mask */ 1810fe56b9e6SYuval Mintz struct qm_rf_bypass_mask { 1811fe56b9e6SYuval Mintz u8 flags; 1812fe56b9e6SYuval Mintz #define QM_RF_BYPASS_MASK_LINEVOQ_MASK 0x1 1813fe56b9e6SYuval Mintz #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT 0 1814fe56b9e6SYuval Mintz #define QM_RF_BYPASS_MASK_RESERVED0_MASK 0x1 1815fe56b9e6SYuval Mintz #define QM_RF_BYPASS_MASK_RESERVED0_SHIFT 1 1816fe56b9e6SYuval Mintz #define QM_RF_BYPASS_MASK_PFWFQ_MASK 0x1 1817fe56b9e6SYuval Mintz #define QM_RF_BYPASS_MASK_PFWFQ_SHIFT 2 1818fe56b9e6SYuval Mintz #define QM_RF_BYPASS_MASK_VPWFQ_MASK 0x1 1819fe56b9e6SYuval Mintz #define QM_RF_BYPASS_MASK_VPWFQ_SHIFT 3 1820fe56b9e6SYuval Mintz #define QM_RF_BYPASS_MASK_PFRL_MASK 0x1 1821fe56b9e6SYuval Mintz #define QM_RF_BYPASS_MASK_PFRL_SHIFT 4 1822fe56b9e6SYuval Mintz #define QM_RF_BYPASS_MASK_VPQCNRL_MASK 0x1 1823fe56b9e6SYuval Mintz #define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT 5 1824fe56b9e6SYuval Mintz #define QM_RF_BYPASS_MASK_FWPAUSE_MASK 0x1 1825fe56b9e6SYuval Mintz #define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT 6 1826fe56b9e6SYuval Mintz #define QM_RF_BYPASS_MASK_RESERVED1_MASK 0x1 1827fe56b9e6SYuval Mintz #define QM_RF_BYPASS_MASK_RESERVED1_SHIFT 7 1828fe56b9e6SYuval Mintz }; 1829fe56b9e6SYuval Mintz 1830fe56b9e6SYuval Mintz /* QM hardware structure of opportunistic credit mask */ 1831fe56b9e6SYuval Mintz struct qm_rf_opportunistic_mask { 1832fe56b9e6SYuval Mintz __le16 flags; 1833fe56b9e6SYuval Mintz #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK 0x1 1834fe56b9e6SYuval Mintz #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT 0 1835fe56b9e6SYuval Mintz #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK 0x1 1836fe56b9e6SYuval Mintz #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT 1 1837fe56b9e6SYuval Mintz #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK 0x1 1838fe56b9e6SYuval Mintz #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT 2 1839fe56b9e6SYuval Mintz #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK 0x1 1840fe56b9e6SYuval Mintz #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT 3 1841fe56b9e6SYuval Mintz #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK 0x1 1842fe56b9e6SYuval Mintz #define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT 4 1843fe56b9e6SYuval Mintz #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK 0x1 1844fe56b9e6SYuval Mintz #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT 5 1845fe56b9e6SYuval Mintz #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK 0x1 1846fe56b9e6SYuval Mintz #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT 6 1847fe56b9e6SYuval Mintz #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK 0x1 1848fe56b9e6SYuval Mintz #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT 7 1849fe56b9e6SYuval Mintz #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK 0x1 1850fe56b9e6SYuval Mintz #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT 8 1851fe56b9e6SYuval Mintz #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK 0x7F 1852fe56b9e6SYuval Mintz #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT 9 1853fe56b9e6SYuval Mintz }; 1854fe56b9e6SYuval Mintz 1855fe56b9e6SYuval Mintz /* QM hardware structure of QM map memory */ 1856fb09a1edSShai Malin struct qm_rf_pq_map { 1857351a4dedSYuval Mintz __le32 reg; 1858fb09a1edSShai Malin #define QM_RF_PQ_MAP_PQ_VALID_MASK 0x1 1859fb09a1edSShai Malin #define QM_RF_PQ_MAP_PQ_VALID_SHIFT 0 1860fb09a1edSShai Malin #define QM_RF_PQ_MAP_RL_ID_MASK 0xFF 1861fb09a1edSShai Malin #define QM_RF_PQ_MAP_RL_ID_SHIFT 1 1862fb09a1edSShai Malin #define QM_RF_PQ_MAP_VP_PQ_ID_MASK 0x1FF 1863fb09a1edSShai Malin #define QM_RF_PQ_MAP_VP_PQ_ID_SHIFT 9 1864fb09a1edSShai Malin #define QM_RF_PQ_MAP_VOQ_MASK 0x1F 1865fb09a1edSShai Malin #define QM_RF_PQ_MAP_VOQ_SHIFT 18 1866fb09a1edSShai Malin #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK 0x3 1867fb09a1edSShai Malin #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_SHIFT 23 1868fb09a1edSShai Malin #define QM_RF_PQ_MAP_RL_VALID_MASK 0x1 1869fb09a1edSShai Malin #define QM_RF_PQ_MAP_RL_VALID_SHIFT 25 1870fb09a1edSShai Malin #define QM_RF_PQ_MAP_RESERVED_MASK 0x3F 1871fb09a1edSShai Malin #define QM_RF_PQ_MAP_RESERVED_SHIFT 26 1872fe56b9e6SYuval Mintz }; 1873fe56b9e6SYuval Mintz 1874fc48b7a6SYuval Mintz /* Completion params for aggregated interrupt completion */ 1875fc48b7a6SYuval Mintz struct sdm_agg_int_comp_params { 1876fc48b7a6SYuval Mintz __le16 params; 1877fc48b7a6SYuval Mintz #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK 0x3F 1878fc48b7a6SYuval Mintz #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT 0 1879fc48b7a6SYuval Mintz #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK 0x1 1880fc48b7a6SYuval Mintz #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6 1881fc48b7a6SYuval Mintz #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK 0x1FF 1882fc48b7a6SYuval Mintz #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT 7 1883fc48b7a6SYuval Mintz }; 1884fc48b7a6SYuval Mintz 1885fe56b9e6SYuval Mintz /* SDM operation gen command (generate aggregative interrupt) */ 1886fe56b9e6SYuval Mintz struct sdm_op_gen { 1887fe56b9e6SYuval Mintz __le32 command; 1888351a4dedSYuval Mintz #define SDM_OP_GEN_COMP_PARAM_MASK 0xFFFF 1889fe56b9e6SYuval Mintz #define SDM_OP_GEN_COMP_PARAM_SHIFT 0 1890351a4dedSYuval Mintz #define SDM_OP_GEN_COMP_TYPE_MASK 0xF 1891fe56b9e6SYuval Mintz #define SDM_OP_GEN_COMP_TYPE_SHIFT 16 1892351a4dedSYuval Mintz #define SDM_OP_GEN_RESERVED_MASK 0xFFF 1893fe56b9e6SYuval Mintz #define SDM_OP_GEN_RESERVED_SHIFT 20 1894fe56b9e6SYuval Mintz }; 1895fe56b9e6SYuval Mintz 189630d5f858SMichal Kalderon /* Physical memory descriptor */ 189730d5f858SMichal Kalderon struct phys_mem_desc { 189830d5f858SMichal Kalderon dma_addr_t phys_addr; 189930d5f858SMichal Kalderon void *virt_addr; 190030d5f858SMichal Kalderon u32 size; /* In bytes */ 190130d5f858SMichal Kalderon }; 190230d5f858SMichal Kalderon 190330d5f858SMichal Kalderon /* Virtual memory descriptor */ 190430d5f858SMichal Kalderon struct virt_mem_desc { 190530d5f858SMichal Kalderon void *ptr; 190630d5f858SMichal Kalderon u32 size; /* In bytes */ 190730d5f858SMichal Kalderon }; 190830d5f858SMichal Kalderon 1909351a4dedSYuval Mintz /********************************/ 1910351a4dedSYuval Mintz /* HSI Init Functions constants */ 1911351a4dedSYuval Mintz /********************************/ 1912351a4dedSYuval Mintz 1913351a4dedSYuval Mintz /* Number of VLAN priorities */ 1914351a4dedSYuval Mintz #define NUM_OF_VLAN_PRIORITIES 8 1915351a4dedSYuval Mintz 1916a2e7699eSTomer Tayar /* BRB RAM init requirements */ 191705fafbfbSYuval Mintz struct init_brb_ram_req { 191850bc60cbSMichal Kalderon u32 guranteed_per_tc; 191950bc60cbSMichal Kalderon u32 headroom_per_tc; 192050bc60cbSMichal Kalderon u32 min_pkt_size; 192150bc60cbSMichal Kalderon u32 max_ports_per_engine; 192205fafbfbSYuval Mintz u8 num_active_tcs[MAX_NUM_PORTS]; 192305fafbfbSYuval Mintz }; 192405fafbfbSYuval Mintz 1925a2e7699eSTomer Tayar /* ETS per-TC init requirements */ 192605fafbfbSYuval Mintz struct init_ets_tc_req { 192705fafbfbSYuval Mintz u8 use_sp; 192805fafbfbSYuval Mintz u8 use_wfq; 192950bc60cbSMichal Kalderon u16 weight; 193005fafbfbSYuval Mintz }; 193105fafbfbSYuval Mintz 1932a2e7699eSTomer Tayar /* ETS init requirements */ 193305fafbfbSYuval Mintz struct init_ets_req { 193450bc60cbSMichal Kalderon u32 mtu; 193505fafbfbSYuval Mintz struct init_ets_tc_req tc_req[NUM_OF_TCS]; 193605fafbfbSYuval Mintz }; 193705fafbfbSYuval Mintz 1938a2e7699eSTomer Tayar /* NIG LB RL init requirements */ 193905fafbfbSYuval Mintz struct init_nig_lb_rl_req { 194050bc60cbSMichal Kalderon u16 lb_mac_rate; 194150bc60cbSMichal Kalderon u16 lb_rate; 194250bc60cbSMichal Kalderon u32 mtu; 194350bc60cbSMichal Kalderon u16 tc_rate[NUM_OF_PHYS_TCS]; 194405fafbfbSYuval Mintz }; 194505fafbfbSYuval Mintz 1946a2e7699eSTomer Tayar /* NIG TC mapping for each priority */ 194705fafbfbSYuval Mintz struct init_nig_pri_tc_map_entry { 194805fafbfbSYuval Mintz u8 tc_id; 194905fafbfbSYuval Mintz u8 valid; 195005fafbfbSYuval Mintz }; 195105fafbfbSYuval Mintz 1952a2e7699eSTomer Tayar /* NIG priority to TC map init requirements */ 195305fafbfbSYuval Mintz struct init_nig_pri_tc_map_req { 195405fafbfbSYuval Mintz struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES]; 195505fafbfbSYuval Mintz }; 195605fafbfbSYuval Mintz 195792fae6fbSMichal Kalderon /* QM per global RL init parameters */ 195892fae6fbSMichal Kalderon struct init_qm_global_rl_params { 1959fe40a830SPrabhakar Kushwaha u8 type; 1960fe40a830SPrabhakar Kushwaha u8 reserved0; 1961fe40a830SPrabhakar Kushwaha u16 reserved1; 196292fae6fbSMichal Kalderon u32 rate_limit; 196392fae6fbSMichal Kalderon }; 196492fae6fbSMichal Kalderon 1965a2e7699eSTomer Tayar /* QM per-port init parameters */ 1966351a4dedSYuval Mintz struct init_qm_port_params { 196792fae6fbSMichal Kalderon u16 active_phys_tcs; 196850bc60cbSMichal Kalderon u16 num_pbf_cmd_lines; 196950bc60cbSMichal Kalderon u16 num_btb_blocks; 197092fae6fbSMichal Kalderon u8 active; 197192fae6fbSMichal Kalderon u8 reserved; 1972351a4dedSYuval Mintz }; 1973351a4dedSYuval Mintz 1974351a4dedSYuval Mintz /* QM per-PQ init parameters */ 1975351a4dedSYuval Mintz struct init_qm_pq_params { 1976fe40a830SPrabhakar Kushwaha u16 vport_id; 1977fe40a830SPrabhakar Kushwaha u16 rl_id; 1978fe40a830SPrabhakar Kushwaha u8 rl_valid; 1979351a4dedSYuval Mintz u8 tc_id; 1980351a4dedSYuval Mintz u8 wrr_group; 198150bc60cbSMichal Kalderon u8 port_id; 1982fe40a830SPrabhakar Kushwaha }; 1983fe40a830SPrabhakar Kushwaha 1984fe40a830SPrabhakar Kushwaha /* QM per RL init parameters */ 1985fe40a830SPrabhakar Kushwaha struct init_qm_rl_params { 1986fe40a830SPrabhakar Kushwaha u32 vport_rl; 1987fe40a830SPrabhakar Kushwaha u8 vport_rl_type; 1988fe40a830SPrabhakar Kushwaha u8 reserved[3]; 1989fe40a830SPrabhakar Kushwaha }; 1990fe40a830SPrabhakar Kushwaha 1991fe40a830SPrabhakar Kushwaha /* QM Rate Limiter types */ 1992fe40a830SPrabhakar Kushwaha enum init_qm_rl_type { 1993fe40a830SPrabhakar Kushwaha QM_RL_TYPE_NORMAL, 1994fe40a830SPrabhakar Kushwaha QM_RL_TYPE_QCN, 1995fe40a830SPrabhakar Kushwaha MAX_INIT_QM_RL_TYPE 1996351a4dedSYuval Mintz }; 1997351a4dedSYuval Mintz 1998351a4dedSYuval Mintz /* QM per-vport init parameters */ 1999351a4dedSYuval Mintz struct init_qm_vport_params { 200092fae6fbSMichal Kalderon u16 wfq; 2001fe40a830SPrabhakar Kushwaha u16 reserved; 2002fe40a830SPrabhakar Kushwaha u16 tc_wfq[NUM_OF_TCS]; 200350bc60cbSMichal Kalderon u16 first_tx_pq_id[NUM_OF_TCS]; 2004351a4dedSYuval Mintz }; 2005351a4dedSYuval Mintz 2006351a4dedSYuval Mintz /**************************************/ 2007351a4dedSYuval Mintz /* Init Tool HSI constants and macros */ 2008351a4dedSYuval Mintz /**************************************/ 2009fe56b9e6SYuval Mintz 2010fe56b9e6SYuval Mintz /* Width of GRC address in bits (addresses are specified in dwords) */ 2011fe56b9e6SYuval Mintz #define GRC_ADDR_BITS 23 201205fafbfbSYuval Mintz #define MAX_GRC_ADDR (BIT(GRC_ADDR_BITS) - 1) 2013fe56b9e6SYuval Mintz 2014fe56b9e6SYuval Mintz /* indicates an init that should be applied to any phase ID */ 2015fe56b9e6SYuval Mintz #define ANY_PHASE_ID 0xffff 2016fe56b9e6SYuval Mintz 2017fe56b9e6SYuval Mintz /* Max size in dwords of a zipped array */ 2018fe56b9e6SYuval Mintz #define MAX_ZIPPED_SIZE 8192 20197b6859fbSMintz, Yuval enum chip_ids { 20207b6859fbSMintz, Yuval CHIP_BB, 20217b6859fbSMintz, Yuval CHIP_K2, 20227b6859fbSMintz, Yuval MAX_CHIP_IDS 20237b6859fbSMintz, Yuval }; 2024fe56b9e6SYuval Mintz 2025c965db44STomer Tayar struct fw_asserts_ram_section { 20260500a70dSMichal Kalderon __le16 section_ram_line_offset; 20270500a70dSMichal Kalderon __le16 section_ram_line_size; 2028c965db44STomer Tayar u8 list_dword_offset; 2029c965db44STomer Tayar u8 list_element_dword_size; 2030c965db44STomer Tayar u8 list_num_elements; 2031c965db44STomer Tayar u8 list_next_index_dword_offset; 2032c965db44STomer Tayar }; 2033c965db44STomer Tayar 2034c965db44STomer Tayar struct fw_ver_num { 20357b6859fbSMintz, Yuval u8 major; 20367b6859fbSMintz, Yuval u8 minor; 20377b6859fbSMintz, Yuval u8 rev; 20387b6859fbSMintz, Yuval u8 eng; 2039c965db44STomer Tayar }; 2040c965db44STomer Tayar 2041c965db44STomer Tayar struct fw_ver_info { 20427b6859fbSMintz, Yuval __le16 tools_ver; 20437b6859fbSMintz, Yuval u8 image_id; 2044c965db44STomer Tayar u8 reserved1; 20457b6859fbSMintz, Yuval struct fw_ver_num num; 20467b6859fbSMintz, Yuval __le32 timestamp; 2047c965db44STomer Tayar __le32 reserved2; 2048c965db44STomer Tayar }; 2049c965db44STomer Tayar 2050c965db44STomer Tayar struct fw_info { 2051c965db44STomer Tayar struct fw_ver_info ver; 2052c965db44STomer Tayar struct fw_asserts_ram_section fw_asserts_section; 2053c965db44STomer Tayar }; 2054c965db44STomer Tayar 2055c965db44STomer Tayar struct fw_info_location { 2056c965db44STomer Tayar __le32 grc_addr; 2057c965db44STomer Tayar __le32 size; 2058c965db44STomer Tayar }; 2059c965db44STomer Tayar 2060351a4dedSYuval Mintz enum init_modes { 2061fe40a830SPrabhakar Kushwaha MODE_BB_A0_DEPRECATED, 20629c79ddaaSMintz, Yuval MODE_BB, 2063c965db44STomer Tayar MODE_K2, 2064351a4dedSYuval Mintz MODE_ASIC, 2065fe40a830SPrabhakar Kushwaha MODE_EMUL_REDUCED, 2066fe40a830SPrabhakar Kushwaha MODE_EMUL_FULL, 2067fe40a830SPrabhakar Kushwaha MODE_FPGA, 2068fe40a830SPrabhakar Kushwaha MODE_CHIPSIM, 2069351a4dedSYuval Mintz MODE_SF, 2070351a4dedSYuval Mintz MODE_MF_SD, 2071351a4dedSYuval Mintz MODE_MF_SI, 2072351a4dedSYuval Mintz MODE_PORTS_PER_ENG_1, 2073351a4dedSYuval Mintz MODE_PORTS_PER_ENG_2, 2074351a4dedSYuval Mintz MODE_PORTS_PER_ENG_4, 2075351a4dedSYuval Mintz MODE_100G, 2076fe40a830SPrabhakar Kushwaha MODE_SKIP_PRAM_INIT, 2077fe40a830SPrabhakar Kushwaha MODE_EMUL_MAC, 2078351a4dedSYuval Mintz MAX_INIT_MODES 2079351a4dedSYuval Mintz }; 2080fe56b9e6SYuval Mintz 2081351a4dedSYuval Mintz enum init_phases { 2082351a4dedSYuval Mintz PHASE_ENGINE, 2083351a4dedSYuval Mintz PHASE_PORT, 2084351a4dedSYuval Mintz PHASE_PF, 2085351a4dedSYuval Mintz PHASE_VF, 2086351a4dedSYuval Mintz PHASE_QM_PF, 2087351a4dedSYuval Mintz MAX_INIT_PHASES 2088351a4dedSYuval Mintz }; 2089fe56b9e6SYuval Mintz 2090351a4dedSYuval Mintz enum init_split_types { 2091351a4dedSYuval Mintz SPLIT_TYPE_NONE, 2092351a4dedSYuval Mintz SPLIT_TYPE_PORT, 2093351a4dedSYuval Mintz SPLIT_TYPE_PF, 2094351a4dedSYuval Mintz SPLIT_TYPE_PORT_PF, 2095351a4dedSYuval Mintz SPLIT_TYPE_VF, 2096351a4dedSYuval Mintz MAX_INIT_SPLIT_TYPES 2097351a4dedSYuval Mintz }; 2098fe56b9e6SYuval Mintz 2099fe56b9e6SYuval Mintz /* Binary buffer header */ 2100fe56b9e6SYuval Mintz struct bin_buffer_hdr { 210150bc60cbSMichal Kalderon u32 offset; 210250bc60cbSMichal Kalderon u32 length; 2103fe56b9e6SYuval Mintz }; 2104fe56b9e6SYuval Mintz 2105a2e7699eSTomer Tayar /* Binary init buffer types */ 2106351a4dedSYuval Mintz enum bin_init_buffer_type { 210705fafbfbSYuval Mintz BIN_BUF_INIT_FW_VER_INFO, 2108351a4dedSYuval Mintz BIN_BUF_INIT_CMD, 2109351a4dedSYuval Mintz BIN_BUF_INIT_VAL, 2110351a4dedSYuval Mintz BIN_BUF_INIT_MODE_TREE, 211105fafbfbSYuval Mintz BIN_BUF_INIT_IRO, 21120500a70dSMichal Kalderon BIN_BUF_INIT_OVERLAYS, 2113351a4dedSYuval Mintz MAX_BIN_INIT_BUFFER_TYPE 2114fe56b9e6SYuval Mintz }; 2115fe56b9e6SYuval Mintz 211630d5f858SMichal Kalderon /* FW overlay buffer header */ 211730d5f858SMichal Kalderon struct fw_overlay_buf_hdr { 211830d5f858SMichal Kalderon u32 data; 211930d5f858SMichal Kalderon #define FW_OVERLAY_BUF_HDR_STORM_ID_MASK 0xFF 212030d5f858SMichal Kalderon #define FW_OVERLAY_BUF_HDR_STORM_ID_SHIFT 0 212130d5f858SMichal Kalderon #define FW_OVERLAY_BUF_HDR_BUF_SIZE_MASK 0xFFFFFF 212230d5f858SMichal Kalderon #define FW_OVERLAY_BUF_HDR_BUF_SIZE_SHIFT 8 212330d5f858SMichal Kalderon }; 212430d5f858SMichal Kalderon 2125351a4dedSYuval Mintz /* init array header: raw */ 2126fe56b9e6SYuval Mintz struct init_array_raw_hdr { 21275ab90341SAlexander Lobakin __le32 data; 2128fe56b9e6SYuval Mintz #define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF 2129fe56b9e6SYuval Mintz #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0 2130351a4dedSYuval Mintz #define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF 2131fe56b9e6SYuval Mintz #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4 2132fe56b9e6SYuval Mintz }; 2133fe56b9e6SYuval Mintz 2134351a4dedSYuval Mintz /* init array header: standard */ 2135fe56b9e6SYuval Mintz struct init_array_standard_hdr { 21365ab90341SAlexander Lobakin __le32 data; 2137fe56b9e6SYuval Mintz #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF 2138fe56b9e6SYuval Mintz #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0 2139fe56b9e6SYuval Mintz #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF 2140fe56b9e6SYuval Mintz #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4 2141fe56b9e6SYuval Mintz }; 2142fe56b9e6SYuval Mintz 2143351a4dedSYuval Mintz /* init array header: zipped */ 2144fe56b9e6SYuval Mintz struct init_array_zipped_hdr { 21455ab90341SAlexander Lobakin __le32 data; 2146fe56b9e6SYuval Mintz #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF 2147fe56b9e6SYuval Mintz #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0 2148fe56b9e6SYuval Mintz #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF 2149fe56b9e6SYuval Mintz #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4 2150fe56b9e6SYuval Mintz }; 2151fe56b9e6SYuval Mintz 2152351a4dedSYuval Mintz /* init array header: pattern */ 2153fe56b9e6SYuval Mintz struct init_array_pattern_hdr { 21545ab90341SAlexander Lobakin __le32 data; 2155fe56b9e6SYuval Mintz #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF 2156fe56b9e6SYuval Mintz #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0 2157fe56b9e6SYuval Mintz #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF 2158fe56b9e6SYuval Mintz #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4 2159fe56b9e6SYuval Mintz #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF 2160fe56b9e6SYuval Mintz #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8 2161fe56b9e6SYuval Mintz }; 2162fe56b9e6SYuval Mintz 2163351a4dedSYuval Mintz /* init array header union */ 2164fe56b9e6SYuval Mintz union init_array_hdr { 2165351a4dedSYuval Mintz struct init_array_raw_hdr raw; 2166fe56b9e6SYuval Mintz struct init_array_standard_hdr standard; 2167351a4dedSYuval Mintz struct init_array_zipped_hdr zipped; 2168351a4dedSYuval Mintz struct init_array_pattern_hdr pattern; 2169fe56b9e6SYuval Mintz }; 2170fe56b9e6SYuval Mintz 2171351a4dedSYuval Mintz /* init array types */ 2172fe56b9e6SYuval Mintz enum init_array_types { 2173351a4dedSYuval Mintz INIT_ARR_STANDARD, 2174351a4dedSYuval Mintz INIT_ARR_ZIPPED, 2175351a4dedSYuval Mintz INIT_ARR_PATTERN, 2176fe56b9e6SYuval Mintz MAX_INIT_ARRAY_TYPES 2177fe56b9e6SYuval Mintz }; 2178fe56b9e6SYuval Mintz 2179fe56b9e6SYuval Mintz /* init operation: callback */ 2180fe56b9e6SYuval Mintz struct init_callback_op { 21815ab90341SAlexander Lobakin __le32 op_data; 2182fe56b9e6SYuval Mintz #define INIT_CALLBACK_OP_OP_MASK 0xF 2183fe56b9e6SYuval Mintz #define INIT_CALLBACK_OP_OP_SHIFT 0 2184fe56b9e6SYuval Mintz #define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF 2185fe56b9e6SYuval Mintz #define INIT_CALLBACK_OP_RESERVED_SHIFT 4 21865ab90341SAlexander Lobakin __le16 callback_id; 21875ab90341SAlexander Lobakin __le16 block_id; 2188fe56b9e6SYuval Mintz }; 2189fe56b9e6SYuval Mintz 2190fe56b9e6SYuval Mintz /* init operation: delay */ 2191fe56b9e6SYuval Mintz struct init_delay_op { 21925ab90341SAlexander Lobakin __le32 op_data; 2193fe56b9e6SYuval Mintz #define INIT_DELAY_OP_OP_MASK 0xF 2194fe56b9e6SYuval Mintz #define INIT_DELAY_OP_OP_SHIFT 0 2195fe56b9e6SYuval Mintz #define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF 2196fe56b9e6SYuval Mintz #define INIT_DELAY_OP_RESERVED_SHIFT 4 21975ab90341SAlexander Lobakin __le32 delay; 2198fe56b9e6SYuval Mintz }; 2199fe56b9e6SYuval Mintz 2200fe56b9e6SYuval Mintz /* init operation: if_mode */ 2201fe56b9e6SYuval Mintz struct init_if_mode_op { 22025ab90341SAlexander Lobakin __le32 op_data; 2203fe56b9e6SYuval Mintz #define INIT_IF_MODE_OP_OP_MASK 0xF 2204fe56b9e6SYuval Mintz #define INIT_IF_MODE_OP_OP_SHIFT 0 2205fe56b9e6SYuval Mintz #define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF 2206fe56b9e6SYuval Mintz #define INIT_IF_MODE_OP_RESERVED1_SHIFT 4 2207fe56b9e6SYuval Mintz #define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF 2208fe56b9e6SYuval Mintz #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16 22095ab90341SAlexander Lobakin __le16 reserved2; 22105ab90341SAlexander Lobakin __le16 modes_buf_offset; 2211fe56b9e6SYuval Mintz }; 2212fe56b9e6SYuval Mintz 2213fe56b9e6SYuval Mintz /* init operation: if_phase */ 2214fe56b9e6SYuval Mintz struct init_if_phase_op { 22155ab90341SAlexander Lobakin __le32 op_data; 2216fe56b9e6SYuval Mintz #define INIT_IF_PHASE_OP_OP_MASK 0xF 2217fe56b9e6SYuval Mintz #define INIT_IF_PHASE_OP_OP_SHIFT 0 22180500a70dSMichal Kalderon #define INIT_IF_PHASE_OP_RESERVED1_MASK 0xFFF 22190500a70dSMichal Kalderon #define INIT_IF_PHASE_OP_RESERVED1_SHIFT 4 2220fe56b9e6SYuval Mintz #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF 2221fe56b9e6SYuval Mintz #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16 22225ab90341SAlexander Lobakin __le32 phase_data; 2223351a4dedSYuval Mintz #define INIT_IF_PHASE_OP_PHASE_MASK 0xFF 2224fe56b9e6SYuval Mintz #define INIT_IF_PHASE_OP_PHASE_SHIFT 0 2225fe56b9e6SYuval Mintz #define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF 2226fe56b9e6SYuval Mintz #define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8 2227351a4dedSYuval Mintz #define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF 2228fe56b9e6SYuval Mintz #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16 2229fe56b9e6SYuval Mintz }; 2230fe56b9e6SYuval Mintz 2231fe56b9e6SYuval Mintz /* init mode operators */ 2232fe56b9e6SYuval Mintz enum init_mode_ops { 2233351a4dedSYuval Mintz INIT_MODE_OP_NOT, 2234351a4dedSYuval Mintz INIT_MODE_OP_OR, 2235351a4dedSYuval Mintz INIT_MODE_OP_AND, 2236fe56b9e6SYuval Mintz MAX_INIT_MODE_OPS 2237fe56b9e6SYuval Mintz }; 2238fe56b9e6SYuval Mintz 2239fe56b9e6SYuval Mintz /* init operation: raw */ 2240fe56b9e6SYuval Mintz struct init_raw_op { 22415ab90341SAlexander Lobakin __le32 op_data; 2242fe56b9e6SYuval Mintz #define INIT_RAW_OP_OP_MASK 0xF 2243fe56b9e6SYuval Mintz #define INIT_RAW_OP_OP_SHIFT 0 2244351a4dedSYuval Mintz #define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF 2245fe56b9e6SYuval Mintz #define INIT_RAW_OP_PARAM1_SHIFT 4 22465ab90341SAlexander Lobakin __le32 param2; 2247fe56b9e6SYuval Mintz }; 2248fe56b9e6SYuval Mintz 2249fe56b9e6SYuval Mintz /* init array params */ 2250fe56b9e6SYuval Mintz struct init_op_array_params { 22515ab90341SAlexander Lobakin __le16 size; 22525ab90341SAlexander Lobakin __le16 offset; 2253fe56b9e6SYuval Mintz }; 2254fe56b9e6SYuval Mintz 2255fe56b9e6SYuval Mintz /* Write init operation arguments */ 2256fe56b9e6SYuval Mintz union init_write_args { 22575ab90341SAlexander Lobakin __le32 inline_val; 22585ab90341SAlexander Lobakin __le32 zeros_count; 22595ab90341SAlexander Lobakin __le32 array_offset; 2260fe56b9e6SYuval Mintz struct init_op_array_params runtime; 2261fe56b9e6SYuval Mintz }; 2262fe56b9e6SYuval Mintz 2263fe56b9e6SYuval Mintz /* init operation: write */ 2264fe56b9e6SYuval Mintz struct init_write_op { 22655ab90341SAlexander Lobakin __le32 data; 2266fe56b9e6SYuval Mintz #define INIT_WRITE_OP_OP_MASK 0xF 2267fe56b9e6SYuval Mintz #define INIT_WRITE_OP_OP_SHIFT 0 2268fe56b9e6SYuval Mintz #define INIT_WRITE_OP_SOURCE_MASK 0x7 2269fe56b9e6SYuval Mintz #define INIT_WRITE_OP_SOURCE_SHIFT 4 2270fe56b9e6SYuval Mintz #define INIT_WRITE_OP_RESERVED_MASK 0x1 2271fe56b9e6SYuval Mintz #define INIT_WRITE_OP_RESERVED_SHIFT 7 2272fe56b9e6SYuval Mintz #define INIT_WRITE_OP_WIDE_BUS_MASK 0x1 2273fe56b9e6SYuval Mintz #define INIT_WRITE_OP_WIDE_BUS_SHIFT 8 2274fe56b9e6SYuval Mintz #define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF 2275fe56b9e6SYuval Mintz #define INIT_WRITE_OP_ADDRESS_SHIFT 9 2276351a4dedSYuval Mintz union init_write_args args; 2277fe56b9e6SYuval Mintz }; 2278fe56b9e6SYuval Mintz 2279fe56b9e6SYuval Mintz /* init operation: read */ 2280fe56b9e6SYuval Mintz struct init_read_op { 22815ab90341SAlexander Lobakin __le32 op_data; 2282fe56b9e6SYuval Mintz #define INIT_READ_OP_OP_MASK 0xF 2283fe56b9e6SYuval Mintz #define INIT_READ_OP_OP_SHIFT 0 2284fc48b7a6SYuval Mintz #define INIT_READ_OP_POLL_TYPE_MASK 0xF 2285fc48b7a6SYuval Mintz #define INIT_READ_OP_POLL_TYPE_SHIFT 4 2286fe56b9e6SYuval Mintz #define INIT_READ_OP_RESERVED_MASK 0x1 2287fc48b7a6SYuval Mintz #define INIT_READ_OP_RESERVED_SHIFT 8 2288fe56b9e6SYuval Mintz #define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF 2289fe56b9e6SYuval Mintz #define INIT_READ_OP_ADDRESS_SHIFT 9 22905ab90341SAlexander Lobakin __le32 expected_val; 2291fe56b9e6SYuval Mintz }; 2292fe56b9e6SYuval Mintz 2293fe56b9e6SYuval Mintz /* Init operations union */ 2294fe56b9e6SYuval Mintz union init_op { 2295351a4dedSYuval Mintz struct init_raw_op raw; 2296351a4dedSYuval Mintz struct init_write_op write; 2297351a4dedSYuval Mintz struct init_read_op read; 2298351a4dedSYuval Mintz struct init_if_mode_op if_mode; 2299351a4dedSYuval Mintz struct init_if_phase_op if_phase; 2300351a4dedSYuval Mintz struct init_callback_op callback; 2301351a4dedSYuval Mintz struct init_delay_op delay; 2302fe56b9e6SYuval Mintz }; 2303fe56b9e6SYuval Mintz 2304fe56b9e6SYuval Mintz /* Init command operation types */ 2305fe56b9e6SYuval Mintz enum init_op_types { 2306351a4dedSYuval Mintz INIT_OP_READ, 2307351a4dedSYuval Mintz INIT_OP_WRITE, 2308fe56b9e6SYuval Mintz INIT_OP_IF_MODE, 2309fe56b9e6SYuval Mintz INIT_OP_IF_PHASE, 2310351a4dedSYuval Mintz INIT_OP_DELAY, 2311351a4dedSYuval Mintz INIT_OP_CALLBACK, 2312fe56b9e6SYuval Mintz MAX_INIT_OP_TYPES 2313fe56b9e6SYuval Mintz }; 2314fe56b9e6SYuval Mintz 2315351a4dedSYuval Mintz /* init polling types */ 2316fc48b7a6SYuval Mintz enum init_poll_types { 2317351a4dedSYuval Mintz INIT_POLL_NONE, 2318351a4dedSYuval Mintz INIT_POLL_EQ, 2319351a4dedSYuval Mintz INIT_POLL_OR, 2320351a4dedSYuval Mintz INIT_POLL_AND, 2321fc48b7a6SYuval Mintz MAX_INIT_POLL_TYPES 2322fc48b7a6SYuval Mintz }; 2323fc48b7a6SYuval Mintz 2324fe56b9e6SYuval Mintz /* init source types */ 2325fe56b9e6SYuval Mintz enum init_source_types { 2326351a4dedSYuval Mintz INIT_SRC_INLINE, 2327351a4dedSYuval Mintz INIT_SRC_ZEROS, 2328351a4dedSYuval Mintz INIT_SRC_ARRAY, 2329351a4dedSYuval Mintz INIT_SRC_RUNTIME, 2330fe56b9e6SYuval Mintz MAX_INIT_SOURCE_TYPES 2331fe56b9e6SYuval Mintz }; 2332fe56b9e6SYuval Mintz 2333fe56b9e6SYuval Mintz /* Internal RAM Offsets macro data */ 2334fe56b9e6SYuval Mintz struct iro { 233550bc60cbSMichal Kalderon u32 base; 233650bc60cbSMichal Kalderon u16 m1; 233750bc60cbSMichal Kalderon u16 m2; 233850bc60cbSMichal Kalderon u16 m3; 233950bc60cbSMichal Kalderon u16 size; 2340fe56b9e6SYuval Mintz }; 2341fe56b9e6SYuval Mintz 2342fe56b9e6SYuval Mintz /* Win 2 */ 234305fafbfbSYuval Mintz #define GTT_BAR0_MAP_REG_IGU_CMD 0x00f000UL 2344351a4dedSYuval Mintz 2345fe56b9e6SYuval Mintz /* Win 3 */ 234605fafbfbSYuval Mintz #define GTT_BAR0_MAP_REG_TSDM_RAM 0x010000UL 2347351a4dedSYuval Mintz 2348fe56b9e6SYuval Mintz /* Win 4 */ 234905fafbfbSYuval Mintz #define GTT_BAR0_MAP_REG_MSDM_RAM 0x011000UL 2350351a4dedSYuval Mintz 2351fe56b9e6SYuval Mintz /* Win 5 */ 235205fafbfbSYuval Mintz #define GTT_BAR0_MAP_REG_MSDM_RAM_1024 0x012000UL 2353351a4dedSYuval Mintz 2354fe56b9e6SYuval Mintz /* Win 6 */ 23552d22bc83SMichal Kalderon #define GTT_BAR0_MAP_REG_MSDM_RAM_2048 0x013000UL 2356351a4dedSYuval Mintz 2357fe56b9e6SYuval Mintz /* Win 7 */ 23582d22bc83SMichal Kalderon #define GTT_BAR0_MAP_REG_USDM_RAM 0x014000UL 2359351a4dedSYuval Mintz 2360fe56b9e6SYuval Mintz /* Win 8 */ 23612d22bc83SMichal Kalderon #define GTT_BAR0_MAP_REG_USDM_RAM_1024 0x015000UL 2362351a4dedSYuval Mintz 2363fe56b9e6SYuval Mintz /* Win 9 */ 23642d22bc83SMichal Kalderon #define GTT_BAR0_MAP_REG_USDM_RAM_2048 0x016000UL 2365351a4dedSYuval Mintz 2366fe56b9e6SYuval Mintz /* Win 10 */ 23672d22bc83SMichal Kalderon #define GTT_BAR0_MAP_REG_XSDM_RAM 0x017000UL 2368351a4dedSYuval Mintz 2369fe56b9e6SYuval Mintz /* Win 11 */ 23702d22bc83SMichal Kalderon #define GTT_BAR0_MAP_REG_XSDM_RAM_1024 0x018000UL 23712d22bc83SMichal Kalderon 23722d22bc83SMichal Kalderon /* Win 12 */ 23732d22bc83SMichal Kalderon #define GTT_BAR0_MAP_REG_YSDM_RAM 0x019000UL 23742d22bc83SMichal Kalderon 23752d22bc83SMichal Kalderon /* Win 13 */ 23762d22bc83SMichal Kalderon #define GTT_BAR0_MAP_REG_PSDM_RAM 0x01a000UL 2377fe56b9e6SYuval Mintz 2378fe40a830SPrabhakar Kushwaha /* Returns the VOQ based on port and TC */ 2379fe40a830SPrabhakar Kushwaha #define VOQ(port, tc, max_phys_tcs_per_port) ((tc) == \ 2380fe40a830SPrabhakar Kushwaha PURE_LB_TC ? NUM_OF_PHYS_TCS *\ 2381fe40a830SPrabhakar Kushwaha MAX_NUM_PORTS_BB + \ 2382fe40a830SPrabhakar Kushwaha (port) : (port) * \ 2383fe40a830SPrabhakar Kushwaha (max_phys_tcs_per_port) + (tc)) 2384fe40a830SPrabhakar Kushwaha 2385fe40a830SPrabhakar Kushwaha struct init_qm_pq_params; 2386fe40a830SPrabhakar Kushwaha 2387fe56b9e6SYuval Mintz /** 238819198e4eSPrabhakar Kushwaha * qed_qm_pf_mem_size(): Prepare QM ILT sizes. 238919198e4eSPrabhakar Kushwaha * 239019198e4eSPrabhakar Kushwaha * @num_pf_cids: Number of connections used by this PF. 239119198e4eSPrabhakar Kushwaha * @num_vf_cids: Number of connections used by VFs of this PF. 239219198e4eSPrabhakar Kushwaha * @num_tids: Number of tasks used by this PF. 239319198e4eSPrabhakar Kushwaha * @num_pf_pqs: Number of PQs used by this PF. 239419198e4eSPrabhakar Kushwaha * @num_vf_pqs: Number of PQs used by VFs of this PF. 239519198e4eSPrabhakar Kushwaha * 239619198e4eSPrabhakar Kushwaha * Return: The required host memory size in 4KB units. 2397fe56b9e6SYuval Mintz * 2398fe56b9e6SYuval Mintz * Returns the required host memory size in 4KB units. 2399fe56b9e6SYuval Mintz * Must be called before all QM init HSI functions. 2400fe56b9e6SYuval Mintz */ 2401da090917STomer Tayar u32 qed_qm_pf_mem_size(u32 num_pf_cids, 2402fe56b9e6SYuval Mintz u32 num_vf_cids, 2403351a4dedSYuval Mintz u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs); 2404fe56b9e6SYuval Mintz 2405fe56b9e6SYuval Mintz struct qed_qm_common_rt_init_params { 2406fe56b9e6SYuval Mintz u8 max_ports_per_engine; 2407fe56b9e6SYuval Mintz u8 max_phys_tcs_per_port; 2408fe56b9e6SYuval Mintz bool pf_rl_en; 2409fe56b9e6SYuval Mintz bool pf_wfq_en; 241092fae6fbSMichal Kalderon bool global_rl_en; 2411fe56b9e6SYuval Mintz bool vport_wfq_en; 2412fe56b9e6SYuval Mintz struct init_qm_port_params *port_params; 2413fe40a830SPrabhakar Kushwaha struct init_qm_global_rl_params 2414fe40a830SPrabhakar Kushwaha global_rl_params[COMMON_MAX_QM_GLOBAL_RLS]; 2415fe56b9e6SYuval Mintz }; 2416fe56b9e6SYuval Mintz 2417fe40a830SPrabhakar Kushwaha /** 2418fe40a830SPrabhakar Kushwaha * qed_qm_common_rt_init(): Prepare QM runtime init values for the 2419fe40a830SPrabhakar Kushwaha * engine phase. 2420fe40a830SPrabhakar Kushwaha * 2421fe40a830SPrabhakar Kushwaha * @p_hwfn: HW device data. 2422fe40a830SPrabhakar Kushwaha * @p_params: Parameters. 2423fe40a830SPrabhakar Kushwaha * 2424fe40a830SPrabhakar Kushwaha * Return: 0 on success, -1 on error. 2425fe40a830SPrabhakar Kushwaha */ 2426351a4dedSYuval Mintz int qed_qm_common_rt_init(struct qed_hwfn *p_hwfn, 2427fe56b9e6SYuval Mintz struct qed_qm_common_rt_init_params *p_params); 2428fe56b9e6SYuval Mintz 2429fe56b9e6SYuval Mintz struct qed_qm_pf_rt_init_params { 2430fe56b9e6SYuval Mintz u8 port_id; 2431fe56b9e6SYuval Mintz u8 pf_id; 2432fe56b9e6SYuval Mintz u8 max_phys_tcs_per_port; 2433da090917STomer Tayar bool is_pf_loading; 2434fe56b9e6SYuval Mintz u32 num_pf_cids; 2435fe56b9e6SYuval Mintz u32 num_vf_cids; 2436fe56b9e6SYuval Mintz u32 num_tids; 2437fe56b9e6SYuval Mintz u16 start_pq; 2438fe56b9e6SYuval Mintz u16 num_pf_pqs; 2439fe56b9e6SYuval Mintz u16 num_vf_pqs; 244092fae6fbSMichal Kalderon u16 start_vport; 244192fae6fbSMichal Kalderon u16 num_vports; 2442fe40a830SPrabhakar Kushwaha u16 start_rl; 2443fe40a830SPrabhakar Kushwaha u16 num_rls; 244405fafbfbSYuval Mintz u16 pf_wfq; 2445fe56b9e6SYuval Mintz u32 pf_rl; 2446fe40a830SPrabhakar Kushwaha u32 link_speed; 2447fe56b9e6SYuval Mintz struct init_qm_pq_params *pq_params; 2448fe56b9e6SYuval Mintz struct init_qm_vport_params *vport_params; 2449fe40a830SPrabhakar Kushwaha struct init_qm_rl_params *rl_params; 2450fe56b9e6SYuval Mintz }; 2451fe56b9e6SYuval Mintz 2452fe40a830SPrabhakar Kushwaha /** 2453fe40a830SPrabhakar Kushwaha * qed_qm_pf_rt_init(): Prepare QM runtime init values for the PF phase. 2454fe40a830SPrabhakar Kushwaha * 2455fe40a830SPrabhakar Kushwaha * @p_hwfn: HW device data. 2456fe40a830SPrabhakar Kushwaha * @p_ptt: Ptt window used for writing the registers 2457fe40a830SPrabhakar Kushwaha * @p_params: Parameters. 2458fe40a830SPrabhakar Kushwaha * 2459fe40a830SPrabhakar Kushwaha * Return: 0 on success, -1 on error. 2460fe40a830SPrabhakar Kushwaha */ 2461fe56b9e6SYuval Mintz int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn, 2462fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2463fe56b9e6SYuval Mintz struct qed_qm_pf_rt_init_params *p_params); 2464fe56b9e6SYuval Mintz 2465fe56b9e6SYuval Mintz /** 246619198e4eSPrabhakar Kushwaha * qed_init_pf_wfq(): Initializes the WFQ weight of the specified PF. 2467351a4dedSYuval Mintz * 246819198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 246919198e4eSPrabhakar Kushwaha * @p_ptt: Ptt window used for writing the registers 247019198e4eSPrabhakar Kushwaha * @pf_id: PF ID 247119198e4eSPrabhakar Kushwaha * @pf_wfq: WFQ weight. Must be non-zero. 2472351a4dedSYuval Mintz * 247319198e4eSPrabhakar Kushwaha * Return: 0 on success, -1 on error. 2474351a4dedSYuval Mintz */ 2475351a4dedSYuval Mintz int qed_init_pf_wfq(struct qed_hwfn *p_hwfn, 2476351a4dedSYuval Mintz struct qed_ptt *p_ptt, u8 pf_id, u16 pf_wfq); 2477351a4dedSYuval Mintz 2478351a4dedSYuval Mintz /** 247919198e4eSPrabhakar Kushwaha * qed_init_pf_rl(): Initializes the rate limit of the specified PF 2480fe56b9e6SYuval Mintz * 248119198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 248219198e4eSPrabhakar Kushwaha * @p_ptt: Ptt window used for writing the registers. 248319198e4eSPrabhakar Kushwaha * @pf_id: PF ID. 248419198e4eSPrabhakar Kushwaha * @pf_rl: rate limit in Mb/sec units 2485fe56b9e6SYuval Mintz * 248619198e4eSPrabhakar Kushwaha * Return: 0 on success, -1 on error. 2487fe56b9e6SYuval Mintz */ 2488fe56b9e6SYuval Mintz int qed_init_pf_rl(struct qed_hwfn *p_hwfn, 2489351a4dedSYuval Mintz struct qed_ptt *p_ptt, u8 pf_id, u32 pf_rl); 2490fe56b9e6SYuval Mintz 2491fe56b9e6SYuval Mintz /** 249219198e4eSPrabhakar Kushwaha * qed_init_vport_wfq(): Initializes the WFQ weight of the specified VPORT 2493351a4dedSYuval Mintz * 249419198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 249519198e4eSPrabhakar Kushwaha * @p_ptt: Ptt window used for writing the registers 249619198e4eSPrabhakar Kushwaha * @first_tx_pq_id: An array containing the first Tx PQ ID associated 2497351a4dedSYuval Mintz * with the VPORT for each TC. This array is filled by 2498351a4dedSYuval Mintz * qed_qm_pf_rt_init 249919198e4eSPrabhakar Kushwaha * @wfq: WFQ weight. Must be non-zero. 2500351a4dedSYuval Mintz * 250119198e4eSPrabhakar Kushwaha * Return: 0 on success, -1 on error. 2502351a4dedSYuval Mintz */ 2503351a4dedSYuval Mintz int qed_init_vport_wfq(struct qed_hwfn *p_hwfn, 2504351a4dedSYuval Mintz struct qed_ptt *p_ptt, 250592fae6fbSMichal Kalderon u16 first_tx_pq_id[NUM_OF_TCS], u16 wfq); 2506351a4dedSYuval Mintz 2507351a4dedSYuval Mintz /** 2508fe40a830SPrabhakar Kushwaha * qed_init_vport_tc_wfq(): Initializes the WFQ weight of the specified 2509fe40a830SPrabhakar Kushwaha * VPORT and TC. 2510fe40a830SPrabhakar Kushwaha * 2511fe40a830SPrabhakar Kushwaha * @p_hwfn: HW device data. 2512fe40a830SPrabhakar Kushwaha * @p_ptt: Ptt window used for writing the registers. 2513fe40a830SPrabhakar Kushwaha * @first_tx_pq_id: The first Tx PQ ID associated with the VPORT and TC. 2514fe40a830SPrabhakar Kushwaha * (filled by qed_qm_pf_rt_init). 2515fe40a830SPrabhakar Kushwaha * @weight: VPORT+TC WFQ weight. 2516fe40a830SPrabhakar Kushwaha * 2517fe40a830SPrabhakar Kushwaha * Return: 0 on success, -1 on error. 2518fe40a830SPrabhakar Kushwaha */ 2519fe40a830SPrabhakar Kushwaha int qed_init_vport_tc_wfq(struct qed_hwfn *p_hwfn, 2520fe40a830SPrabhakar Kushwaha struct qed_ptt *p_ptt, 2521fe40a830SPrabhakar Kushwaha u16 first_tx_pq_id, u16 weight); 2522fe40a830SPrabhakar Kushwaha 2523fe40a830SPrabhakar Kushwaha /** 252419198e4eSPrabhakar Kushwaha * qed_init_global_rl(): Initializes the rate limit of the specified 252519198e4eSPrabhakar Kushwaha * rate limiter. 2526fe56b9e6SYuval Mintz * 252719198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 252819198e4eSPrabhakar Kushwaha * @p_ptt: Ptt window used for writing the registers. 252919198e4eSPrabhakar Kushwaha * @rl_id: RL ID. 253019198e4eSPrabhakar Kushwaha * @rate_limit: Rate limit in Mb/sec units 2531fe40a830SPrabhakar Kushwaha * @vport_rl_type: Vport RL type. 2532fe56b9e6SYuval Mintz * 253319198e4eSPrabhakar Kushwaha * Return: 0 on success, -1 on error. 2534fe56b9e6SYuval Mintz */ 253592fae6fbSMichal Kalderon int qed_init_global_rl(struct qed_hwfn *p_hwfn, 2536da090917STomer Tayar struct qed_ptt *p_ptt, 2537fe40a830SPrabhakar Kushwaha u16 rl_id, u32 rate_limit, 2538fe40a830SPrabhakar Kushwaha enum init_qm_rl_type vport_rl_type); 2539da090917STomer Tayar 2540fe56b9e6SYuval Mintz /** 254119198e4eSPrabhakar Kushwaha * qed_send_qm_stop_cmd(): Sends a stop command to the QM. 2542fe56b9e6SYuval Mintz * 254319198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 254419198e4eSPrabhakar Kushwaha * @p_ptt: Ptt window used for writing the registers. 254519198e4eSPrabhakar Kushwaha * @is_release_cmd: true for release, false for stop. 254619198e4eSPrabhakar Kushwaha * @is_tx_pq: true for Tx PQs, false for Other PQs. 254719198e4eSPrabhakar Kushwaha * @start_pq: first PQ ID to stop 254819198e4eSPrabhakar Kushwaha * @num_pqs: Number of PQs to stop, starting from start_pq. 2549fe56b9e6SYuval Mintz * 255019198e4eSPrabhakar Kushwaha * Return: Bool, true if successful, false if timeout occurred while waiting 255119198e4eSPrabhakar Kushwaha * for QM command done. 2552fe56b9e6SYuval Mintz */ 2553fe56b9e6SYuval Mintz bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn, 2554fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2555fe56b9e6SYuval Mintz bool is_release_cmd, 2556351a4dedSYuval Mintz bool is_tx_pq, u16 start_pq, u16 num_pqs); 2557fe56b9e6SYuval Mintz 2558351a4dedSYuval Mintz /** 255919198e4eSPrabhakar Kushwaha * qed_set_vxlan_dest_port(): Initializes vxlan tunnel destination udp port. 2560351a4dedSYuval Mintz * 256119198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 256219198e4eSPrabhakar Kushwaha * @p_ptt: Ptt window used for writing the registers. 256319198e4eSPrabhakar Kushwaha * @dest_port: vxlan destination udp port. 256419198e4eSPrabhakar Kushwaha * 256519198e4eSPrabhakar Kushwaha * Return: Void. 2566351a4dedSYuval Mintz */ 2567464f6645SManish Chopra void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn, 2568464f6645SManish Chopra struct qed_ptt *p_ptt, u16 dest_port); 2569351a4dedSYuval Mintz 2570351a4dedSYuval Mintz /** 257119198e4eSPrabhakar Kushwaha * qed_set_vxlan_enable(): Enable or disable VXLAN tunnel in HW. 2572351a4dedSYuval Mintz * 257319198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 257419198e4eSPrabhakar Kushwaha * @p_ptt: Ptt window used for writing the registers. 257519198e4eSPrabhakar Kushwaha * @vxlan_enable: vxlan enable flag. 257619198e4eSPrabhakar Kushwaha * 257719198e4eSPrabhakar Kushwaha * Return: Void. 2578351a4dedSYuval Mintz */ 2579464f6645SManish Chopra void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn, 2580464f6645SManish Chopra struct qed_ptt *p_ptt, bool vxlan_enable); 2581351a4dedSYuval Mintz 2582351a4dedSYuval Mintz /** 258319198e4eSPrabhakar Kushwaha * qed_set_gre_enable(): Enable or disable GRE tunnel in HW. 2584351a4dedSYuval Mintz * 258519198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 258619198e4eSPrabhakar Kushwaha * @p_ptt: Ptt window used for writing the registers. 258719198e4eSPrabhakar Kushwaha * @eth_gre_enable: Eth GRE enable flag. 258819198e4eSPrabhakar Kushwaha * @ip_gre_enable: IP GRE enable flag. 258919198e4eSPrabhakar Kushwaha * 259019198e4eSPrabhakar Kushwaha * Return: Void. 2591351a4dedSYuval Mintz */ 2592464f6645SManish Chopra void qed_set_gre_enable(struct qed_hwfn *p_hwfn, 2593351a4dedSYuval Mintz struct qed_ptt *p_ptt, 2594351a4dedSYuval Mintz bool eth_gre_enable, bool ip_gre_enable); 2595351a4dedSYuval Mintz 2596351a4dedSYuval Mintz /** 259719198e4eSPrabhakar Kushwaha * qed_set_geneve_dest_port(): Initializes geneve tunnel destination udp port 2598351a4dedSYuval Mintz * 259919198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 260019198e4eSPrabhakar Kushwaha * @p_ptt: Ptt window used for writing the registers. 260119198e4eSPrabhakar Kushwaha * @dest_port: Geneve destination udp port. 260219198e4eSPrabhakar Kushwaha * 260319198e4eSPrabhakar Kushwaha * Retur: Void. 2604351a4dedSYuval Mintz */ 2605464f6645SManish Chopra void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn, 2606464f6645SManish Chopra struct qed_ptt *p_ptt, u16 dest_port); 2607464f6645SManish Chopra 2608351a4dedSYuval Mintz /** 260919198e4eSPrabhakar Kushwaha * qed_set_geneve_enable(): Enable or disable GRE tunnel in HW. 2610351a4dedSYuval Mintz * 261119198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 261219198e4eSPrabhakar Kushwaha * @p_ptt: Ptt window used for writing the registers. 261319198e4eSPrabhakar Kushwaha * @eth_geneve_enable: Eth GENEVE enable flag. 261419198e4eSPrabhakar Kushwaha * @ip_geneve_enable: IP GENEVE enable flag. 261519198e4eSPrabhakar Kushwaha * 261619198e4eSPrabhakar Kushwaha * Return: Void. 2617351a4dedSYuval Mintz */ 2618351a4dedSYuval Mintz void qed_set_geneve_enable(struct qed_hwfn *p_hwfn, 2619351a4dedSYuval Mintz struct qed_ptt *p_ptt, 2620351a4dedSYuval Mintz bool eth_geneve_enable, bool ip_geneve_enable); 2621da090917STomer Tayar 262250bc60cbSMichal Kalderon void qed_set_vxlan_no_l2_enable(struct qed_hwfn *p_hwfn, 262350bc60cbSMichal Kalderon struct qed_ptt *p_ptt, bool enable); 262450bc60cbSMichal Kalderon 2625da090917STomer Tayar /** 262619198e4eSPrabhakar Kushwaha * qed_gft_disable(): Disable GFT. 2627da090917STomer Tayar * 262819198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 262919198e4eSPrabhakar Kushwaha * @p_ptt: Ptt window used for writing the registers. 263019198e4eSPrabhakar Kushwaha * @pf_id: PF on which to disable GFT. 263119198e4eSPrabhakar Kushwaha * 263219198e4eSPrabhakar Kushwaha * Return: Void. 2633da090917STomer Tayar */ 2634da090917STomer Tayar void qed_gft_disable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 pf_id); 2635da090917STomer Tayar 2636da090917STomer Tayar /** 263719198e4eSPrabhakar Kushwaha * qed_gft_config(): Enable and configure HW for GFT. 2638da090917STomer Tayar * 263919198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 264019198e4eSPrabhakar Kushwaha * @p_ptt: Ptt window used for writing the registers. 264119198e4eSPrabhakar Kushwaha * @pf_id: PF on which to enable GFT. 264219198e4eSPrabhakar Kushwaha * @tcp: Set profile tcp packets. 264319198e4eSPrabhakar Kushwaha * @udp: Set profile udp packet. 264419198e4eSPrabhakar Kushwaha * @ipv4: Set profile ipv4 packet. 264519198e4eSPrabhakar Kushwaha * @ipv6: Set profile ipv6 packet. 264619198e4eSPrabhakar Kushwaha * @profile_type: Define packet same fields. Use enum gft_profile_type. 264719198e4eSPrabhakar Kushwaha * 264819198e4eSPrabhakar Kushwaha * Return: Void. 2649da090917STomer Tayar */ 2650da090917STomer Tayar void qed_gft_config(struct qed_hwfn *p_hwfn, 2651da090917STomer Tayar struct qed_ptt *p_ptt, 2652da090917STomer Tayar u16 pf_id, 2653da090917STomer Tayar bool tcp, 2654da090917STomer Tayar bool udp, 2655da090917STomer Tayar bool ipv4, bool ipv6, enum gft_profile_type profile_type); 2656da090917STomer Tayar 2657da090917STomer Tayar /** 265819198e4eSPrabhakar Kushwaha * qed_enable_context_validation(): Enable and configure context 2659da090917STomer Tayar * validation. 2660da090917STomer Tayar * 266119198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 266219198e4eSPrabhakar Kushwaha * @p_ptt: Ptt window used for writing the registers. 266319198e4eSPrabhakar Kushwaha * 266419198e4eSPrabhakar Kushwaha * Return: Void. 2665da090917STomer Tayar */ 2666da090917STomer Tayar void qed_enable_context_validation(struct qed_hwfn *p_hwfn, 2667da090917STomer Tayar struct qed_ptt *p_ptt); 2668da090917STomer Tayar 2669da090917STomer Tayar /** 267019198e4eSPrabhakar Kushwaha * qed_calc_session_ctx_validation(): Calcualte validation byte for 2671da090917STomer Tayar * session context. 2672da090917STomer Tayar * 267319198e4eSPrabhakar Kushwaha * @p_ctx_mem: Pointer to context memory. 267419198e4eSPrabhakar Kushwaha * @ctx_size: Context size. 267519198e4eSPrabhakar Kushwaha * @ctx_type: Context type. 267619198e4eSPrabhakar Kushwaha * @cid: Context cid. 267719198e4eSPrabhakar Kushwaha * 267819198e4eSPrabhakar Kushwaha * Return: Void. 2679da090917STomer Tayar */ 2680da090917STomer Tayar void qed_calc_session_ctx_validation(void *p_ctx_mem, 2681da090917STomer Tayar u16 ctx_size, u8 ctx_type, u32 cid); 2682da090917STomer Tayar 2683da090917STomer Tayar /** 268419198e4eSPrabhakar Kushwaha * qed_calc_task_ctx_validation(): Calcualte validation byte for task 2685da090917STomer Tayar * context. 2686da090917STomer Tayar * 268719198e4eSPrabhakar Kushwaha * @p_ctx_mem: Pointer to context memory. 268819198e4eSPrabhakar Kushwaha * @ctx_size: Context size. 268919198e4eSPrabhakar Kushwaha * @ctx_type: Context type. 269019198e4eSPrabhakar Kushwaha * @tid: Context tid. 269119198e4eSPrabhakar Kushwaha * 269219198e4eSPrabhakar Kushwaha * Return: Void. 2693da090917STomer Tayar */ 2694da090917STomer Tayar void qed_calc_task_ctx_validation(void *p_ctx_mem, 2695da090917STomer Tayar u16 ctx_size, u8 ctx_type, u32 tid); 2696da090917STomer Tayar 2697da090917STomer Tayar /** 269819198e4eSPrabhakar Kushwaha * qed_memset_session_ctx(): Memset session context to 0 while 2699da090917STomer Tayar * preserving validation bytes. 2700da090917STomer Tayar * 270119198e4eSPrabhakar Kushwaha * @p_ctx_mem: Pointer to context memory. 270219198e4eSPrabhakar Kushwaha * @ctx_size: Size to initialzie. 270319198e4eSPrabhakar Kushwaha * @ctx_type: Context type. 270419198e4eSPrabhakar Kushwaha * 270519198e4eSPrabhakar Kushwaha * Return: Void. 2706da090917STomer Tayar */ 2707da090917STomer Tayar void qed_memset_session_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type); 2708da090917STomer Tayar 2709da090917STomer Tayar /** 271019198e4eSPrabhakar Kushwaha * qed_memset_task_ctx(): Memset task context to 0 while preserving 2711da090917STomer Tayar * validation bytes. 2712da090917STomer Tayar * 271319198e4eSPrabhakar Kushwaha * @p_ctx_mem: Pointer to context memory. 271419198e4eSPrabhakar Kushwaha * @ctx_size: size to initialzie. 271519198e4eSPrabhakar Kushwaha * @ctx_type: context type. 271619198e4eSPrabhakar Kushwaha * 271719198e4eSPrabhakar Kushwaha * Return: Void. 2718da090917STomer Tayar */ 2719da090917STomer Tayar void qed_memset_task_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type); 2720351a4dedSYuval Mintz 2721d52c89f1SMichal Kalderon #define NUM_STORMS 6 2722d52c89f1SMichal Kalderon 2723d52c89f1SMichal Kalderon /** 2724*7e9979e3SPrabhakar Kushwaha * qed_get_protocol_type_str(): Get a string for Protocol type. 2725*7e9979e3SPrabhakar Kushwaha * 2726*7e9979e3SPrabhakar Kushwaha * @protocol_type: Protocol type (using enum protocol_type). 2727*7e9979e3SPrabhakar Kushwaha * 2728*7e9979e3SPrabhakar Kushwaha * Return: String. 2729*7e9979e3SPrabhakar Kushwaha */ 2730*7e9979e3SPrabhakar Kushwaha const char *qed_get_protocol_type_str(u32 protocol_type); 2731*7e9979e3SPrabhakar Kushwaha 2732*7e9979e3SPrabhakar Kushwaha /** 2733*7e9979e3SPrabhakar Kushwaha * qed_get_ramrod_cmd_id_str(): Get a string for Ramrod command ID. 2734*7e9979e3SPrabhakar Kushwaha * 2735*7e9979e3SPrabhakar Kushwaha * @protocol_type: Protocol type (using enum protocol_type). 2736*7e9979e3SPrabhakar Kushwaha * @ramrod_cmd_id: Ramrod command ID (using per-protocol enum <protocol>_ramrod_cmd_id). 2737*7e9979e3SPrabhakar Kushwaha * 2738*7e9979e3SPrabhakar Kushwaha * Return: String. 2739*7e9979e3SPrabhakar Kushwaha */ 2740*7e9979e3SPrabhakar Kushwaha const char *qed_get_ramrod_cmd_id_str(u32 protocol_type, u32 ramrod_cmd_id); 2741*7e9979e3SPrabhakar Kushwaha 2742*7e9979e3SPrabhakar Kushwaha /** 274319198e4eSPrabhakar Kushwaha * qed_set_rdma_error_level(): Sets the RDMA assert level. 2744d52c89f1SMichal Kalderon * If the severity of the error will be 2745d52c89f1SMichal Kalderon * above the level, the FW will assert. 274619198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 274719198e4eSPrabhakar Kushwaha * @p_ptt: Ptt window used for writing the registers. 274819198e4eSPrabhakar Kushwaha * @assert_level: An array of assert levels for each storm. 2749d52c89f1SMichal Kalderon * 275019198e4eSPrabhakar Kushwaha * Return: Void. 2751d52c89f1SMichal Kalderon */ 2752d52c89f1SMichal Kalderon void qed_set_rdma_error_level(struct qed_hwfn *p_hwfn, 2753d52c89f1SMichal Kalderon struct qed_ptt *p_ptt, 2754d52c89f1SMichal Kalderon u8 assert_level[NUM_STORMS]); 275530d5f858SMichal Kalderon /** 275619198e4eSPrabhakar Kushwaha * qed_fw_overlay_mem_alloc(): Allocates and fills the FW overlay memory. 275730d5f858SMichal Kalderon * 275819198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 275919198e4eSPrabhakar Kushwaha * @fw_overlay_in_buf: The input FW overlay buffer. 276019198e4eSPrabhakar Kushwaha * @buf_size_in_bytes: The size of the input FW overlay buffer in bytes. 276130d5f858SMichal Kalderon * must be aligned to dwords. 276230d5f858SMichal Kalderon * 276319198e4eSPrabhakar Kushwaha * Return: A pointer to the allocated overlays memory, 276430d5f858SMichal Kalderon * or NULL in case of failures. 276530d5f858SMichal Kalderon */ 276630d5f858SMichal Kalderon struct phys_mem_desc * 276730d5f858SMichal Kalderon qed_fw_overlay_mem_alloc(struct qed_hwfn *p_hwfn, 276830d5f858SMichal Kalderon const u32 *const fw_overlay_in_buf, 276930d5f858SMichal Kalderon u32 buf_size_in_bytes); 277030d5f858SMichal Kalderon 277130d5f858SMichal Kalderon /** 277219198e4eSPrabhakar Kushwaha * qed_fw_overlay_init_ram(): Initializes the FW overlay RAM. 277330d5f858SMichal Kalderon * 277419198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 277519198e4eSPrabhakar Kushwaha * @p_ptt: Ptt window used for writing the registers. 277619198e4eSPrabhakar Kushwaha * @fw_overlay_mem: the allocated FW overlay memory. 277719198e4eSPrabhakar Kushwaha * 277819198e4eSPrabhakar Kushwaha * Return: Void. 277930d5f858SMichal Kalderon */ 278030d5f858SMichal Kalderon void qed_fw_overlay_init_ram(struct qed_hwfn *p_hwfn, 278130d5f858SMichal Kalderon struct qed_ptt *p_ptt, 278230d5f858SMichal Kalderon struct phys_mem_desc *fw_overlay_mem); 278330d5f858SMichal Kalderon 278430d5f858SMichal Kalderon /** 278519198e4eSPrabhakar Kushwaha * qed_fw_overlay_mem_free(): Frees the FW overlay memory. 278630d5f858SMichal Kalderon * 278719198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 278819198e4eSPrabhakar Kushwaha * @fw_overlay_mem: The allocated FW overlay memory to free. 278919198e4eSPrabhakar Kushwaha * 279019198e4eSPrabhakar Kushwaha * Return: Void. 279130d5f858SMichal Kalderon */ 279230d5f858SMichal Kalderon void qed_fw_overlay_mem_free(struct qed_hwfn *p_hwfn, 2793fe40a830SPrabhakar Kushwaha struct phys_mem_desc **fw_overlay_mem); 2794fe40a830SPrabhakar Kushwaha 2795fe40a830SPrabhakar Kushwaha #define PCICFG_OFFSET 0x2000 2796fe40a830SPrabhakar Kushwaha #define GRC_CONFIG_REG_PF_INIT_VF 0x624 2797fe40a830SPrabhakar Kushwaha 2798fe40a830SPrabhakar Kushwaha /* First VF_NUM for PF is encoded in this register. 2799fe40a830SPrabhakar Kushwaha * The number of VFs assigned to a PF is assumed to be a multiple of 8. 2800fe40a830SPrabhakar Kushwaha * Software should program these bits based on Total Number of VFs programmed 2801fe40a830SPrabhakar Kushwaha * for each PF. 2802fe40a830SPrabhakar Kushwaha * Since registers from 0x000-0x7ff are spilt across functions, each PF will 2803fe40a830SPrabhakar Kushwaha * have the same location for the same 4 bits 2804fe40a830SPrabhakar Kushwaha */ 2805fe40a830SPrabhakar Kushwaha #define GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK 0xff 2806d52c89f1SMichal Kalderon 2807fe56b9e6SYuval Mintz /* Runtime array offsets */ 2808fe56b9e6SYuval Mintz #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0 2809fe56b9e6SYuval Mintz #define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1 2810fe56b9e6SYuval Mintz #define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2 2811fe56b9e6SYuval Mintz #define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3 2812fe56b9e6SYuval Mintz #define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4 2813fe56b9e6SYuval Mintz #define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5 2814fe56b9e6SYuval Mintz #define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6 2815fe56b9e6SYuval Mintz #define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7 2816fe56b9e6SYuval Mintz #define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8 2817fe56b9e6SYuval Mintz #define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9 2818fe56b9e6SYuval Mintz #define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10 2819fe56b9e6SYuval Mintz #define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11 2820fe56b9e6SYuval Mintz #define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12 2821fe56b9e6SYuval Mintz #define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13 2822fe56b9e6SYuval Mintz #define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14 2823fe56b9e6SYuval Mintz #define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15 28246aebde8dSMichal Kalderon #define DORQ_REG_VF_ICID_BIT_SHIFT_NORM_RT_OFFSET 16 28256aebde8dSMichal Kalderon #define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 17 28266aebde8dSMichal Kalderon #define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 18 28276aebde8dSMichal Kalderon #define IGU_REG_PF_CONFIGURATION_RT_OFFSET 19 28286aebde8dSMichal Kalderon #define IGU_REG_VF_CONFIGURATION_RT_OFFSET 20 28296aebde8dSMichal Kalderon #define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 21 28306aebde8dSMichal Kalderon #define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 22 28316aebde8dSMichal Kalderon #define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 23 28326aebde8dSMichal Kalderon #define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 24 28336aebde8dSMichal Kalderon #define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 25 28346aebde8dSMichal Kalderon #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 26 28356aebde8dSMichal Kalderon #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736 28366aebde8dSMichal Kalderon #define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 762 28376aebde8dSMichal Kalderon #define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 736 28386aebde8dSMichal Kalderon #define CAU_REG_PI_MEMORY_RT_OFFSET 1498 2839fe56b9e6SYuval Mintz #define CAU_REG_PI_MEMORY_RT_SIZE 4416 28406aebde8dSMichal Kalderon #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 5914 28416aebde8dSMichal Kalderon #define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 5915 28426aebde8dSMichal Kalderon #define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 5916 28436aebde8dSMichal Kalderon #define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 5917 28446aebde8dSMichal Kalderon #define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 5918 28456aebde8dSMichal Kalderon #define PRS_REG_SEARCH_TCP_RT_OFFSET 5919 28466aebde8dSMichal Kalderon #define PRS_REG_SEARCH_FCOE_RT_OFFSET 5920 28476aebde8dSMichal Kalderon #define PRS_REG_SEARCH_ROCE_RT_OFFSET 5921 28486aebde8dSMichal Kalderon #define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 5922 28496aebde8dSMichal Kalderon #define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 5923 28506aebde8dSMichal Kalderon #define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 5924 28516aebde8dSMichal Kalderon #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 5925 28526aebde8dSMichal Kalderon #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 5926 28536aebde8dSMichal Kalderon #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 5927 28546aebde8dSMichal Kalderon #define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 5928 28556aebde8dSMichal Kalderon #define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 5929 28566aebde8dSMichal Kalderon #define SRC_REG_FIRSTFREE_RT_OFFSET 5930 2857fe56b9e6SYuval Mintz #define SRC_REG_FIRSTFREE_RT_SIZE 2 28586aebde8dSMichal Kalderon #define SRC_REG_LASTFREE_RT_OFFSET 5932 2859fe56b9e6SYuval Mintz #define SRC_REG_LASTFREE_RT_SIZE 2 28606aebde8dSMichal Kalderon #define SRC_REG_COUNTFREE_RT_OFFSET 5934 28616aebde8dSMichal Kalderon #define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 5935 28626aebde8dSMichal Kalderon #define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 5936 28636aebde8dSMichal Kalderon #define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 5937 28646aebde8dSMichal Kalderon #define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 5938 28656aebde8dSMichal Kalderon #define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 5939 28666aebde8dSMichal Kalderon #define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 5940 28676aebde8dSMichal Kalderon #define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 5941 28686aebde8dSMichal Kalderon #define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 5942 28696aebde8dSMichal Kalderon #define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 5943 28706aebde8dSMichal Kalderon #define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 5944 28716aebde8dSMichal Kalderon #define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 5945 28726aebde8dSMichal Kalderon #define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 5946 28736aebde8dSMichal Kalderon #define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 5947 28746aebde8dSMichal Kalderon #define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 5948 28756aebde8dSMichal Kalderon #define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 5949 28766aebde8dSMichal Kalderon #define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 5950 28776aebde8dSMichal Kalderon #define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 5951 28786aebde8dSMichal Kalderon #define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 5952 28796aebde8dSMichal Kalderon #define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 5953 28806aebde8dSMichal Kalderon #define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 5954 28816aebde8dSMichal Kalderon #define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 5955 28826aebde8dSMichal Kalderon #define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 5956 28836aebde8dSMichal Kalderon #define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 5957 28846aebde8dSMichal Kalderon #define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 5958 28856aebde8dSMichal Kalderon #define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 5959 28866aebde8dSMichal Kalderon #define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 5960 28876aebde8dSMichal Kalderon #define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 5961 28886aebde8dSMichal Kalderon #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 5962 28896aebde8dSMichal Kalderon #define PSWRQ2_REG_VF_BASE_RT_OFFSET 5963 28906aebde8dSMichal Kalderon #define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 5964 28916aebde8dSMichal Kalderon #define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 5965 28926aebde8dSMichal Kalderon #define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 5966 28936aebde8dSMichal Kalderon #define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 5967 28946aebde8dSMichal Kalderon #define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000 28956aebde8dSMichal Kalderon #define PGLUE_REG_B_VF_BASE_RT_OFFSET 27967 28966aebde8dSMichal Kalderon #define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 27968 28976aebde8dSMichal Kalderon #define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 27969 28986aebde8dSMichal Kalderon #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 27970 28996aebde8dSMichal Kalderon #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 27971 29006aebde8dSMichal Kalderon #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 27972 29016aebde8dSMichal Kalderon #define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 27973 29026aebde8dSMichal Kalderon #define TM_REG_VF_ENABLE_CONN_RT_OFFSET 27974 29036aebde8dSMichal Kalderon #define TM_REG_PF_ENABLE_CONN_RT_OFFSET 27975 29046aebde8dSMichal Kalderon #define TM_REG_PF_ENABLE_TASK_RT_OFFSET 27976 29056aebde8dSMichal Kalderon #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 27977 29066aebde8dSMichal Kalderon #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 27978 29076aebde8dSMichal Kalderon #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 27979 2908fe56b9e6SYuval Mintz #define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416 29096aebde8dSMichal Kalderon #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 28395 29106aebde8dSMichal Kalderon #define TM_REG_CONFIG_TASK_MEM_RT_SIZE 512 29116aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZE_0_RT_OFFSET 28907 29126aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZE_1_RT_OFFSET 28908 29136aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZE_2_RT_OFFSET 28909 29146aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 28910 29156aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 28911 29166aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 28912 29176aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 28913 29186aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 28914 29196aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 28915 29206aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 28916 29216aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 28917 29226aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 28918 29236aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 28919 29246aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 28920 29256aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 28921 29266aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 28922 29276aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 28923 29286aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 28924 29296aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 28925 29306aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 28926 29316aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 28927 29326aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 28928 29336aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 28929 29346aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 28930 29356aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 28931 29366aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 28932 29376aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 28933 29386aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 28934 29396aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 28935 29406aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 28936 29416aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 28937 29426aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 28938 29436aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 28939 29446aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 28940 29456aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 28941 29466aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 28942 29476aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 28943 29486aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 28944 29496aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 28945 29506aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 28946 29516aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 28947 29526aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 28948 29536aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 28949 29546aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 28950 29556aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 28951 29566aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 28952 29576aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 28953 29586aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 28954 29596aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 28955 29606aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 28956 29616aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 28957 29626aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 28958 29636aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 28959 29646aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 28960 29656aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 28961 29666aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 28962 29676aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 28963 29686aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 28964 29696aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 28965 29706aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 28966 29716aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 28967 29726aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 28968 29736aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 28969 29746aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 28970 29756aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 28971 29766aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 28972 29776aebde8dSMichal Kalderon #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 28973 29786aebde8dSMichal Kalderon #define QM_REG_BASEADDROTHERPQ_RT_OFFSET 28974 2979fe56b9e6SYuval Mintz #define QM_REG_BASEADDROTHERPQ_RT_SIZE 128 29806aebde8dSMichal Kalderon #define QM_REG_PTRTBLOTHER_RT_OFFSET 29102 2981da090917STomer Tayar #define QM_REG_PTRTBLOTHER_RT_SIZE 256 29826aebde8dSMichal Kalderon #define QM_REG_VOQCRDLINE_RT_OFFSET 29358 29836aebde8dSMichal Kalderon #define QM_REG_VOQCRDLINE_RT_SIZE 20 29846aebde8dSMichal Kalderon #define QM_REG_VOQINITCRDLINE_RT_OFFSET 29378 29856aebde8dSMichal Kalderon #define QM_REG_VOQINITCRDLINE_RT_SIZE 20 29866aebde8dSMichal Kalderon #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29398 29876aebde8dSMichal Kalderon #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29399 29886aebde8dSMichal Kalderon #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29400 29896aebde8dSMichal Kalderon #define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29401 29906aebde8dSMichal Kalderon #define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29402 29916aebde8dSMichal Kalderon #define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29403 29926aebde8dSMichal Kalderon #define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29404 29936aebde8dSMichal Kalderon #define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29405 29946aebde8dSMichal Kalderon #define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29406 29956aebde8dSMichal Kalderon #define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29407 29966aebde8dSMichal Kalderon #define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29408 29976aebde8dSMichal Kalderon #define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29409 29986aebde8dSMichal Kalderon #define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29410 29996aebde8dSMichal Kalderon #define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29411 30006aebde8dSMichal Kalderon #define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29412 30016aebde8dSMichal Kalderon #define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29413 30026aebde8dSMichal Kalderon #define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29414 30036aebde8dSMichal Kalderon #define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29415 30046aebde8dSMichal Kalderon #define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29416 30056aebde8dSMichal Kalderon #define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29417 30066aebde8dSMichal Kalderon #define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29418 30076aebde8dSMichal Kalderon #define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29419 30086aebde8dSMichal Kalderon #define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29420 30096aebde8dSMichal Kalderon #define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29421 30106aebde8dSMichal Kalderon #define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29422 30116aebde8dSMichal Kalderon #define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29423 30126aebde8dSMichal Kalderon #define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29424 30136aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_0_RT_OFFSET 29425 30146aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_1_RT_OFFSET 29426 30156aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_2_RT_OFFSET 29427 30166aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_3_RT_OFFSET 29428 30176aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_4_RT_OFFSET 29429 30186aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_5_RT_OFFSET 29430 30196aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_6_RT_OFFSET 29431 30206aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_7_RT_OFFSET 29432 30216aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_8_RT_OFFSET 29433 30226aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_9_RT_OFFSET 29434 30236aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_10_RT_OFFSET 29435 30246aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_11_RT_OFFSET 29436 30256aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_12_RT_OFFSET 29437 30266aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_13_RT_OFFSET 29438 30276aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_14_RT_OFFSET 29439 30286aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_15_RT_OFFSET 29440 30296aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_16_RT_OFFSET 29441 30306aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_17_RT_OFFSET 29442 30316aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_18_RT_OFFSET 29443 30326aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_19_RT_OFFSET 29444 30336aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_20_RT_OFFSET 29445 30346aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_21_RT_OFFSET 29446 30356aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_22_RT_OFFSET 29447 30366aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_23_RT_OFFSET 29448 30376aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_24_RT_OFFSET 29449 30386aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_25_RT_OFFSET 29450 30396aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_26_RT_OFFSET 29451 30406aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_27_RT_OFFSET 29452 30416aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_28_RT_OFFSET 29453 30426aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_29_RT_OFFSET 29454 30436aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_30_RT_OFFSET 29455 30446aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_31_RT_OFFSET 29456 30456aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_32_RT_OFFSET 29457 30466aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_33_RT_OFFSET 29458 30476aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_34_RT_OFFSET 29459 30486aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_35_RT_OFFSET 29460 30496aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_36_RT_OFFSET 29461 30506aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_37_RT_OFFSET 29462 30516aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_38_RT_OFFSET 29463 30526aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_39_RT_OFFSET 29464 30536aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_40_RT_OFFSET 29465 30546aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_41_RT_OFFSET 29466 30556aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_42_RT_OFFSET 29467 30566aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_43_RT_OFFSET 29468 30576aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_44_RT_OFFSET 29469 30586aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_45_RT_OFFSET 29470 30596aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_46_RT_OFFSET 29471 30606aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_47_RT_OFFSET 29472 30616aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_48_RT_OFFSET 29473 30626aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_49_RT_OFFSET 29474 30636aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_50_RT_OFFSET 29475 30646aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_51_RT_OFFSET 29476 30656aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_52_RT_OFFSET 29477 30666aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_53_RT_OFFSET 29478 30676aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_54_RT_OFFSET 29479 30686aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_55_RT_OFFSET 29480 30696aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_56_RT_OFFSET 29481 30706aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_57_RT_OFFSET 29482 30716aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_58_RT_OFFSET 29483 30726aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_59_RT_OFFSET 29484 30736aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_60_RT_OFFSET 29485 30746aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_61_RT_OFFSET 29486 30756aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_62_RT_OFFSET 29487 30766aebde8dSMichal Kalderon #define QM_REG_PQTX2PF_63_RT_OFFSET 29488 30776aebde8dSMichal Kalderon #define QM_REG_PQOTHER2PF_0_RT_OFFSET 29489 30786aebde8dSMichal Kalderon #define QM_REG_PQOTHER2PF_1_RT_OFFSET 29490 30796aebde8dSMichal Kalderon #define QM_REG_PQOTHER2PF_2_RT_OFFSET 29491 30806aebde8dSMichal Kalderon #define QM_REG_PQOTHER2PF_3_RT_OFFSET 29492 30816aebde8dSMichal Kalderon #define QM_REG_PQOTHER2PF_4_RT_OFFSET 29493 30826aebde8dSMichal Kalderon #define QM_REG_PQOTHER2PF_5_RT_OFFSET 29494 30836aebde8dSMichal Kalderon #define QM_REG_PQOTHER2PF_6_RT_OFFSET 29495 30846aebde8dSMichal Kalderon #define QM_REG_PQOTHER2PF_7_RT_OFFSET 29496 30856aebde8dSMichal Kalderon #define QM_REG_PQOTHER2PF_8_RT_OFFSET 29497 30866aebde8dSMichal Kalderon #define QM_REG_PQOTHER2PF_9_RT_OFFSET 29498 30876aebde8dSMichal Kalderon #define QM_REG_PQOTHER2PF_10_RT_OFFSET 29499 30886aebde8dSMichal Kalderon #define QM_REG_PQOTHER2PF_11_RT_OFFSET 29500 30896aebde8dSMichal Kalderon #define QM_REG_PQOTHER2PF_12_RT_OFFSET 29501 30906aebde8dSMichal Kalderon #define QM_REG_PQOTHER2PF_13_RT_OFFSET 29502 30916aebde8dSMichal Kalderon #define QM_REG_PQOTHER2PF_14_RT_OFFSET 29503 30926aebde8dSMichal Kalderon #define QM_REG_PQOTHER2PF_15_RT_OFFSET 29504 30936aebde8dSMichal Kalderon #define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 29505 30946aebde8dSMichal Kalderon #define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 29506 30956aebde8dSMichal Kalderon #define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 29507 30966aebde8dSMichal Kalderon #define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 29508 30976aebde8dSMichal Kalderon #define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 29509 30986aebde8dSMichal Kalderon #define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 29510 30996aebde8dSMichal Kalderon #define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 29511 31006aebde8dSMichal Kalderon #define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 29512 31016aebde8dSMichal Kalderon #define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 29513 31026aebde8dSMichal Kalderon #define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 29514 31036aebde8dSMichal Kalderon #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 29515 31046aebde8dSMichal Kalderon #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 29516 31056aebde8dSMichal Kalderon #define QM_REG_RLGLBLINCVAL_RT_OFFSET 29517 3106fe56b9e6SYuval Mintz #define QM_REG_RLGLBLINCVAL_RT_SIZE 256 31076aebde8dSMichal Kalderon #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 29773 3108fe56b9e6SYuval Mintz #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256 31096aebde8dSMichal Kalderon #define QM_REG_RLGLBLCRD_RT_OFFSET 30029 3110fe56b9e6SYuval Mintz #define QM_REG_RLGLBLCRD_RT_SIZE 256 31116aebde8dSMichal Kalderon #define QM_REG_RLGLBLENABLE_RT_OFFSET 30285 31126aebde8dSMichal Kalderon #define QM_REG_RLPFPERIOD_RT_OFFSET 30286 31136aebde8dSMichal Kalderon #define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30287 31146aebde8dSMichal Kalderon #define QM_REG_RLPFINCVAL_RT_OFFSET 30288 3115fe56b9e6SYuval Mintz #define QM_REG_RLPFINCVAL_RT_SIZE 16 31166aebde8dSMichal Kalderon #define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30304 3117fe56b9e6SYuval Mintz #define QM_REG_RLPFUPPERBOUND_RT_SIZE 16 31186aebde8dSMichal Kalderon #define QM_REG_RLPFCRD_RT_OFFSET 30320 3119fe56b9e6SYuval Mintz #define QM_REG_RLPFCRD_RT_SIZE 16 31206aebde8dSMichal Kalderon #define QM_REG_RLPFENABLE_RT_OFFSET 30336 31216aebde8dSMichal Kalderon #define QM_REG_RLPFVOQENABLE_RT_OFFSET 30337 31226aebde8dSMichal Kalderon #define QM_REG_WFQPFWEIGHT_RT_OFFSET 30338 3123fe56b9e6SYuval Mintz #define QM_REG_WFQPFWEIGHT_RT_SIZE 16 31246aebde8dSMichal Kalderon #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30354 3125fe56b9e6SYuval Mintz #define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16 31266aebde8dSMichal Kalderon #define QM_REG_WFQPFCRD_RT_OFFSET 30370 31276aebde8dSMichal Kalderon #define QM_REG_WFQPFCRD_RT_SIZE 160 31286aebde8dSMichal Kalderon #define QM_REG_WFQPFENABLE_RT_OFFSET 30530 31296aebde8dSMichal Kalderon #define QM_REG_WFQVPENABLE_RT_OFFSET 30531 31306aebde8dSMichal Kalderon #define QM_REG_BASEADDRTXPQ_RT_OFFSET 30532 3131fe56b9e6SYuval Mintz #define QM_REG_BASEADDRTXPQ_RT_SIZE 512 31326aebde8dSMichal Kalderon #define QM_REG_TXPQMAP_RT_OFFSET 31044 3133fe56b9e6SYuval Mintz #define QM_REG_TXPQMAP_RT_SIZE 512 31346aebde8dSMichal Kalderon #define QM_REG_WFQVPWEIGHT_RT_OFFSET 31556 3135fe56b9e6SYuval Mintz #define QM_REG_WFQVPWEIGHT_RT_SIZE 512 3136fe40a830SPrabhakar Kushwaha #define QM_REG_WFQVPUPPERBOUND_RT_OFFSET 32068 3137fe40a830SPrabhakar Kushwaha #define QM_REG_WFQVPUPPERBOUND_RT_SIZE 512 3138fe40a830SPrabhakar Kushwaha #define QM_REG_WFQVPCRD_RT_OFFSET 32580 3139fe56b9e6SYuval Mintz #define QM_REG_WFQVPCRD_RT_SIZE 512 3140fe40a830SPrabhakar Kushwaha #define QM_REG_WFQVPMAP_RT_OFFSET 33092 3141fe56b9e6SYuval Mintz #define QM_REG_WFQVPMAP_RT_SIZE 512 3142fe40a830SPrabhakar Kushwaha #define QM_REG_PTRTBLTX_RT_OFFSET 33604 3143da090917STomer Tayar #define QM_REG_PTRTBLTX_RT_SIZE 1024 3144fe40a830SPrabhakar Kushwaha #define QM_REG_WFQPFCRD_MSB_RT_OFFSET 34628 31456aebde8dSMichal Kalderon #define QM_REG_WFQPFCRD_MSB_RT_SIZE 160 3146fe40a830SPrabhakar Kushwaha #define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 34788 3147fe40a830SPrabhakar Kushwaha #define NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET 34789 3148fe40a830SPrabhakar Kushwaha #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 34790 3149fe40a830SPrabhakar Kushwaha #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 34791 3150fe40a830SPrabhakar Kushwaha #define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 34792 3151fe40a830SPrabhakar Kushwaha #define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 34793 3152fe40a830SPrabhakar Kushwaha #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 34794 3153fe40a830SPrabhakar Kushwaha #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 34795 3154fe56b9e6SYuval Mintz #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4 3155fe40a830SPrabhakar Kushwaha #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 34799 3156fe56b9e6SYuval Mintz #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4 3157fe40a830SPrabhakar Kushwaha #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 34803 3158fe56b9e6SYuval Mintz #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32 3159fe40a830SPrabhakar Kushwaha #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 34835 3160fe56b9e6SYuval Mintz #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16 3161fe40a830SPrabhakar Kushwaha #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 34851 3162fe56b9e6SYuval Mintz #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16 3163fe40a830SPrabhakar Kushwaha #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 34867 3164fe56b9e6SYuval Mintz #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16 3165fe40a830SPrabhakar Kushwaha #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 34883 3166fe56b9e6SYuval Mintz #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16 3167fe40a830SPrabhakar Kushwaha #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 34899 3168fe40a830SPrabhakar Kushwaha #define NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET 34900 3169da090917STomer Tayar #define NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE 8 3170fe40a830SPrabhakar Kushwaha #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 34908 3171fe40a830SPrabhakar Kushwaha #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 34909 3172fe40a830SPrabhakar Kushwaha #define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 34910 3173fe40a830SPrabhakar Kushwaha #define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 34911 3174fe40a830SPrabhakar Kushwaha #define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 34912 3175fe40a830SPrabhakar Kushwaha #define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 34913 3176fe40a830SPrabhakar Kushwaha #define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 34914 3177fe40a830SPrabhakar Kushwaha #define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 34915 3178fe40a830SPrabhakar Kushwaha #define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 34916 3179fe40a830SPrabhakar Kushwaha #define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 34917 3180fe40a830SPrabhakar Kushwaha #define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 34918 3181fe40a830SPrabhakar Kushwaha #define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 34919 3182fe40a830SPrabhakar Kushwaha #define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 34920 3183fe40a830SPrabhakar Kushwaha #define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 34921 3184fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 34922 3185fe40a830SPrabhakar Kushwaha #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 34923 3186fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 34924 3187fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 34925 3188fe40a830SPrabhakar Kushwaha #define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 34926 3189fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 34927 3190fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 34928 3191fe40a830SPrabhakar Kushwaha #define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 34929 3192fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 34930 3193fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 34931 3194fe40a830SPrabhakar Kushwaha #define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 34932 3195fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 34933 3196fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 34934 3197fe40a830SPrabhakar Kushwaha #define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 34935 3198fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 34936 3199fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 34937 3200fe40a830SPrabhakar Kushwaha #define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 34938 3201fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 34939 3202fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 34940 3203fe40a830SPrabhakar Kushwaha #define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 34941 3204fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 34942 3205fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 34943 3206fe40a830SPrabhakar Kushwaha #define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 34944 3207fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 34945 3208fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 34946 3209fe40a830SPrabhakar Kushwaha #define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 34947 3210fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 34948 3211fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 34949 3212fe40a830SPrabhakar Kushwaha #define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 34950 3213fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 34951 3214fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 34952 3215fe40a830SPrabhakar Kushwaha #define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 34953 3216fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 34954 3217fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 34955 3218fe40a830SPrabhakar Kushwaha #define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 34956 3219fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 34957 3220fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 34958 3221fe40a830SPrabhakar Kushwaha #define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 34959 3222fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 34960 3223fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 34961 3224fe40a830SPrabhakar Kushwaha #define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 34962 3225fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 34963 3226fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 34964 3227fe40a830SPrabhakar Kushwaha #define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 34965 3228fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 34966 3229fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 34967 3230fe40a830SPrabhakar Kushwaha #define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 34968 3231fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 34969 3232fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 34970 3233fe40a830SPrabhakar Kushwaha #define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 34971 3234fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 34972 3235fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 34973 3236fe40a830SPrabhakar Kushwaha #define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 34974 3237fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 34975 3238fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 34976 3239fe40a830SPrabhakar Kushwaha #define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 34977 3240fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 34978 3241fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 34979 3242fe40a830SPrabhakar Kushwaha #define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 34980 3243fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 34981 3244fe40a830SPrabhakar Kushwaha #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 34982 3245fe40a830SPrabhakar Kushwaha #define XCM_REG_CON_PHY_Q3_RT_OFFSET 34983 3246fe56b9e6SYuval Mintz 3247fe40a830SPrabhakar Kushwaha #define RUNTIME_ARRAY_SIZE 34984 3248da090917STomer Tayar 3249da090917STomer Tayar /* Init Callbacks */ 3250da090917STomer Tayar #define DMAE_READY_CB 0 3251fe56b9e6SYuval Mintz 3252fc48b7a6SYuval Mintz /* The eth storm context for the Tstorm */ 3253fc48b7a6SYuval Mintz struct tstorm_eth_conn_st_ctx { 3254fe56b9e6SYuval Mintz __le32 reserved[4]; 3255fe56b9e6SYuval Mintz }; 3256fe56b9e6SYuval Mintz 3257fe56b9e6SYuval Mintz /* The eth storm context for the Pstorm */ 3258fe56b9e6SYuval Mintz struct pstorm_eth_conn_st_ctx { 3259fe56b9e6SYuval Mintz __le32 reserved[8]; 3260fe56b9e6SYuval Mintz }; 3261fe56b9e6SYuval Mintz 3262fe56b9e6SYuval Mintz /* The eth storm context for the Xstorm */ 3263fe56b9e6SYuval Mintz struct xstorm_eth_conn_st_ctx { 3264fe56b9e6SYuval Mintz __le32 reserved[60]; 3265fe56b9e6SYuval Mintz }; 3266fe56b9e6SYuval Mintz 3267fb09a1edSShai Malin struct xstorm_eth_conn_ag_ctx { 3268351a4dedSYuval Mintz u8 reserved0; 3269da090917STomer Tayar u8 state; 3270fe56b9e6SYuval Mintz u8 flags0; 3271fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 3272fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 3273fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1 3274fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1 3275fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1 3276fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2 3277fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 3278fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 3279fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1 3280fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4 3281fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1 3282fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5 3283fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1 3284fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6 3285fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1 3286fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7 3287fe56b9e6SYuval Mintz u8 flags1; 3288fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1 3289fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0 3290fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1 3291fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1 3292fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1 3293fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2 3294fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1 3295fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3 3296fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_MASK 0x1 3297fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_SHIFT 4 3298fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_MASK 0x1 3299fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_SHIFT 5 3300fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 3301fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 3302fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 3303fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 3304fe56b9e6SYuval Mintz u8 flags2; 3305fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 3306fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0 3307fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 3308fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2 3309fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 3310fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4 3311fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 3312fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6 3313fe56b9e6SYuval Mintz u8 flags3; 3314fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 3315fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0 3316fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 3317fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2 3318fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 3319fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4 3320fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 3321fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6 3322fe56b9e6SYuval Mintz u8 flags4; 3323fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 3324fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0 3325fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 3326fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2 3327fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 3328fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4 3329fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3 3330fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6 3331fe56b9e6SYuval Mintz u8 flags5; 3332fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3 3333fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0 3334fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3 3335fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2 3336fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3 3337fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4 3338fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3 3339fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6 3340fe56b9e6SYuval Mintz u8 flags6; 3341fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 3342fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 3343fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 3344fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 3345fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3 3346fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4 3347fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 3348fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 3349fe56b9e6SYuval Mintz u8 flags7; 3350fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 3351fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 3352fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3 3353fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2 3354fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3 3355fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4 3356fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 3357fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6 3358fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 3359fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7 3360fe56b9e6SYuval Mintz u8 flags8; 3361fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 3362fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0 3363fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 3364fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1 3365fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 3366fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2 3367fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 3368fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3 3369fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 3370fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4 3371fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 3372fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5 3373fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 3374fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6 3375fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 3376fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7 3377fe56b9e6SYuval Mintz u8 flags9; 3378fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 3379fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0 3380fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1 3381fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1 3382fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1 3383fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2 3384fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1 3385fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3 3386fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1 3387fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4 3388fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1 3389fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5 3390fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 3391fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 3392fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 3393fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 3394fe56b9e6SYuval Mintz u8 flags10; 3395fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 3396fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 3397fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 3398fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 3399fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 3400fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 3401fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1 3402fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3 3403fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 3404fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 3405fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 3406fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 3407fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1 3408fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6 3409fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1 3410fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7 3411fe56b9e6SYuval Mintz u8 flags11; 3412fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1 3413fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0 3414fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1 3415fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1 3416fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 3417fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 3418fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 3419fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3 3420fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 3421fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4 3422fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 3423fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5 3424fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 3425fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 3426fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1 3427fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7 3428fe56b9e6SYuval Mintz u8 flags12; 3429fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1 3430fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0 3431fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1 3432fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1 3433fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 3434fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 3435fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 3436fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 3437fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1 3438fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4 3439fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1 3440fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5 3441fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1 3442fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6 3443fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1 3444fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7 3445fe56b9e6SYuval Mintz u8 flags13; 3446fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1 3447fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0 3448fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1 3449fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1 3450fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 3451fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 3452fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 3453fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 3454fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 3455fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 3456fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 3457fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 3458fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 3459fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 3460fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 3461fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 3462fe56b9e6SYuval Mintz u8 flags14; 3463fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 3464fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 3465fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 3466fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 3467fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 3468fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 3469fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 3470fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 3471fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 3472fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 3473fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 3474fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 3475fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 3476fb09a1edSShai Malin #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 3477351a4dedSYuval Mintz u8 edpm_event_id; 3478351a4dedSYuval Mintz __le16 physical_q0; 347921dd79e8STomer Tayar __le16 e5_reserved1; 3480351a4dedSYuval Mintz __le16 edpm_num_bds; 3481351a4dedSYuval Mintz __le16 tx_bd_cons; 3482351a4dedSYuval Mintz __le16 tx_bd_prod; 348350bc60cbSMichal Kalderon __le16 updated_qm_pq_id; 3484351a4dedSYuval Mintz __le16 conn_dpi; 3485351a4dedSYuval Mintz u8 byte3; 3486351a4dedSYuval Mintz u8 byte4; 3487351a4dedSYuval Mintz u8 byte5; 3488351a4dedSYuval Mintz u8 byte6; 3489351a4dedSYuval Mintz __le32 reg0; 3490351a4dedSYuval Mintz __le32 reg1; 3491351a4dedSYuval Mintz __le32 reg2; 3492351a4dedSYuval Mintz __le32 reg3; 3493351a4dedSYuval Mintz __le32 reg4; 3494351a4dedSYuval Mintz __le32 reg5; 3495351a4dedSYuval Mintz __le32 reg6; 3496351a4dedSYuval Mintz __le16 word7; 3497351a4dedSYuval Mintz __le16 word8; 3498351a4dedSYuval Mintz __le16 word9; 3499351a4dedSYuval Mintz __le16 word10; 3500351a4dedSYuval Mintz __le32 reg7; 3501351a4dedSYuval Mintz __le32 reg8; 3502351a4dedSYuval Mintz __le32 reg9; 3503351a4dedSYuval Mintz u8 byte7; 3504351a4dedSYuval Mintz u8 byte8; 3505351a4dedSYuval Mintz u8 byte9; 3506351a4dedSYuval Mintz u8 byte10; 3507351a4dedSYuval Mintz u8 byte11; 3508351a4dedSYuval Mintz u8 byte12; 3509351a4dedSYuval Mintz u8 byte13; 3510351a4dedSYuval Mintz u8 byte14; 3511351a4dedSYuval Mintz u8 byte15; 351221dd79e8STomer Tayar u8 e5_reserved; 3513351a4dedSYuval Mintz __le16 word11; 3514351a4dedSYuval Mintz __le32 reg10; 3515351a4dedSYuval Mintz __le32 reg11; 3516351a4dedSYuval Mintz __le32 reg12; 3517351a4dedSYuval Mintz __le32 reg13; 3518351a4dedSYuval Mintz __le32 reg14; 3519351a4dedSYuval Mintz __le32 reg15; 3520351a4dedSYuval Mintz __le32 reg16; 3521351a4dedSYuval Mintz __le32 reg17; 3522351a4dedSYuval Mintz __le32 reg18; 3523351a4dedSYuval Mintz __le32 reg19; 3524351a4dedSYuval Mintz __le16 word12; 3525351a4dedSYuval Mintz __le16 word13; 3526351a4dedSYuval Mintz __le16 word14; 3527351a4dedSYuval Mintz __le16 word15; 3528fe56b9e6SYuval Mintz }; 3529fe56b9e6SYuval Mintz 3530fc48b7a6SYuval Mintz /* The eth storm context for the Ystorm */ 3531fc48b7a6SYuval Mintz struct ystorm_eth_conn_st_ctx { 3532fe56b9e6SYuval Mintz __le32 reserved[8]; 3533fe56b9e6SYuval Mintz }; 3534fe56b9e6SYuval Mintz 3535fb09a1edSShai Malin struct ystorm_eth_conn_ag_ctx { 3536351a4dedSYuval Mintz u8 byte0; 3537351a4dedSYuval Mintz u8 state; 3538fe56b9e6SYuval Mintz u8 flags0; 3539fb09a1edSShai Malin #define YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 3540fb09a1edSShai Malin #define YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 3541fb09a1edSShai Malin #define YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 3542fb09a1edSShai Malin #define YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 3543fb09a1edSShai Malin #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 3544fb09a1edSShai Malin #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2 3545fb09a1edSShai Malin #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3 3546fb09a1edSShai Malin #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4 3547fb09a1edSShai Malin #define YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 3548fb09a1edSShai Malin #define YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 3549fe56b9e6SYuval Mintz u8 flags1; 3550fb09a1edSShai Malin #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 3551fb09a1edSShai Malin #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0 3552fb09a1edSShai Malin #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1 3553fb09a1edSShai Malin #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1 3554fb09a1edSShai Malin #define YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 3555fb09a1edSShai Malin #define YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 3556fb09a1edSShai Malin #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 3557fb09a1edSShai Malin #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 3558fb09a1edSShai Malin #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 3559fb09a1edSShai Malin #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 3560fb09a1edSShai Malin #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 3561fb09a1edSShai Malin #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 3562fb09a1edSShai Malin #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 3563fb09a1edSShai Malin #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 3564fb09a1edSShai Malin #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 3565fb09a1edSShai Malin #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 3566351a4dedSYuval Mintz u8 tx_q0_int_coallecing_timeset; 3567351a4dedSYuval Mintz u8 byte3; 3568351a4dedSYuval Mintz __le16 word0; 3569351a4dedSYuval Mintz __le32 terminate_spqe; 3570351a4dedSYuval Mintz __le32 reg1; 3571351a4dedSYuval Mintz __le16 tx_bd_cons_upd; 3572351a4dedSYuval Mintz __le16 word2; 3573351a4dedSYuval Mintz __le16 word3; 3574351a4dedSYuval Mintz __le16 word4; 3575351a4dedSYuval Mintz __le32 reg2; 3576351a4dedSYuval Mintz __le32 reg3; 3577fe56b9e6SYuval Mintz }; 3578fe56b9e6SYuval Mintz 3579fb09a1edSShai Malin struct tstorm_eth_conn_ag_ctx { 3580351a4dedSYuval Mintz u8 byte0; 3581351a4dedSYuval Mintz u8 byte1; 3582fe56b9e6SYuval Mintz u8 flags0; 3583fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 3584fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 3585fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 3586fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 3587fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1 3588fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2 3589fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1 3590fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3 3591fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1 3592fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4 3593fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1 3594fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5 3595fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 3596fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6 3597fe56b9e6SYuval Mintz u8 flags1; 3598fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 3599fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0 3600fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 3601fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2 3602fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 3603fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4 3604fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 3605fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6 3606fe56b9e6SYuval Mintz u8 flags2; 3607fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 3608fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0 3609fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 3610fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2 3611fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 3612fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4 3613fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 3614fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6 3615fe56b9e6SYuval Mintz u8 flags3; 3616fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 3617fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0 3618fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 3619fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2 3620fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 3621fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4 3622fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 3623fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5 3624fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 3625fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6 3626fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 3627fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7 3628fe56b9e6SYuval Mintz u8 flags4; 3629fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 3630fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0 3631fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 3632fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1 3633fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 3634fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2 3635fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 3636fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3 3637fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 3638fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4 3639fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 3640fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5 3641fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 3642fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6 3643fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 3644fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 3645fe56b9e6SYuval Mintz u8 flags5; 3646fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 3647fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 3648fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 3649fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 3650fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 3651fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 3652fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 3653fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 3654fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 3655fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 3656fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1 3657fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5 3658fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 3659fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 3660fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 3661fb09a1edSShai Malin #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 3662351a4dedSYuval Mintz __le32 reg0; 3663351a4dedSYuval Mintz __le32 reg1; 3664351a4dedSYuval Mintz __le32 reg2; 3665351a4dedSYuval Mintz __le32 reg3; 3666351a4dedSYuval Mintz __le32 reg4; 3667351a4dedSYuval Mintz __le32 reg5; 3668351a4dedSYuval Mintz __le32 reg6; 3669351a4dedSYuval Mintz __le32 reg7; 3670351a4dedSYuval Mintz __le32 reg8; 3671351a4dedSYuval Mintz u8 byte2; 3672351a4dedSYuval Mintz u8 byte3; 3673351a4dedSYuval Mintz __le16 rx_bd_cons; 3674351a4dedSYuval Mintz u8 byte4; 3675351a4dedSYuval Mintz u8 byte5; 3676351a4dedSYuval Mintz __le16 rx_bd_prod; 3677351a4dedSYuval Mintz __le16 word2; 3678351a4dedSYuval Mintz __le16 word3; 3679351a4dedSYuval Mintz __le32 reg9; 3680351a4dedSYuval Mintz __le32 reg10; 3681fe56b9e6SYuval Mintz }; 3682fe56b9e6SYuval Mintz 3683fb09a1edSShai Malin struct ustorm_eth_conn_ag_ctx { 3684351a4dedSYuval Mintz u8 byte0; 3685351a4dedSYuval Mintz u8 byte1; 3686fe56b9e6SYuval Mintz u8 flags0; 3687fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 3688fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 3689fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 3690fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 3691fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3 3692fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2 3693fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3 3694fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4 3695fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 3696fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 3697fe56b9e6SYuval Mintz u8 flags1; 3698fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 3699fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0 3700fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3 3701fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2 3702fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3 3703fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4 3704fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 3705fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6 3706fe56b9e6SYuval Mintz u8 flags2; 3707fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1 3708fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0 3709fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1 3710fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1 3711fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 3712fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 3713fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 3714fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3 3715fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1 3716fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4 3717fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1 3718fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5 3719fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 3720fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6 3721fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 3722fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 3723fe56b9e6SYuval Mintz u8 flags3; 3724fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 3725fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 3726fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 3727fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 3728fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 3729fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 3730fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 3731fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 3732fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 3733fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 3734fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 3735fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5 3736fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 3737fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 3738fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 3739fb09a1edSShai Malin #define USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 3740351a4dedSYuval Mintz u8 byte2; 3741351a4dedSYuval Mintz u8 byte3; 3742351a4dedSYuval Mintz __le16 word0; 3743351a4dedSYuval Mintz __le16 tx_bd_cons; 3744351a4dedSYuval Mintz __le32 reg0; 3745351a4dedSYuval Mintz __le32 reg1; 3746351a4dedSYuval Mintz __le32 reg2; 3747351a4dedSYuval Mintz __le32 tx_int_coallecing_timeset; 3748351a4dedSYuval Mintz __le16 tx_drv_bd_cons; 3749351a4dedSYuval Mintz __le16 rx_drv_cqe_cons; 3750fe56b9e6SYuval Mintz }; 3751fe56b9e6SYuval Mintz 3752fc48b7a6SYuval Mintz /* The eth storm context for the Ustorm */ 3753fc48b7a6SYuval Mintz struct ustorm_eth_conn_st_ctx { 3754fc48b7a6SYuval Mintz __le32 reserved[40]; 3755fc48b7a6SYuval Mintz }; 3756fc48b7a6SYuval Mintz 3757fc48b7a6SYuval Mintz /* The eth storm context for the Mstorm */ 3758fc48b7a6SYuval Mintz struct mstorm_eth_conn_st_ctx { 3759fc48b7a6SYuval Mintz __le32 reserved[8]; 3760fc48b7a6SYuval Mintz }; 3761fc48b7a6SYuval Mintz 3762fc48b7a6SYuval Mintz /* eth connection context */ 3763fb09a1edSShai Malin struct eth_conn_context { 3764fc48b7a6SYuval Mintz struct tstorm_eth_conn_st_ctx tstorm_st_context; 3765fc48b7a6SYuval Mintz struct regpair tstorm_st_padding[2]; 3766fc48b7a6SYuval Mintz struct pstorm_eth_conn_st_ctx pstorm_st_context; 3767fc48b7a6SYuval Mintz struct xstorm_eth_conn_st_ctx xstorm_st_context; 3768fb09a1edSShai Malin struct xstorm_eth_conn_ag_ctx xstorm_ag_context; 3769fb09a1edSShai Malin struct tstorm_eth_conn_ag_ctx tstorm_ag_context; 3770fc48b7a6SYuval Mintz struct ystorm_eth_conn_st_ctx ystorm_st_context; 3771fb09a1edSShai Malin struct ystorm_eth_conn_ag_ctx ystorm_ag_context; 3772fb09a1edSShai Malin struct ustorm_eth_conn_ag_ctx ustorm_ag_context; 3773fc48b7a6SYuval Mintz struct ustorm_eth_conn_st_ctx ustorm_st_context; 3774fc48b7a6SYuval Mintz struct mstorm_eth_conn_st_ctx mstorm_st_context; 3775fc48b7a6SYuval Mintz }; 3776fc48b7a6SYuval Mintz 3777a2e7699eSTomer Tayar /* Ethernet filter types: mac/vlan/pair */ 377805fafbfbSYuval Mintz enum eth_error_code { 377905fafbfbSYuval Mintz ETH_OK = 0x00, 378005fafbfbSYuval Mintz ETH_FILTERS_MAC_ADD_FAIL_FULL, 378105fafbfbSYuval Mintz ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2, 378205fafbfbSYuval Mintz ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2, 378305fafbfbSYuval Mintz ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2, 378405fafbfbSYuval Mintz ETH_FILTERS_MAC_DEL_FAIL_NOF, 378505fafbfbSYuval Mintz ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2, 378605fafbfbSYuval Mintz ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2, 378705fafbfbSYuval Mintz ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC, 378805fafbfbSYuval Mintz ETH_FILTERS_VLAN_ADD_FAIL_FULL, 378905fafbfbSYuval Mintz ETH_FILTERS_VLAN_ADD_FAIL_DUP, 379005fafbfbSYuval Mintz ETH_FILTERS_VLAN_DEL_FAIL_NOF, 379105fafbfbSYuval Mintz ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1, 379205fafbfbSYuval Mintz ETH_FILTERS_PAIR_ADD_FAIL_DUP, 379305fafbfbSYuval Mintz ETH_FILTERS_PAIR_ADD_FAIL_FULL, 379405fafbfbSYuval Mintz ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC, 379505fafbfbSYuval Mintz ETH_FILTERS_PAIR_DEL_FAIL_NOF, 379605fafbfbSYuval Mintz ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1, 379705fafbfbSYuval Mintz ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC, 379805fafbfbSYuval Mintz ETH_FILTERS_VNI_ADD_FAIL_FULL, 379905fafbfbSYuval Mintz ETH_FILTERS_VNI_ADD_FAIL_DUP, 38007b6859fbSMintz, Yuval ETH_FILTERS_GFT_UPDATE_FAIL, 38010500a70dSMichal Kalderon ETH_RX_QUEUE_FAIL_LOAD_VF_DATA, 38020500a70dSMichal Kalderon ETH_FILTERS_GFS_ADD_FILTER_FAIL_MAX_HOPS, 38030500a70dSMichal Kalderon ETH_FILTERS_GFS_ADD_FILTER_FAIL_NO_FREE_ENRTY, 38040500a70dSMichal Kalderon ETH_FILTERS_GFS_ADD_FILTER_FAIL_ALREADY_EXISTS, 38050500a70dSMichal Kalderon ETH_FILTERS_GFS_ADD_FILTER_FAIL_PCI_ERROR, 38060500a70dSMichal Kalderon ETH_FILTERS_GFS_ADD_FINLER_FAIL_MAGIC_NUM_ERROR, 38070500a70dSMichal Kalderon ETH_FILTERS_GFS_DEL_FILTER_FAIL_MAX_HOPS, 38080500a70dSMichal Kalderon ETH_FILTERS_GFS_DEL_FILTER_FAIL_NO_MATCH_ENRTY, 38090500a70dSMichal Kalderon ETH_FILTERS_GFS_DEL_FILTER_FAIL_PCI_ERROR, 38100500a70dSMichal Kalderon ETH_FILTERS_GFS_DEL_FILTER_FAIL_MAGIC_NUM_ERROR, 381105fafbfbSYuval Mintz MAX_ETH_ERROR_CODE 381205fafbfbSYuval Mintz }; 381305fafbfbSYuval Mintz 3814a2e7699eSTomer Tayar /* Opcodes for the event ring */ 3815351a4dedSYuval Mintz enum eth_event_opcode { 3816351a4dedSYuval Mintz ETH_EVENT_UNUSED, 3817351a4dedSYuval Mintz ETH_EVENT_VPORT_START, 3818351a4dedSYuval Mintz ETH_EVENT_VPORT_UPDATE, 3819351a4dedSYuval Mintz ETH_EVENT_VPORT_STOP, 3820351a4dedSYuval Mintz ETH_EVENT_TX_QUEUE_START, 3821351a4dedSYuval Mintz ETH_EVENT_TX_QUEUE_STOP, 3822351a4dedSYuval Mintz ETH_EVENT_RX_QUEUE_START, 3823351a4dedSYuval Mintz ETH_EVENT_RX_QUEUE_UPDATE, 3824351a4dedSYuval Mintz ETH_EVENT_RX_QUEUE_STOP, 3825351a4dedSYuval Mintz ETH_EVENT_FILTERS_UPDATE, 3826da090917STomer Tayar ETH_EVENT_RX_ADD_OPENFLOW_FILTER, 3827da090917STomer Tayar ETH_EVENT_RX_DELETE_OPENFLOW_FILTER, 3828da090917STomer Tayar ETH_EVENT_RX_CREATE_OPENFLOW_ACTION, 3829351a4dedSYuval Mintz ETH_EVENT_RX_ADD_UDP_FILTER, 3830351a4dedSYuval Mintz ETH_EVENT_RX_DELETE_UDP_FILTER, 3831da090917STomer Tayar ETH_EVENT_RX_CREATE_GFT_ACTION, 3832da090917STomer Tayar ETH_EVENT_RX_GFT_UPDATE_FILTER, 3833da090917STomer Tayar ETH_EVENT_TX_QUEUE_UPDATE, 38340500a70dSMichal Kalderon ETH_EVENT_RGFS_ADD_FILTER, 38350500a70dSMichal Kalderon ETH_EVENT_RGFS_DEL_FILTER, 38360500a70dSMichal Kalderon ETH_EVENT_TGFS_ADD_FILTER, 38370500a70dSMichal Kalderon ETH_EVENT_TGFS_DEL_FILTER, 38380500a70dSMichal Kalderon ETH_EVENT_GFS_COUNTERS_REPORT_REQUEST, 3839351a4dedSYuval Mintz MAX_ETH_EVENT_OPCODE 3840351a4dedSYuval Mintz }; 3841351a4dedSYuval Mintz 3842351a4dedSYuval Mintz /* Classify rule types in E2/E3 */ 3843fc48b7a6SYuval Mintz enum eth_filter_action { 3844351a4dedSYuval Mintz ETH_FILTER_ACTION_UNUSED, 3845fc48b7a6SYuval Mintz ETH_FILTER_ACTION_REMOVE, 3846fc48b7a6SYuval Mintz ETH_FILTER_ACTION_ADD, 3847fc48b7a6SYuval Mintz ETH_FILTER_ACTION_REMOVE_ALL, 3848fc48b7a6SYuval Mintz MAX_ETH_FILTER_ACTION 3849fc48b7a6SYuval Mintz }; 3850fc48b7a6SYuval Mintz 3851351a4dedSYuval Mintz /* Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$ */ 3852fc48b7a6SYuval Mintz struct eth_filter_cmd { 3853351a4dedSYuval Mintz u8 type; 3854351a4dedSYuval Mintz u8 vport_id; 3855351a4dedSYuval Mintz u8 action; 3856fc48b7a6SYuval Mintz u8 reserved0; 3857fc48b7a6SYuval Mintz __le32 vni; 3858fc48b7a6SYuval Mintz __le16 mac_lsb; 3859fc48b7a6SYuval Mintz __le16 mac_mid; 3860fc48b7a6SYuval Mintz __le16 mac_msb; 3861fc48b7a6SYuval Mintz __le16 vlan_id; 3862fc48b7a6SYuval Mintz }; 3863fc48b7a6SYuval Mintz 3864351a4dedSYuval Mintz /* $$KEEP_ENDIANNESS$$ */ 3865fc48b7a6SYuval Mintz struct eth_filter_cmd_header { 3866fc48b7a6SYuval Mintz u8 rx; 3867fc48b7a6SYuval Mintz u8 tx; 3868fc48b7a6SYuval Mintz u8 cmd_cnt; 3869fc48b7a6SYuval Mintz u8 assert_on_error; 3870fc48b7a6SYuval Mintz u8 reserved1[4]; 3871fc48b7a6SYuval Mintz }; 3872fc48b7a6SYuval Mintz 3873351a4dedSYuval Mintz /* Ethernet filter types: mac/vlan/pair */ 3874fc48b7a6SYuval Mintz enum eth_filter_type { 3875351a4dedSYuval Mintz ETH_FILTER_TYPE_UNUSED, 3876fc48b7a6SYuval Mintz ETH_FILTER_TYPE_MAC, 3877fc48b7a6SYuval Mintz ETH_FILTER_TYPE_VLAN, 3878fc48b7a6SYuval Mintz ETH_FILTER_TYPE_PAIR, 3879fc48b7a6SYuval Mintz ETH_FILTER_TYPE_INNER_MAC, 3880fc48b7a6SYuval Mintz ETH_FILTER_TYPE_INNER_VLAN, 3881fc48b7a6SYuval Mintz ETH_FILTER_TYPE_INNER_PAIR, 3882fc48b7a6SYuval Mintz ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR, 3883fc48b7a6SYuval Mintz ETH_FILTER_TYPE_MAC_VNI_PAIR, 3884fc48b7a6SYuval Mintz ETH_FILTER_TYPE_VNI, 3885fc48b7a6SYuval Mintz MAX_ETH_FILTER_TYPE 3886fc48b7a6SYuval Mintz }; 3887fc48b7a6SYuval Mintz 3888a3f72307SDenis Bolotin /* inner to inner vlan priority translation configurations */ 3889a3f72307SDenis Bolotin struct eth_in_to_in_pri_map_cfg { 3890a3f72307SDenis Bolotin u8 inner_vlan_pri_remap_en; 3891a3f72307SDenis Bolotin u8 reserved[7]; 3892a3f72307SDenis Bolotin u8 non_rdma_in_to_in_pri_map[8]; 3893a3f72307SDenis Bolotin u8 rdma_in_to_in_pri_map[8]; 3894a3f72307SDenis Bolotin }; 3895a3f72307SDenis Bolotin 3896a2e7699eSTomer Tayar /* Eth IPv4 Fragment Type */ 389705fafbfbSYuval Mintz enum eth_ipv4_frag_type { 389805fafbfbSYuval Mintz ETH_IPV4_NOT_FRAG, 389905fafbfbSYuval Mintz ETH_IPV4_FIRST_FRAG, 390005fafbfbSYuval Mintz ETH_IPV4_NON_FIRST_FRAG, 390105fafbfbSYuval Mintz MAX_ETH_IPV4_FRAG_TYPE 390205fafbfbSYuval Mintz }; 390305fafbfbSYuval Mintz 3904a2e7699eSTomer Tayar /* eth IPv4 Fragment Type */ 3905be086e7cSMintz, Yuval enum eth_ip_type { 3906be086e7cSMintz, Yuval ETH_IPV4, 3907be086e7cSMintz, Yuval ETH_IPV6, 3908be086e7cSMintz, Yuval MAX_ETH_IP_TYPE 3909be086e7cSMintz, Yuval }; 3910be086e7cSMintz, Yuval 3911a2e7699eSTomer Tayar /* Ethernet Ramrod Command IDs */ 3912fc48b7a6SYuval Mintz enum eth_ramrod_cmd_id { 3913fc48b7a6SYuval Mintz ETH_RAMROD_UNUSED, 3914351a4dedSYuval Mintz ETH_RAMROD_VPORT_START, 3915351a4dedSYuval Mintz ETH_RAMROD_VPORT_UPDATE, 3916351a4dedSYuval Mintz ETH_RAMROD_VPORT_STOP, 3917351a4dedSYuval Mintz ETH_RAMROD_RX_QUEUE_START, 3918351a4dedSYuval Mintz ETH_RAMROD_RX_QUEUE_STOP, 3919351a4dedSYuval Mintz ETH_RAMROD_TX_QUEUE_START, 3920351a4dedSYuval Mintz ETH_RAMROD_TX_QUEUE_STOP, 3921351a4dedSYuval Mintz ETH_RAMROD_FILTERS_UPDATE, 3922351a4dedSYuval Mintz ETH_RAMROD_RX_QUEUE_UPDATE, 3923351a4dedSYuval Mintz ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION, 3924351a4dedSYuval Mintz ETH_RAMROD_RX_ADD_OPENFLOW_FILTER, 3925351a4dedSYuval Mintz ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER, 3926351a4dedSYuval Mintz ETH_RAMROD_RX_ADD_UDP_FILTER, 3927351a4dedSYuval Mintz ETH_RAMROD_RX_DELETE_UDP_FILTER, 3928351a4dedSYuval Mintz ETH_RAMROD_RX_CREATE_GFT_ACTION, 3929fe40a830SPrabhakar Kushwaha ETH_RAMROD_RX_UPDATE_GFT_FILTER, 3930da090917STomer Tayar ETH_RAMROD_TX_QUEUE_UPDATE, 39310500a70dSMichal Kalderon ETH_RAMROD_RGFS_FILTER_ADD, 39320500a70dSMichal Kalderon ETH_RAMROD_RGFS_FILTER_DEL, 39330500a70dSMichal Kalderon ETH_RAMROD_TGFS_FILTER_ADD, 39340500a70dSMichal Kalderon ETH_RAMROD_TGFS_FILTER_DEL, 39350500a70dSMichal Kalderon ETH_RAMROD_GFS_COUNTERS_REPORT_REQUEST, 3936fc48b7a6SYuval Mintz MAX_ETH_RAMROD_CMD_ID 3937fc48b7a6SYuval Mintz }; 3938fc48b7a6SYuval Mintz 3939a2e7699eSTomer Tayar /* Return code from eth sp ramrods */ 3940351a4dedSYuval Mintz struct eth_return_code { 3941351a4dedSYuval Mintz u8 value; 39420500a70dSMichal Kalderon #define ETH_RETURN_CODE_ERR_CODE_MASK 0x3F 3943351a4dedSYuval Mintz #define ETH_RETURN_CODE_ERR_CODE_SHIFT 0 39440500a70dSMichal Kalderon #define ETH_RETURN_CODE_RESERVED_MASK 0x1 39450500a70dSMichal Kalderon #define ETH_RETURN_CODE_RESERVED_SHIFT 6 3946351a4dedSYuval Mintz #define ETH_RETURN_CODE_RX_TX_MASK 0x1 3947351a4dedSYuval Mintz #define ETH_RETURN_CODE_RX_TX_SHIFT 7 3948351a4dedSYuval Mintz }; 3949351a4dedSYuval Mintz 39500500a70dSMichal Kalderon /* tx destination enum */ 39510500a70dSMichal Kalderon enum eth_tx_dst_mode_config_enum { 39520500a70dSMichal Kalderon ETH_TX_DST_MODE_CONFIG_DISABLE, 39530500a70dSMichal Kalderon ETH_TX_DST_MODE_CONFIG_FORWARD_DATA_IN_BD, 39540500a70dSMichal Kalderon ETH_TX_DST_MODE_CONFIG_FORWARD_DATA_IN_VPORT, 39550500a70dSMichal Kalderon MAX_ETH_TX_DST_MODE_CONFIG_ENUM 39560500a70dSMichal Kalderon }; 39570500a70dSMichal Kalderon 3958351a4dedSYuval Mintz /* What to do in case an error occurs */ 3959fc48b7a6SYuval Mintz enum eth_tx_err { 3960351a4dedSYuval Mintz ETH_TX_ERR_DROP, 3961fc48b7a6SYuval Mintz ETH_TX_ERR_ASSERT_MALICIOUS, 3962fc48b7a6SYuval Mintz MAX_ETH_TX_ERR 3963fc48b7a6SYuval Mintz }; 3964fc48b7a6SYuval Mintz 3965351a4dedSYuval Mintz /* Array of the different error type behaviors */ 3966fc48b7a6SYuval Mintz struct eth_tx_err_vals { 3967fc48b7a6SYuval Mintz __le16 values; 3968fc48b7a6SYuval Mintz #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1 3969fc48b7a6SYuval Mintz #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0 3970fc48b7a6SYuval Mintz #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1 3971fc48b7a6SYuval Mintz #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT 1 3972fc48b7a6SYuval Mintz #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1 3973fc48b7a6SYuval Mintz #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT 2 3974fc48b7a6SYuval Mintz #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1 3975fc48b7a6SYuval Mintz #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT 3 3976fc48b7a6SYuval Mintz #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1 3977fc48b7a6SYuval Mintz #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4 3978fc48b7a6SYuval Mintz #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1 3979fc48b7a6SYuval Mintz #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5 3980fc48b7a6SYuval Mintz #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1 3981fc48b7a6SYuval Mintz #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6 39820500a70dSMichal Kalderon #define ETH_TX_ERR_VALS_ILLEGAL_BD_FLAGS_MASK 0x1 39830500a70dSMichal Kalderon #define ETH_TX_ERR_VALS_ILLEGAL_BD_FLAGS_SHIFT 7 39840500a70dSMichal Kalderon #define ETH_TX_ERR_VALS_RESERVED_MASK 0xFF 39850500a70dSMichal Kalderon #define ETH_TX_ERR_VALS_RESERVED_SHIFT 8 3986fc48b7a6SYuval Mintz }; 3987fc48b7a6SYuval Mintz 3988351a4dedSYuval Mintz /* vport rss configuration data */ 3989fc48b7a6SYuval Mintz struct eth_vport_rss_config { 3990fc48b7a6SYuval Mintz __le16 capabilities; 3991fc48b7a6SYuval Mintz #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1 3992fc48b7a6SYuval Mintz #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0 3993fc48b7a6SYuval Mintz #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1 3994fc48b7a6SYuval Mintz #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1 3995fc48b7a6SYuval Mintz #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1 3996fc48b7a6SYuval Mintz #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2 3997fc48b7a6SYuval Mintz #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1 3998fc48b7a6SYuval Mintz #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3 3999fc48b7a6SYuval Mintz #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1 4000fc48b7a6SYuval Mintz #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4 4001fc48b7a6SYuval Mintz #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1 4002fc48b7a6SYuval Mintz #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5 4003fc48b7a6SYuval Mintz #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1 4004fc48b7a6SYuval Mintz #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6 4005fc48b7a6SYuval Mintz #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF 4006fc48b7a6SYuval Mintz #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 7 4007fc48b7a6SYuval Mintz u8 rss_id; 4008fc48b7a6SYuval Mintz u8 rss_mode; 4009fc48b7a6SYuval Mintz u8 update_rss_key; 4010fc48b7a6SYuval Mintz u8 update_rss_ind_table; 4011fc48b7a6SYuval Mintz u8 update_rss_capabilities; 4012fc48b7a6SYuval Mintz u8 tbl_size; 4013fe40a830SPrabhakar Kushwaha u8 ind_table_mask_valid; 4014fe40a830SPrabhakar Kushwaha u8 reserved2[3]; 4015fc48b7a6SYuval Mintz __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM]; 4016fe40a830SPrabhakar Kushwaha __le32 ind_table_mask[ETH_RSS_IND_TABLE_MASK_SIZE_REGS]; 4017fc48b7a6SYuval Mintz __le32 rss_key[ETH_RSS_KEY_SIZE_REGS]; 4018fe40a830SPrabhakar Kushwaha __le32 reserved3; 4019fc48b7a6SYuval Mintz }; 4020fc48b7a6SYuval Mintz 4021351a4dedSYuval Mintz /* eth vport RSS mode */ 4022fc48b7a6SYuval Mintz enum eth_vport_rss_mode { 4023fc48b7a6SYuval Mintz ETH_VPORT_RSS_MODE_DISABLED, 4024fc48b7a6SYuval Mintz ETH_VPORT_RSS_MODE_REGULAR, 4025fc48b7a6SYuval Mintz MAX_ETH_VPORT_RSS_MODE 4026fc48b7a6SYuval Mintz }; 4027fc48b7a6SYuval Mintz 4028351a4dedSYuval Mintz /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */ 4029fc48b7a6SYuval Mintz struct eth_vport_rx_mode { 4030fc48b7a6SYuval Mintz __le16 state; 4031fc48b7a6SYuval Mintz #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1 4032fc48b7a6SYuval Mintz #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0 4033fc48b7a6SYuval Mintz #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1 4034fc48b7a6SYuval Mintz #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1 4035fc48b7a6SYuval Mintz #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1 4036fc48b7a6SYuval Mintz #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2 4037fc48b7a6SYuval Mintz #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1 4038fc48b7a6SYuval Mintz #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3 4039fc48b7a6SYuval Mintz #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1 4040fc48b7a6SYuval Mintz #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4 4041fc48b7a6SYuval Mintz #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1 4042fc48b7a6SYuval Mintz #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5 4043d52c89f1SMichal Kalderon #define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_MASK 0x1 4044d52c89f1SMichal Kalderon #define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_SHIFT 6 4045d52c89f1SMichal Kalderon #define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x1FF 4046d52c89f1SMichal Kalderon #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 7 4047fc48b7a6SYuval Mintz }; 4048fc48b7a6SYuval Mintz 4049351a4dedSYuval Mintz /* Command for setting tpa parameters */ 4050fc48b7a6SYuval Mintz struct eth_vport_tpa_param { 4051088c8618SManish Chopra u8 tpa_ipv4_en_flg; 4052088c8618SManish Chopra u8 tpa_ipv6_en_flg; 4053088c8618SManish Chopra u8 tpa_ipv4_tunn_en_flg; 4054088c8618SManish Chopra u8 tpa_ipv6_tunn_en_flg; 4055088c8618SManish Chopra u8 tpa_pkt_split_flg; 4056088c8618SManish Chopra u8 tpa_hdr_data_split_flg; 4057088c8618SManish Chopra u8 tpa_gro_consistent_flg; 4058351a4dedSYuval Mintz 4059088c8618SManish Chopra u8 tpa_max_aggs_num; 4060351a4dedSYuval Mintz 4061351a4dedSYuval Mintz __le16 tpa_max_size; 4062351a4dedSYuval Mintz __le16 tpa_min_size_to_start; 4063351a4dedSYuval Mintz 4064351a4dedSYuval Mintz __le16 tpa_min_size_to_cont; 4065088c8618SManish Chopra u8 max_buff_num; 4066088c8618SManish Chopra u8 reserved; 4067fc48b7a6SYuval Mintz }; 4068fc48b7a6SYuval Mintz 4069351a4dedSYuval Mintz /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */ 4070fc48b7a6SYuval Mintz struct eth_vport_tx_mode { 4071fc48b7a6SYuval Mintz __le16 state; 4072fc48b7a6SYuval Mintz #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1 4073fc48b7a6SYuval Mintz #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0 4074fc48b7a6SYuval Mintz #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1 4075fc48b7a6SYuval Mintz #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1 4076fc48b7a6SYuval Mintz #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1 4077fc48b7a6SYuval Mintz #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2 4078fc48b7a6SYuval Mintz #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1 4079fc48b7a6SYuval Mintz #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3 4080fc48b7a6SYuval Mintz #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1 4081fc48b7a6SYuval Mintz #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4 4082fc48b7a6SYuval Mintz #define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF 4083fc48b7a6SYuval Mintz #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5 4084fc48b7a6SYuval Mintz }; 4085fc48b7a6SYuval Mintz 4086a2e7699eSTomer Tayar /* GFT filter update action type */ 4087d51e4af5SChopra, Manish enum gft_filter_update_action { 4088d51e4af5SChopra, Manish GFT_ADD_FILTER, 4089d51e4af5SChopra, Manish GFT_DELETE_FILTER, 4090d51e4af5SChopra, Manish MAX_GFT_FILTER_UPDATE_ACTION 4091d51e4af5SChopra, Manish }; 4092d51e4af5SChopra, Manish 4093fe40a830SPrabhakar Kushwaha /* Ramrod data for rx create gft action */ 4094fe40a830SPrabhakar Kushwaha struct rx_create_gft_action_ramrod_data { 4095fe40a830SPrabhakar Kushwaha u8 vport_id; 4096fe40a830SPrabhakar Kushwaha u8 reserved[7]; 4097fe40a830SPrabhakar Kushwaha }; 4098fe40a830SPrabhakar Kushwaha 4099fe40a830SPrabhakar Kushwaha /* Ramrod data for rx create openflow action */ 4100fe40a830SPrabhakar Kushwaha struct rx_create_openflow_action_ramrod_data { 4101fe40a830SPrabhakar Kushwaha u8 vport_id; 4102fe40a830SPrabhakar Kushwaha u8 reserved[7]; 4103fe40a830SPrabhakar Kushwaha }; 4104fe40a830SPrabhakar Kushwaha 4105a2e7699eSTomer Tayar /* Ramrod data for rx add openflow filter */ 4106fe40a830SPrabhakar Kushwaha struct rx_openflow_filter_ramrod_data { 41077b6859fbSMintz, Yuval __le16 action_icid; 41087b6859fbSMintz, Yuval u8 priority; 41097b6859fbSMintz, Yuval u8 reserved0; 41107b6859fbSMintz, Yuval __le32 tenant_id; 41117b6859fbSMintz, Yuval __le16 dst_mac_hi; 41127b6859fbSMintz, Yuval __le16 dst_mac_mid; 41137b6859fbSMintz, Yuval __le16 dst_mac_lo; 41147b6859fbSMintz, Yuval __le16 src_mac_hi; 41157b6859fbSMintz, Yuval __le16 src_mac_mid; 41167b6859fbSMintz, Yuval __le16 src_mac_lo; 41177b6859fbSMintz, Yuval __le16 vlan_id; 41187b6859fbSMintz, Yuval __le16 l2_eth_type; 41197b6859fbSMintz, Yuval u8 ipv4_dscp; 41207b6859fbSMintz, Yuval u8 ipv4_frag_type; 41217b6859fbSMintz, Yuval u8 ipv4_over_ip; 41227b6859fbSMintz, Yuval u8 tenant_id_exists; 41237b6859fbSMintz, Yuval __le32 ipv4_dst_addr; 41247b6859fbSMintz, Yuval __le32 ipv4_src_addr; 41257b6859fbSMintz, Yuval __le16 l4_dst_port; 41267b6859fbSMintz, Yuval __le16 l4_src_port; 41277b6859fbSMintz, Yuval }; 41287b6859fbSMintz, Yuval 4129351a4dedSYuval Mintz /* Ramrod data for rx queue start ramrod */ 4130fc48b7a6SYuval Mintz struct rx_queue_start_ramrod_data { 4131fc48b7a6SYuval Mintz __le16 rx_queue_id; 4132fc48b7a6SYuval Mintz __le16 num_of_pbl_pages; 4133fc48b7a6SYuval Mintz __le16 bd_max_bytes; 4134fc48b7a6SYuval Mintz __le16 sb_id; 4135fc48b7a6SYuval Mintz u8 sb_index; 4136fc48b7a6SYuval Mintz u8 vport_id; 4137fc48b7a6SYuval Mintz u8 default_rss_queue_flg; 4138fc48b7a6SYuval Mintz u8 complete_cqe_flg; 4139fc48b7a6SYuval Mintz u8 complete_event_flg; 4140fc48b7a6SYuval Mintz u8 stats_counter_id; 4141fc48b7a6SYuval Mintz u8 pin_context; 4142fc48b7a6SYuval Mintz u8 pxp_tph_valid_bd; 4143fc48b7a6SYuval Mintz u8 pxp_tph_valid_pkt; 4144fc48b7a6SYuval Mintz u8 pxp_st_hint; 4145351a4dedSYuval Mintz 4146fc48b7a6SYuval Mintz __le16 pxp_st_index; 4147fc48b7a6SYuval Mintz u8 pmd_mode; 4148351a4dedSYuval Mintz 4149fc48b7a6SYuval Mintz u8 notify_en; 4150fc48b7a6SYuval Mintz u8 toggle_val; 4151351a4dedSYuval Mintz 4152351a4dedSYuval Mintz u8 vf_rx_prod_index; 415305fafbfbSYuval Mintz u8 vf_rx_prod_use_zone_a; 415405fafbfbSYuval Mintz u8 reserved[5]; 4155fc48b7a6SYuval Mintz __le16 reserved1; 4156fc48b7a6SYuval Mintz struct regpair cqe_pbl_addr; 4157fc48b7a6SYuval Mintz struct regpair bd_base; 4158fc48b7a6SYuval Mintz struct regpair reserved2; 4159fc48b7a6SYuval Mintz }; 4160fc48b7a6SYuval Mintz 4161a2e7699eSTomer Tayar /* Ramrod data for rx queue stop ramrod */ 4162fc48b7a6SYuval Mintz struct rx_queue_stop_ramrod_data { 4163fc48b7a6SYuval Mintz __le16 rx_queue_id; 4164fc48b7a6SYuval Mintz u8 complete_cqe_flg; 4165fc48b7a6SYuval Mintz u8 complete_event_flg; 4166fc48b7a6SYuval Mintz u8 vport_id; 4167fc48b7a6SYuval Mintz u8 reserved[3]; 4168fc48b7a6SYuval Mintz }; 4169fc48b7a6SYuval Mintz 4170351a4dedSYuval Mintz /* Ramrod data for rx queue update ramrod */ 4171fc48b7a6SYuval Mintz struct rx_queue_update_ramrod_data { 4172fc48b7a6SYuval Mintz __le16 rx_queue_id; 4173fc48b7a6SYuval Mintz u8 complete_cqe_flg; 4174fc48b7a6SYuval Mintz u8 complete_event_flg; 4175fc48b7a6SYuval Mintz u8 vport_id; 417650bc60cbSMichal Kalderon u8 set_default_rss_queue; 417750bc60cbSMichal Kalderon u8 reserved[3]; 4178fc48b7a6SYuval Mintz u8 reserved1; 4179fc48b7a6SYuval Mintz u8 reserved2; 4180fc48b7a6SYuval Mintz u8 reserved3; 4181fc48b7a6SYuval Mintz __le16 reserved4; 4182fc48b7a6SYuval Mintz __le16 reserved5; 4183fc48b7a6SYuval Mintz struct regpair reserved6; 4184fc48b7a6SYuval Mintz }; 4185fc48b7a6SYuval Mintz 4186351a4dedSYuval Mintz /* Ramrod data for rx Add UDP Filter */ 4187fe40a830SPrabhakar Kushwaha struct rx_udp_filter_ramrod_data { 4188351a4dedSYuval Mintz __le16 action_icid; 4189351a4dedSYuval Mintz __le16 vlan_id; 4190351a4dedSYuval Mintz u8 ip_type; 4191351a4dedSYuval Mintz u8 tenant_id_exists; 4192351a4dedSYuval Mintz __le16 reserved1; 4193351a4dedSYuval Mintz __le32 ip_dst_addr[4]; 4194351a4dedSYuval Mintz __le32 ip_src_addr[4]; 4195351a4dedSYuval Mintz __le16 udp_dst_port; 4196351a4dedSYuval Mintz __le16 udp_src_port; 4197351a4dedSYuval Mintz __le32 tenant_id; 4198351a4dedSYuval Mintz }; 4199351a4dedSYuval Mintz 4200a2e7699eSTomer Tayar /* Add or delete GFT filter - filter is packet header of type of packet wished 4201a2e7699eSTomer Tayar * to pass certain FW flow. 4202a2e7699eSTomer Tayar */ 4203fe40a830SPrabhakar Kushwaha struct rx_update_gft_filter_ramrod_data { 4204d51e4af5SChopra, Manish struct regpair pkt_hdr_addr; 4205d51e4af5SChopra, Manish __le16 pkt_hdr_length; 4206da090917STomer Tayar __le16 action_icid; 4207da090917STomer Tayar __le16 rx_qid; 4208da090917STomer Tayar __le16 flow_id; 4209da090917STomer Tayar __le16 vport_id; 4210da090917STomer Tayar u8 action_icid_valid; 4211da090917STomer Tayar u8 rx_qid_valid; 4212da090917STomer Tayar u8 flow_id_valid; 4213d51e4af5SChopra, Manish u8 filter_action; 42147b6859fbSMintz, Yuval u8 assert_on_error; 421550bc60cbSMichal Kalderon u8 inner_vlan_removal_en; 4216d51e4af5SChopra, Manish }; 4217d51e4af5SChopra, Manish 42180500a70dSMichal Kalderon /* Ramrod data for tx queue start ramrod */ 4219fc48b7a6SYuval Mintz struct tx_queue_start_ramrod_data { 4220fc48b7a6SYuval Mintz __le16 sb_id; 4221fc48b7a6SYuval Mintz u8 sb_index; 4222fc48b7a6SYuval Mintz u8 vport_id; 4223fc48b7a6SYuval Mintz u8 reserved0; 4224fc48b7a6SYuval Mintz u8 stats_counter_id; 4225fc48b7a6SYuval Mintz __le16 qm_pq_id; 4226fc48b7a6SYuval Mintz u8 flags; 4227fc48b7a6SYuval Mintz #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1 4228fc48b7a6SYuval Mintz #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0 4229fc48b7a6SYuval Mintz #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1 4230fc48b7a6SYuval Mintz #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1 4231fc48b7a6SYuval Mintz #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1 42320500a70dSMichal Kalderon #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 2 4233fc48b7a6SYuval Mintz #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1 42340500a70dSMichal Kalderon #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 3 4235fc48b7a6SYuval Mintz #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1 42360500a70dSMichal Kalderon #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 4 42370500a70dSMichal Kalderon #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x7 42380500a70dSMichal Kalderon #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 5 4239fc48b7a6SYuval Mintz u8 pxp_st_hint; 4240fc48b7a6SYuval Mintz u8 pxp_tph_valid_bd; 4241fc48b7a6SYuval Mintz u8 pxp_tph_valid_pkt; 4242fc48b7a6SYuval Mintz __le16 pxp_st_index; 4243fe40a830SPrabhakar Kushwaha u8 comp_agg_size; 4244fe40a830SPrabhakar Kushwaha u8 reserved3; 4245fc48b7a6SYuval Mintz __le16 queue_zone_id; 424605fafbfbSYuval Mintz __le16 reserved2; 4247fc48b7a6SYuval Mintz __le16 pbl_size; 4248fc48b7a6SYuval Mintz __le16 tx_queue_id; 424905fafbfbSYuval Mintz __le16 same_as_last_id; 425005fafbfbSYuval Mintz __le16 reserved[3]; 4251fc48b7a6SYuval Mintz struct regpair pbl_base_addr; 4252fc48b7a6SYuval Mintz struct regpair bd_cons_address; 4253fc48b7a6SYuval Mintz }; 4254fc48b7a6SYuval Mintz 4255351a4dedSYuval Mintz /* Ramrod data for tx queue stop ramrod */ 4256fc48b7a6SYuval Mintz struct tx_queue_stop_ramrod_data { 4257fc48b7a6SYuval Mintz __le16 reserved[4]; 4258fc48b7a6SYuval Mintz }; 4259fc48b7a6SYuval Mintz 4260da090917STomer Tayar /* Ramrod data for tx queue update ramrod */ 4261da090917STomer Tayar struct tx_queue_update_ramrod_data { 4262da090917STomer Tayar __le16 update_qm_pq_id_flg; 4263da090917STomer Tayar __le16 qm_pq_id; 4264da090917STomer Tayar __le32 reserved0; 4265da090917STomer Tayar struct regpair reserved1[5]; 4266da090917STomer Tayar }; 4267da090917STomer Tayar 4268a3f72307SDenis Bolotin /* Inner to Inner VLAN priority map update mode */ 4269a3f72307SDenis Bolotin enum update_in_to_in_pri_map_mode_enum { 4270a3f72307SDenis Bolotin ETH_IN_TO_IN_PRI_MAP_UPDATE_DISABLED, 4271a3f72307SDenis Bolotin ETH_IN_TO_IN_PRI_MAP_UPDATE_NON_RDMA_TBL, 4272a3f72307SDenis Bolotin ETH_IN_TO_IN_PRI_MAP_UPDATE_RDMA_TBL, 4273a3f72307SDenis Bolotin MAX_UPDATE_IN_TO_IN_PRI_MAP_MODE_ENUM 4274a3f72307SDenis Bolotin }; 4275a3f72307SDenis Bolotin 4276351a4dedSYuval Mintz /* Ramrod data for vport update ramrod */ 4277fc48b7a6SYuval Mintz struct vport_filter_update_ramrod_data { 4278fc48b7a6SYuval Mintz struct eth_filter_cmd_header filter_cmd_hdr; 4279fc48b7a6SYuval Mintz struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT]; 4280fc48b7a6SYuval Mintz }; 4281fc48b7a6SYuval Mintz 4282351a4dedSYuval Mintz /* Ramrod data for vport start ramrod */ 4283fc48b7a6SYuval Mintz struct vport_start_ramrod_data { 4284fc48b7a6SYuval Mintz u8 vport_id; 4285fc48b7a6SYuval Mintz u8 sw_fid; 4286fc48b7a6SYuval Mintz __le16 mtu; 4287fc48b7a6SYuval Mintz u8 drop_ttl0_en; 4288fc48b7a6SYuval Mintz u8 inner_vlan_removal_en; 4289fc48b7a6SYuval Mintz struct eth_vport_rx_mode rx_mode; 4290fc48b7a6SYuval Mintz struct eth_vport_tx_mode tx_mode; 4291fc48b7a6SYuval Mintz struct eth_vport_tpa_param tpa_param; 4292fc48b7a6SYuval Mintz __le16 default_vlan; 4293fc48b7a6SYuval Mintz u8 tx_switching_en; 4294fc48b7a6SYuval Mintz u8 anti_spoofing_en; 4295fc48b7a6SYuval Mintz u8 default_vlan_en; 4296fc48b7a6SYuval Mintz u8 handle_ptp_pkts; 4297fc48b7a6SYuval Mintz u8 silent_vlan_removal_en; 4298fc48b7a6SYuval Mintz u8 untagged; 4299fc48b7a6SYuval Mintz struct eth_tx_err_vals tx_err_behav; 4300fc48b7a6SYuval Mintz u8 zero_placement_offset; 4301351a4dedSYuval Mintz u8 ctl_frame_mac_check_en; 4302351a4dedSYuval Mintz u8 ctl_frame_ethtype_check_en; 43030500a70dSMichal Kalderon u8 reserved0; 43040500a70dSMichal Kalderon u8 reserved1; 43050500a70dSMichal Kalderon u8 tx_dst_port_mode_config; 43060500a70dSMichal Kalderon u8 dst_vport_id; 43070500a70dSMichal Kalderon u8 tx_dst_port_mode; 43080500a70dSMichal Kalderon u8 dst_vport_id_valid; 4309a3f72307SDenis Bolotin u8 wipe_inner_vlan_pri_en; 43100500a70dSMichal Kalderon u8 reserved2[2]; 4311a3f72307SDenis Bolotin struct eth_in_to_in_pri_map_cfg in_to_in_vlan_pri_map_cfg; 4312fc48b7a6SYuval Mintz }; 4313fc48b7a6SYuval Mintz 4314351a4dedSYuval Mintz /* Ramrod data for vport stop ramrod */ 4315fc48b7a6SYuval Mintz struct vport_stop_ramrod_data { 4316fc48b7a6SYuval Mintz u8 vport_id; 4317fc48b7a6SYuval Mintz u8 reserved[7]; 4318fc48b7a6SYuval Mintz }; 4319fc48b7a6SYuval Mintz 4320351a4dedSYuval Mintz /* Ramrod data for vport update ramrod */ 4321fc48b7a6SYuval Mintz struct vport_update_ramrod_data_cmn { 4322fc48b7a6SYuval Mintz u8 vport_id; 4323fc48b7a6SYuval Mintz u8 update_rx_active_flg; 4324fc48b7a6SYuval Mintz u8 rx_active_flg; 4325fc48b7a6SYuval Mintz u8 update_tx_active_flg; 4326fc48b7a6SYuval Mintz u8 tx_active_flg; 4327fc48b7a6SYuval Mintz u8 update_rx_mode_flg; 4328fc48b7a6SYuval Mintz u8 update_tx_mode_flg; 4329fc48b7a6SYuval Mintz u8 update_approx_mcast_flg; 4330351a4dedSYuval Mintz 4331fc48b7a6SYuval Mintz u8 update_rss_flg; 4332fc48b7a6SYuval Mintz u8 update_inner_vlan_removal_en_flg; 4333351a4dedSYuval Mintz 4334fc48b7a6SYuval Mintz u8 inner_vlan_removal_en; 4335fc48b7a6SYuval Mintz u8 update_tpa_param_flg; 4336fc48b7a6SYuval Mintz u8 update_tpa_en_flg; 4337fc48b7a6SYuval Mintz u8 update_tx_switching_en_flg; 4338351a4dedSYuval Mintz 4339fc48b7a6SYuval Mintz u8 tx_switching_en; 4340fc48b7a6SYuval Mintz u8 update_anti_spoofing_en_flg; 4341351a4dedSYuval Mintz 4342fc48b7a6SYuval Mintz u8 anti_spoofing_en; 4343fc48b7a6SYuval Mintz u8 update_handle_ptp_pkts; 4344351a4dedSYuval Mintz 4345fc48b7a6SYuval Mintz u8 handle_ptp_pkts; 4346fc48b7a6SYuval Mintz u8 update_default_vlan_en_flg; 4347351a4dedSYuval Mintz 4348fc48b7a6SYuval Mintz u8 default_vlan_en; 4349351a4dedSYuval Mintz 4350fc48b7a6SYuval Mintz u8 update_default_vlan_flg; 4351351a4dedSYuval Mintz 4352fc48b7a6SYuval Mintz __le16 default_vlan; 4353fc48b7a6SYuval Mintz u8 update_accept_any_vlan_flg; 4354351a4dedSYuval Mintz 4355fc48b7a6SYuval Mintz u8 accept_any_vlan; 4356fc48b7a6SYuval Mintz u8 silent_vlan_removal_en; 4357fc48b7a6SYuval Mintz u8 update_mtu_flg; 4358351a4dedSYuval Mintz 4359fc48b7a6SYuval Mintz __le16 mtu; 4360be086e7cSMintz, Yuval u8 update_ctl_frame_checks_en_flg; 4361be086e7cSMintz, Yuval u8 ctl_frame_mac_check_en; 4362be086e7cSMintz, Yuval u8 ctl_frame_ethtype_check_en; 4363a3f72307SDenis Bolotin u8 update_in_to_in_pri_map_mode; 4364a3f72307SDenis Bolotin u8 in_to_in_pri_map[8]; 4365fe40a830SPrabhakar Kushwaha u8 update_tx_dst_port_mode_flg; 4366fe40a830SPrabhakar Kushwaha u8 tx_dst_port_mode_config; 4367fe40a830SPrabhakar Kushwaha u8 dst_vport_id; 4368fe40a830SPrabhakar Kushwaha u8 tx_dst_port_mode; 4369fe40a830SPrabhakar Kushwaha u8 dst_vport_id_valid; 4370fe40a830SPrabhakar Kushwaha u8 reserved[1]; 4371fc48b7a6SYuval Mintz }; 4372fc48b7a6SYuval Mintz 4373fc48b7a6SYuval Mintz struct vport_update_ramrod_mcast { 4374fc48b7a6SYuval Mintz __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS]; 4375fc48b7a6SYuval Mintz }; 4376fc48b7a6SYuval Mintz 4377351a4dedSYuval Mintz /* Ramrod data for vport update ramrod */ 4378fc48b7a6SYuval Mintz struct vport_update_ramrod_data { 4379fc48b7a6SYuval Mintz struct vport_update_ramrod_data_cmn common; 4380351a4dedSYuval Mintz 4381fc48b7a6SYuval Mintz struct eth_vport_rx_mode rx_mode; 4382fc48b7a6SYuval Mintz struct eth_vport_tx_mode tx_mode; 438350bc60cbSMichal Kalderon __le32 reserved[3]; 4384fc48b7a6SYuval Mintz struct eth_vport_tpa_param tpa_param; 4385fc48b7a6SYuval Mintz struct vport_update_ramrod_mcast approx_mcast; 4386fc48b7a6SYuval Mintz struct eth_vport_rss_config rss_config; 4387fe56b9e6SYuval Mintz }; 4388fe56b9e6SYuval Mintz 4389fb09a1edSShai Malin struct xstorm_eth_conn_ag_ctx_dq_ext_ldpart { 4390be086e7cSMintz, Yuval u8 reserved0; 4391da090917STomer Tayar u8 state; 4392be086e7cSMintz, Yuval u8 flags0; 439321dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 439421dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 439521dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1 439621dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1 439721dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1 439821dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2 439921dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 440021dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 440121dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1 440221dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4 440321dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1 440421dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5 440521dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1 440621dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6 440721dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1 440821dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7 4409be086e7cSMintz, Yuval u8 flags1; 441021dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1 441121dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0 441221dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1 441321dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1 441421dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1 441521dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2 441621dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 441721dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 4418da090917STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_MASK 0x1 4419da090917STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_SHIFT 4 4420da090917STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_MASK 0x1 4421da090917STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_SHIFT 5 442221dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1 442321dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6 442421dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1 442521dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7 4426be086e7cSMintz, Yuval u8 flags2; 442721dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3 442821dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0 442921dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3 443021dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2 443121dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3 443221dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4 443321dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3 443421dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6 4435be086e7cSMintz, Yuval u8 flags3; 443621dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3 443721dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0 443821dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3 443921dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2 444021dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3 444121dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4 444221dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3 444321dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6 4444be086e7cSMintz, Yuval u8 flags4; 444521dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3 444621dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0 444721dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3 444821dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2 444921dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3 445021dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4 445121dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3 445221dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6 4453be086e7cSMintz, Yuval u8 flags5; 445421dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3 445521dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0 445621dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3 445721dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2 445821dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3 445921dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4 446021dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3 446121dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6 4462be086e7cSMintz, Yuval u8 flags6; 446321dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3 446421dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0 446521dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3 446621dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2 446721dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3 446821dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4 446921dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3 447021dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6 4471be086e7cSMintz, Yuval u8 flags7; 447221dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3 447321dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0 447421dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3 447521dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2 447621dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 447721dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 447821dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 447921dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 448021dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 448121dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 4482be086e7cSMintz, Yuval u8 flags8; 448321dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 448421dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 448521dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 448621dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 448721dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 448821dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2 448921dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 449021dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3 449121dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 449221dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4 449321dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1 449421dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5 449521dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 449621dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 449721dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 449821dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 4499be086e7cSMintz, Yuval u8 flags9; 450021dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 450121dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 450221dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 450321dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 450421dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 450521dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 450621dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 450721dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 450821dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 450921dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4 451021dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 451121dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 451221dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1 451321dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6 451421dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1 451521dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7 4516be086e7cSMintz, Yuval u8 flags10; 451721dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1 451821dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0 451921dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1 452021dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1 452121dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1 452221dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2 452321dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1 452421dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3 452521dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 452621dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 452721dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1 452821dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5 452921dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1 453021dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6 453121dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1 453221dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7 4533be086e7cSMintz, Yuval u8 flags11; 453421dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1 453521dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0 453621dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1 453721dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1 453821dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1 453921dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2 454021dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 454121dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 454221dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 454321dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 454421dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 454521dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5 454621dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 454721dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 454821dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 454921dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 4550be086e7cSMintz, Yuval u8 flags12; 455121dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 455221dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0 455321dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 455421dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 455521dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 455621dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 455721dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 455821dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 455921dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 456021dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4 456121dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 456221dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 456321dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 456421dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6 456521dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 456621dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7 4567be086e7cSMintz, Yuval u8 flags13; 456821dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 456921dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 457021dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 457121dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 457221dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 457321dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 457421dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 457521dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 457621dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 457721dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 457821dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 457921dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 458021dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 458121dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 458221dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 458321dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 4584be086e7cSMintz, Yuval u8 flags14; 458521dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1 458621dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0 458721dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1 458821dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1 458921dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1 459021dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2 459121dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1 459221dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3 459321dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1 459421dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4 459521dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 459621dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 459721dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3 459821dd79e8STomer Tayar #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6 4599be086e7cSMintz, Yuval u8 edpm_event_id; 4600be086e7cSMintz, Yuval __le16 physical_q0; 460121dd79e8STomer Tayar __le16 e5_reserved1; 4602be086e7cSMintz, Yuval __le16 edpm_num_bds; 4603be086e7cSMintz, Yuval __le16 tx_bd_cons; 4604be086e7cSMintz, Yuval __le16 tx_bd_prod; 460550bc60cbSMichal Kalderon __le16 updated_qm_pq_id; 4606be086e7cSMintz, Yuval __le16 conn_dpi; 4607be086e7cSMintz, Yuval u8 byte3; 4608be086e7cSMintz, Yuval u8 byte4; 4609be086e7cSMintz, Yuval u8 byte5; 4610be086e7cSMintz, Yuval u8 byte6; 4611be086e7cSMintz, Yuval __le32 reg0; 4612be086e7cSMintz, Yuval __le32 reg1; 4613be086e7cSMintz, Yuval __le32 reg2; 4614be086e7cSMintz, Yuval __le32 reg3; 4615be086e7cSMintz, Yuval __le32 reg4; 4616be086e7cSMintz, Yuval }; 4617be086e7cSMintz, Yuval 4618fb09a1edSShai Malin struct mstorm_eth_conn_ag_ctx { 46197b6859fbSMintz, Yuval u8 byte0; 46207b6859fbSMintz, Yuval u8 byte1; 46217b6859fbSMintz, Yuval u8 flags0; 4622fb09a1edSShai Malin #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 4623fb09a1edSShai Malin #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 4624fb09a1edSShai Malin #define MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 4625fb09a1edSShai Malin #define MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 4626fb09a1edSShai Malin #define MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 4627fb09a1edSShai Malin #define MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2 4628fb09a1edSShai Malin #define MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 4629fb09a1edSShai Malin #define MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4 4630fb09a1edSShai Malin #define MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 4631fb09a1edSShai Malin #define MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 46327b6859fbSMintz, Yuval u8 flags1; 4633fb09a1edSShai Malin #define MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 4634fb09a1edSShai Malin #define MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0 4635fb09a1edSShai Malin #define MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 4636fb09a1edSShai Malin #define MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1 4637fb09a1edSShai Malin #define MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 4638fb09a1edSShai Malin #define MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 4639fb09a1edSShai Malin #define MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 4640fb09a1edSShai Malin #define MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 4641fb09a1edSShai Malin #define MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 4642fb09a1edSShai Malin #define MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 4643fb09a1edSShai Malin #define MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 4644fb09a1edSShai Malin #define MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 4645fb09a1edSShai Malin #define MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 4646fb09a1edSShai Malin #define MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 4647fb09a1edSShai Malin #define MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 4648fb09a1edSShai Malin #define MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 46497b6859fbSMintz, Yuval __le16 word0; 46507b6859fbSMintz, Yuval __le16 word1; 46517b6859fbSMintz, Yuval __le32 reg0; 46527b6859fbSMintz, Yuval __le32 reg1; 46537b6859fbSMintz, Yuval }; 46547b6859fbSMintz, Yuval 4655fb09a1edSShai Malin struct xstorm_eth_hw_conn_ag_ctx { 4656be086e7cSMintz, Yuval u8 reserved0; 4657da090917STomer Tayar u8 state; 4658be086e7cSMintz, Yuval u8 flags0; 4659fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 4660fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 4661fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1 4662fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1 4663fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1 4664fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2 4665fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 4666fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 4667fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1 4668fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4 4669fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1 4670fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5 4671fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1 4672fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6 4673fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1 4674fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7 4675be086e7cSMintz, Yuval u8 flags1; 4676fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1 4677fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0 4678fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1 4679fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1 4680fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1 4681fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2 4682fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1 4683fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3 4684fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_MASK 0x1 4685fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_SHIFT 4 4686fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_MASK 0x1 4687fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_SHIFT 5 4688fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 4689fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 4690fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 4691fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 4692be086e7cSMintz, Yuval u8 flags2; 4693fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3 4694fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0 4695fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3 4696fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2 4697fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3 4698fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4 4699fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3 4700fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6 4701be086e7cSMintz, Yuval u8 flags3; 4702fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3 4703fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0 4704fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3 4705fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2 4706fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3 4707fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4 4708fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3 4709fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6 4710be086e7cSMintz, Yuval u8 flags4; 4711fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3 4712fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0 4713fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3 4714fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2 4715fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3 4716fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4 4717fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3 4718fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6 4719be086e7cSMintz, Yuval u8 flags5; 4720fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3 4721fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0 4722fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3 4723fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2 4724fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3 4725fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4 4726fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3 4727fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6 4728be086e7cSMintz, Yuval u8 flags6; 4729fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 4730fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 4731fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 4732fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 4733fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3 4734fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4 4735fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 4736fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 4737be086e7cSMintz, Yuval u8 flags7; 4738fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 4739fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 4740fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3 4741fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2 4742fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3 4743fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4 4744fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1 4745fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6 4746fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1 4747fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7 4748be086e7cSMintz, Yuval u8 flags8; 4749fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1 4750fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0 4751fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1 4752fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1 4753fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1 4754fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2 4755fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1 4756fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3 4757fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1 4758fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4 4759fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1 4760fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5 4761fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1 4762fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6 4763fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1 4764fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7 4765be086e7cSMintz, Yuval u8 flags9; 4766fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1 4767fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0 4768fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1 4769fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1 4770fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1 4771fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2 4772fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1 4773fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3 4774fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1 4775fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4 4776fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1 4777fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5 4778fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 4779fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 4780fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 4781fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 4782be086e7cSMintz, Yuval u8 flags10; 4783fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 4784fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 4785fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 4786fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 4787fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 4788fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 4789fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1 4790fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3 4791fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 4792fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 4793fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 4794fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 4795fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1 4796fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6 4797fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1 4798fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7 4799be086e7cSMintz, Yuval u8 flags11; 4800fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1 4801fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0 4802fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1 4803fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1 4804fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 4805fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 4806fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1 4807fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3 4808fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1 4809fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4 4810fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1 4811fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5 4812fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 4813fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 4814fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1 4815fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7 4816be086e7cSMintz, Yuval u8 flags12; 4817fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1 4818fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0 4819fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1 4820fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1 4821fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 4822fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 4823fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 4824fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 4825fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1 4826fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4 4827fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1 4828fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5 4829fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1 4830fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6 4831fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1 4832fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7 4833be086e7cSMintz, Yuval u8 flags13; 4834fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1 4835fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0 4836fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1 4837fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1 4838fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 4839fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 4840fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 4841fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 4842fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 4843fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 4844fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 4845fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 4846fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 4847fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 4848fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 4849fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 4850be086e7cSMintz, Yuval u8 flags14; 4851fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 4852fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 4853fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 4854fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 4855fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 4856fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 4857fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 4858fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 4859fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 4860fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 4861fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 4862fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 4863fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 4864fb09a1edSShai Malin #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 4865be086e7cSMintz, Yuval u8 edpm_event_id; 4866be086e7cSMintz, Yuval __le16 physical_q0; 486721dd79e8STomer Tayar __le16 e5_reserved1; 4868be086e7cSMintz, Yuval __le16 edpm_num_bds; 4869be086e7cSMintz, Yuval __le16 tx_bd_cons; 4870be086e7cSMintz, Yuval __le16 tx_bd_prod; 487150bc60cbSMichal Kalderon __le16 updated_qm_pq_id; 4872be086e7cSMintz, Yuval __le16 conn_dpi; 4873be086e7cSMintz, Yuval }; 4874be086e7cSMintz, Yuval 4875a2e7699eSTomer Tayar /* GFT CAM line struct with fields breakout */ 48767b6859fbSMintz, Yuval struct gft_cam_line_mapped { 48777b6859fbSMintz, Yuval __le32 camline; 48787b6859fbSMintz, Yuval #define GFT_CAM_LINE_MAPPED_VALID_MASK 0x1 48797b6859fbSMintz, Yuval #define GFT_CAM_LINE_MAPPED_VALID_SHIFT 0 48807b6859fbSMintz, Yuval #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK 0x1 48817b6859fbSMintz, Yuval #define GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT 1 48827b6859fbSMintz, Yuval #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK 0x1 48837b6859fbSMintz, Yuval #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT 2 48847b6859fbSMintz, Yuval #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK 0xF 48857b6859fbSMintz, Yuval #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT 3 48867b6859fbSMintz, Yuval #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK 0xF 48877b6859fbSMintz, Yuval #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT 7 48887b6859fbSMintz, Yuval #define GFT_CAM_LINE_MAPPED_PF_ID_MASK 0xF 48897b6859fbSMintz, Yuval #define GFT_CAM_LINE_MAPPED_PF_ID_SHIFT 11 48907b6859fbSMintz, Yuval #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK 0x1 48917b6859fbSMintz, Yuval #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT 15 48927b6859fbSMintz, Yuval #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK 0x1 48937b6859fbSMintz, Yuval #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT 16 48947b6859fbSMintz, Yuval #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK 0xF 48957b6859fbSMintz, Yuval #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT 17 48967b6859fbSMintz, Yuval #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK 0xF 48977b6859fbSMintz, Yuval #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT 21 48987b6859fbSMintz, Yuval #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK 0xF 48997b6859fbSMintz, Yuval #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_SHIFT 25 49007b6859fbSMintz, Yuval #define GFT_CAM_LINE_MAPPED_RESERVED1_MASK 0x7 49017b6859fbSMintz, Yuval #define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT 29 49027b6859fbSMintz, Yuval }; 49037b6859fbSMintz, Yuval 4904a2e7699eSTomer Tayar /* Used in gft_profile_key: Indication for ip version */ 49057b6859fbSMintz, Yuval enum gft_profile_ip_version { 49067b6859fbSMintz, Yuval GFT_PROFILE_IPV4 = 0, 49077b6859fbSMintz, Yuval GFT_PROFILE_IPV6 = 1, 49087b6859fbSMintz, Yuval MAX_GFT_PROFILE_IP_VERSION 49097b6859fbSMintz, Yuval }; 49107b6859fbSMintz, Yuval 4911a2e7699eSTomer Tayar /* Profile key stucr fot GFT logic in Prs */ 49127b6859fbSMintz, Yuval struct gft_profile_key { 49137b6859fbSMintz, Yuval __le16 profile_key; 49147b6859fbSMintz, Yuval #define GFT_PROFILE_KEY_IP_VERSION_MASK 0x1 49157b6859fbSMintz, Yuval #define GFT_PROFILE_KEY_IP_VERSION_SHIFT 0 49167b6859fbSMintz, Yuval #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK 0x1 49177b6859fbSMintz, Yuval #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT 1 49187b6859fbSMintz, Yuval #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK 0xF 49197b6859fbSMintz, Yuval #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT 2 49207b6859fbSMintz, Yuval #define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK 0xF 49217b6859fbSMintz, Yuval #define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT 6 49227b6859fbSMintz, Yuval #define GFT_PROFILE_KEY_PF_ID_MASK 0xF 49237b6859fbSMintz, Yuval #define GFT_PROFILE_KEY_PF_ID_SHIFT 10 49247b6859fbSMintz, Yuval #define GFT_PROFILE_KEY_RESERVED0_MASK 0x3 49257b6859fbSMintz, Yuval #define GFT_PROFILE_KEY_RESERVED0_SHIFT 14 49267b6859fbSMintz, Yuval }; 49277b6859fbSMintz, Yuval 4928a2e7699eSTomer Tayar /* Used in gft_profile_key: Indication for tunnel type */ 49297b6859fbSMintz, Yuval enum gft_profile_tunnel_type { 49307b6859fbSMintz, Yuval GFT_PROFILE_NO_TUNNEL = 0, 49317b6859fbSMintz, Yuval GFT_PROFILE_VXLAN_TUNNEL = 1, 49327b6859fbSMintz, Yuval GFT_PROFILE_GRE_MAC_OR_NVGRE_TUNNEL = 2, 49337b6859fbSMintz, Yuval GFT_PROFILE_GRE_IP_TUNNEL = 3, 49347b6859fbSMintz, Yuval GFT_PROFILE_GENEVE_MAC_TUNNEL = 4, 49357b6859fbSMintz, Yuval GFT_PROFILE_GENEVE_IP_TUNNEL = 5, 49367b6859fbSMintz, Yuval MAX_GFT_PROFILE_TUNNEL_TYPE 49377b6859fbSMintz, Yuval }; 49387b6859fbSMintz, Yuval 4939a2e7699eSTomer Tayar /* Used in gft_profile_key: Indication for protocol type */ 49407b6859fbSMintz, Yuval enum gft_profile_upper_protocol_type { 49417b6859fbSMintz, Yuval GFT_PROFILE_ROCE_PROTOCOL = 0, 49427b6859fbSMintz, Yuval GFT_PROFILE_RROCE_PROTOCOL = 1, 49437b6859fbSMintz, Yuval GFT_PROFILE_FCOE_PROTOCOL = 2, 49447b6859fbSMintz, Yuval GFT_PROFILE_ICMP_PROTOCOL = 3, 49457b6859fbSMintz, Yuval GFT_PROFILE_ARP_PROTOCOL = 4, 49467b6859fbSMintz, Yuval GFT_PROFILE_USER_TCP_SRC_PORT_1_INNER = 5, 49477b6859fbSMintz, Yuval GFT_PROFILE_USER_TCP_DST_PORT_1_INNER = 6, 49487b6859fbSMintz, Yuval GFT_PROFILE_TCP_PROTOCOL = 7, 49497b6859fbSMintz, Yuval GFT_PROFILE_USER_UDP_DST_PORT_1_INNER = 8, 49507b6859fbSMintz, Yuval GFT_PROFILE_USER_UDP_DST_PORT_2_OUTER = 9, 49517b6859fbSMintz, Yuval GFT_PROFILE_UDP_PROTOCOL = 10, 49527b6859fbSMintz, Yuval GFT_PROFILE_USER_IP_1_INNER = 11, 49537b6859fbSMintz, Yuval GFT_PROFILE_USER_IP_2_OUTER = 12, 49547b6859fbSMintz, Yuval GFT_PROFILE_USER_ETH_1_INNER = 13, 49557b6859fbSMintz, Yuval GFT_PROFILE_USER_ETH_2_OUTER = 14, 49567b6859fbSMintz, Yuval GFT_PROFILE_RAW = 15, 49577b6859fbSMintz, Yuval MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE 49587b6859fbSMintz, Yuval }; 49597b6859fbSMintz, Yuval 4960a2e7699eSTomer Tayar /* GFT RAM line struct */ 49617b6859fbSMintz, Yuval struct gft_ram_line { 49627b6859fbSMintz, Yuval __le32 lo; 49637b6859fbSMintz, Yuval #define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3 49647b6859fbSMintz, Yuval #define GFT_RAM_LINE_VLAN_SELECT_SHIFT 0 49657b6859fbSMintz, Yuval #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK 0x1 49667b6859fbSMintz, Yuval #define GFT_RAM_LINE_TUNNEL_ENTROPHY_SHIFT 2 49677b6859fbSMintz, Yuval #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK 0x1 49687b6859fbSMintz, Yuval #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_SHIFT 3 49697b6859fbSMintz, Yuval #define GFT_RAM_LINE_TUNNEL_TTL_MASK 0x1 49707b6859fbSMintz, Yuval #define GFT_RAM_LINE_TUNNEL_TTL_SHIFT 4 49717b6859fbSMintz, Yuval #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK 0x1 49727b6859fbSMintz, Yuval #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_SHIFT 5 49737b6859fbSMintz, Yuval #define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK 0x1 49747b6859fbSMintz, Yuval #define GFT_RAM_LINE_TUNNEL_DST_PORT_SHIFT 6 49757b6859fbSMintz, Yuval #define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK 0x1 49767b6859fbSMintz, Yuval #define GFT_RAM_LINE_TUNNEL_SRC_PORT_SHIFT 7 49777b6859fbSMintz, Yuval #define GFT_RAM_LINE_TUNNEL_DSCP_MASK 0x1 49787b6859fbSMintz, Yuval #define GFT_RAM_LINE_TUNNEL_DSCP_SHIFT 8 49797b6859fbSMintz, Yuval #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK 0x1 49807b6859fbSMintz, Yuval #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_SHIFT 9 49817b6859fbSMintz, Yuval #define GFT_RAM_LINE_TUNNEL_DST_IP_MASK 0x1 49827b6859fbSMintz, Yuval #define GFT_RAM_LINE_TUNNEL_DST_IP_SHIFT 10 49837b6859fbSMintz, Yuval #define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK 0x1 49847b6859fbSMintz, Yuval #define GFT_RAM_LINE_TUNNEL_SRC_IP_SHIFT 11 49857b6859fbSMintz, Yuval #define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK 0x1 49867b6859fbSMintz, Yuval #define GFT_RAM_LINE_TUNNEL_PRIORITY_SHIFT 12 49877b6859fbSMintz, Yuval #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK 0x1 49887b6859fbSMintz, Yuval #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_SHIFT 13 49897b6859fbSMintz, Yuval #define GFT_RAM_LINE_TUNNEL_VLAN_MASK 0x1 49907b6859fbSMintz, Yuval #define GFT_RAM_LINE_TUNNEL_VLAN_SHIFT 14 49917b6859fbSMintz, Yuval #define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK 0x1 49927b6859fbSMintz, Yuval #define GFT_RAM_LINE_TUNNEL_DST_MAC_SHIFT 15 49937b6859fbSMintz, Yuval #define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK 0x1 49947b6859fbSMintz, Yuval #define GFT_RAM_LINE_TUNNEL_SRC_MAC_SHIFT 16 49957b6859fbSMintz, Yuval #define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK 0x1 49967b6859fbSMintz, Yuval #define GFT_RAM_LINE_TTL_EQUAL_ONE_SHIFT 17 49977b6859fbSMintz, Yuval #define GFT_RAM_LINE_TTL_MASK 0x1 49987b6859fbSMintz, Yuval #define GFT_RAM_LINE_TTL_SHIFT 18 49997b6859fbSMintz, Yuval #define GFT_RAM_LINE_ETHERTYPE_MASK 0x1 50007b6859fbSMintz, Yuval #define GFT_RAM_LINE_ETHERTYPE_SHIFT 19 50017b6859fbSMintz, Yuval #define GFT_RAM_LINE_RESERVED0_MASK 0x1 50027b6859fbSMintz, Yuval #define GFT_RAM_LINE_RESERVED0_SHIFT 20 50037b6859fbSMintz, Yuval #define GFT_RAM_LINE_TCP_FLAG_FIN_MASK 0x1 50047b6859fbSMintz, Yuval #define GFT_RAM_LINE_TCP_FLAG_FIN_SHIFT 21 50057b6859fbSMintz, Yuval #define GFT_RAM_LINE_TCP_FLAG_SYN_MASK 0x1 50067b6859fbSMintz, Yuval #define GFT_RAM_LINE_TCP_FLAG_SYN_SHIFT 22 50077b6859fbSMintz, Yuval #define GFT_RAM_LINE_TCP_FLAG_RST_MASK 0x1 50087b6859fbSMintz, Yuval #define GFT_RAM_LINE_TCP_FLAG_RST_SHIFT 23 50097b6859fbSMintz, Yuval #define GFT_RAM_LINE_TCP_FLAG_PSH_MASK 0x1 50107b6859fbSMintz, Yuval #define GFT_RAM_LINE_TCP_FLAG_PSH_SHIFT 24 50117b6859fbSMintz, Yuval #define GFT_RAM_LINE_TCP_FLAG_ACK_MASK 0x1 50127b6859fbSMintz, Yuval #define GFT_RAM_LINE_TCP_FLAG_ACK_SHIFT 25 50137b6859fbSMintz, Yuval #define GFT_RAM_LINE_TCP_FLAG_URG_MASK 0x1 50147b6859fbSMintz, Yuval #define GFT_RAM_LINE_TCP_FLAG_URG_SHIFT 26 50157b6859fbSMintz, Yuval #define GFT_RAM_LINE_TCP_FLAG_ECE_MASK 0x1 50167b6859fbSMintz, Yuval #define GFT_RAM_LINE_TCP_FLAG_ECE_SHIFT 27 50177b6859fbSMintz, Yuval #define GFT_RAM_LINE_TCP_FLAG_CWR_MASK 0x1 50187b6859fbSMintz, Yuval #define GFT_RAM_LINE_TCP_FLAG_CWR_SHIFT 28 50197b6859fbSMintz, Yuval #define GFT_RAM_LINE_TCP_FLAG_NS_MASK 0x1 50207b6859fbSMintz, Yuval #define GFT_RAM_LINE_TCP_FLAG_NS_SHIFT 29 50217b6859fbSMintz, Yuval #define GFT_RAM_LINE_DST_PORT_MASK 0x1 50227b6859fbSMintz, Yuval #define GFT_RAM_LINE_DST_PORT_SHIFT 30 50237b6859fbSMintz, Yuval #define GFT_RAM_LINE_SRC_PORT_MASK 0x1 50247b6859fbSMintz, Yuval #define GFT_RAM_LINE_SRC_PORT_SHIFT 31 50257b6859fbSMintz, Yuval __le32 hi; 50267b6859fbSMintz, Yuval #define GFT_RAM_LINE_DSCP_MASK 0x1 50277b6859fbSMintz, Yuval #define GFT_RAM_LINE_DSCP_SHIFT 0 50287b6859fbSMintz, Yuval #define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK 0x1 50297b6859fbSMintz, Yuval #define GFT_RAM_LINE_OVER_IP_PROTOCOL_SHIFT 1 50307b6859fbSMintz, Yuval #define GFT_RAM_LINE_DST_IP_MASK 0x1 50317b6859fbSMintz, Yuval #define GFT_RAM_LINE_DST_IP_SHIFT 2 50327b6859fbSMintz, Yuval #define GFT_RAM_LINE_SRC_IP_MASK 0x1 50337b6859fbSMintz, Yuval #define GFT_RAM_LINE_SRC_IP_SHIFT 3 50347b6859fbSMintz, Yuval #define GFT_RAM_LINE_PRIORITY_MASK 0x1 50357b6859fbSMintz, Yuval #define GFT_RAM_LINE_PRIORITY_SHIFT 4 50367b6859fbSMintz, Yuval #define GFT_RAM_LINE_PROVIDER_VLAN_MASK 0x1 50377b6859fbSMintz, Yuval #define GFT_RAM_LINE_PROVIDER_VLAN_SHIFT 5 50387b6859fbSMintz, Yuval #define GFT_RAM_LINE_VLAN_MASK 0x1 50397b6859fbSMintz, Yuval #define GFT_RAM_LINE_VLAN_SHIFT 6 50407b6859fbSMintz, Yuval #define GFT_RAM_LINE_DST_MAC_MASK 0x1 50417b6859fbSMintz, Yuval #define GFT_RAM_LINE_DST_MAC_SHIFT 7 50427b6859fbSMintz, Yuval #define GFT_RAM_LINE_SRC_MAC_MASK 0x1 50437b6859fbSMintz, Yuval #define GFT_RAM_LINE_SRC_MAC_SHIFT 8 50447b6859fbSMintz, Yuval #define GFT_RAM_LINE_TENANT_ID_MASK 0x1 50457b6859fbSMintz, Yuval #define GFT_RAM_LINE_TENANT_ID_SHIFT 9 50467b6859fbSMintz, Yuval #define GFT_RAM_LINE_RESERVED1_MASK 0x3FFFFF 50477b6859fbSMintz, Yuval #define GFT_RAM_LINE_RESERVED1_SHIFT 10 50487b6859fbSMintz, Yuval }; 50497b6859fbSMintz, Yuval 5050a2e7699eSTomer Tayar /* Used in the first 2 bits for gft_ram_line: Indication for vlan mask */ 50517b6859fbSMintz, Yuval enum gft_vlan_select { 50527b6859fbSMintz, Yuval INNER_PROVIDER_VLAN = 0, 50537b6859fbSMintz, Yuval INNER_VLAN = 1, 50547b6859fbSMintz, Yuval OUTER_PROVIDER_VLAN = 2, 50557b6859fbSMintz, Yuval OUTER_VLAN = 3, 50567b6859fbSMintz, Yuval MAX_GFT_VLAN_SELECT 50577b6859fbSMintz, Yuval }; 50587b6859fbSMintz, Yuval 5059a2e7699eSTomer Tayar /* The rdma task context of Mstorm */ 50607a9b6b8fSYuval Mintz struct ystorm_rdma_task_st_ctx { 50617a9b6b8fSYuval Mintz struct regpair temp[4]; 50627a9b6b8fSYuval Mintz }; 50637a9b6b8fSYuval Mintz 5064fb09a1edSShai Malin struct ystorm_rdma_task_ag_ctx { 50657a9b6b8fSYuval Mintz u8 reserved; 50667a9b6b8fSYuval Mintz u8 byte1; 50677a9b6b8fSYuval Mintz __le16 msem_ctx_upd_seq; 50687a9b6b8fSYuval Mintz u8 flags0; 5069fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF 5070fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 5071fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 5072fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 5073fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 5074fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 5075fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1 5076fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6 5077fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1 5078fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT 7 50797a9b6b8fSYuval Mintz u8 flags1; 5080fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 5081fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0 5082fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 5083fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2 5084fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 5085fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4 5086fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 5087fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6 5088fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 5089fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7 50907a9b6b8fSYuval Mintz u8 flags2; 5091fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 5092fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 5093fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 5094fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1 5095fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 5096fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2 5097fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 5098fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3 5099fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 5100fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4 5101fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 5102fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5 5103fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 5104fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6 5105fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 5106fb09a1edSShai Malin #define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7 51077a9b6b8fSYuval Mintz u8 key; 5108d52c89f1SMichal Kalderon __le32 mw_cnt_or_qp_id; 51097a9b6b8fSYuval Mintz u8 ref_cnt_seq; 51107a9b6b8fSYuval Mintz u8 ctx_upd_seq; 51117a9b6b8fSYuval Mintz __le16 dif_flags; 51127a9b6b8fSYuval Mintz __le16 tx_ref_count; 51137a9b6b8fSYuval Mintz __le16 last_used_ltid; 51147a9b6b8fSYuval Mintz __le16 parent_mr_lo; 51157a9b6b8fSYuval Mintz __le16 parent_mr_hi; 51167a9b6b8fSYuval Mintz __le32 fbo_lo; 51177a9b6b8fSYuval Mintz __le32 fbo_hi; 51187a9b6b8fSYuval Mintz }; 51197a9b6b8fSYuval Mintz 5120fb09a1edSShai Malin struct mstorm_rdma_task_ag_ctx { 51217a9b6b8fSYuval Mintz u8 reserved; 51227a9b6b8fSYuval Mintz u8 byte1; 51237a9b6b8fSYuval Mintz __le16 icid; 51247a9b6b8fSYuval Mintz u8 flags0; 5125fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF 5126fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 5127fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 5128fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 5129fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 5130fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 5131fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 5132fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 5133fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1 5134fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT 7 51357a9b6b8fSYuval Mintz u8 flags1; 5136fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 5137fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0 5138fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 5139fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2 5140fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 5141fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4 5142fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 5143fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6 5144fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 5145fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7 51467a9b6b8fSYuval Mintz u8 flags2; 5147fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 5148fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0 5149fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 5150fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1 5151fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 5152fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2 5153fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 5154fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3 5155fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 5156fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4 5157fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 5158fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5 5159fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 5160fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6 5161fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 5162fb09a1edSShai Malin #define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7 51637a9b6b8fSYuval Mintz u8 key; 5164d52c89f1SMichal Kalderon __le32 mw_cnt_or_qp_id; 51657a9b6b8fSYuval Mintz u8 ref_cnt_seq; 51667a9b6b8fSYuval Mintz u8 ctx_upd_seq; 51677a9b6b8fSYuval Mintz __le16 dif_flags; 51687a9b6b8fSYuval Mintz __le16 tx_ref_count; 51697a9b6b8fSYuval Mintz __le16 last_used_ltid; 51707a9b6b8fSYuval Mintz __le16 parent_mr_lo; 51717a9b6b8fSYuval Mintz __le16 parent_mr_hi; 51727a9b6b8fSYuval Mintz __le32 fbo_lo; 51737a9b6b8fSYuval Mintz __le32 fbo_hi; 51747a9b6b8fSYuval Mintz }; 51757a9b6b8fSYuval Mintz 5176a2e7699eSTomer Tayar /* The roce task context of Mstorm */ 5177a2e7699eSTomer Tayar struct mstorm_rdma_task_st_ctx { 5178a2e7699eSTomer Tayar struct regpair temp[4]; 5179a2e7699eSTomer Tayar }; 5180a2e7699eSTomer Tayar 51810500a70dSMichal Kalderon /* The roce task context of Ustorm */ 51820500a70dSMichal Kalderon struct ustorm_rdma_task_st_ctx { 51830500a70dSMichal Kalderon struct regpair temp[6]; 51840500a70dSMichal Kalderon }; 51850500a70dSMichal Kalderon 5186fb09a1edSShai Malin struct ustorm_rdma_task_ag_ctx { 51877a9b6b8fSYuval Mintz u8 reserved; 518850bc60cbSMichal Kalderon u8 state; 51897a9b6b8fSYuval Mintz __le16 icid; 51907a9b6b8fSYuval Mintz u8 flags0; 5191fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF 5192fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 5193fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 5194fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 5195fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 5196fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 5197fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3 5198fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6 51997a9b6b8fSYuval Mintz u8 flags1; 5200fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3 5201fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0 5202fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3 5203fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2 5204fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_DIF_BLOCK_SIZE_MASK 0x3 5205fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_DIF_BLOCK_SIZE_SHIFT 4 5206fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 5207fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6 52087a9b6b8fSYuval Mintz u8 flags2; 5209fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1 5210fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0 5211fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1 5212fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1 5213fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1 5214fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2 5215fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_RESERVED4_MASK 0x1 5216fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_RESERVED4_SHIFT 3 5217fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 5218fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4 5219fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 5220fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5 5221fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 5222fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6 5223fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 5224fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7 52257a9b6b8fSYuval Mintz u8 flags3; 5226fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_DIF_RXMIT_PROD_CONS_EN_MASK 0x1 5227fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_DIF_RXMIT_PROD_CONS_EN_SHIFT 0 5228fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 5229fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1 5230fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_PROD_CONS_EN_MASK 0x1 5231fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_PROD_CONS_EN_SHIFT 2 5232fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 5233fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3 5234fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF 5235fb09a1edSShai Malin #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4 52367a9b6b8fSYuval Mintz __le32 dif_err_intervals; 52377a9b6b8fSYuval Mintz __le32 dif_error_1st_interval; 52380500a70dSMichal Kalderon __le32 dif_rxmit_cons; 52390500a70dSMichal Kalderon __le32 dif_rxmit_prod; 524050bc60cbSMichal Kalderon __le32 sge_index; 52410500a70dSMichal Kalderon __le32 sq_cons; 524250bc60cbSMichal Kalderon u8 byte2; 524350bc60cbSMichal Kalderon u8 byte3; 52440500a70dSMichal Kalderon __le16 dif_write_cons; 52450500a70dSMichal Kalderon __le16 dif_write_prod; 524650bc60cbSMichal Kalderon __le16 word3; 52470500a70dSMichal Kalderon __le32 dif_error_buffer_address_lo; 52480500a70dSMichal Kalderon __le32 dif_error_buffer_address_hi; 52497a9b6b8fSYuval Mintz }; 52507a9b6b8fSYuval Mintz 5251a2e7699eSTomer Tayar /* RDMA task context */ 5252fb09a1edSShai Malin struct rdma_task_context { 52537a9b6b8fSYuval Mintz struct ystorm_rdma_task_st_ctx ystorm_st_context; 5254fb09a1edSShai Malin struct ystorm_rdma_task_ag_ctx ystorm_ag_context; 52557a9b6b8fSYuval Mintz struct tdif_task_context tdif_context; 5256fb09a1edSShai Malin struct mstorm_rdma_task_ag_ctx mstorm_ag_context; 52577a9b6b8fSYuval Mintz struct mstorm_rdma_task_st_ctx mstorm_st_context; 52587a9b6b8fSYuval Mintz struct rdif_task_context rdif_context; 52590500a70dSMichal Kalderon struct ustorm_rdma_task_st_ctx ustorm_st_context; 52600500a70dSMichal Kalderon struct regpair ustorm_st_padding[2]; 5261fb09a1edSShai Malin struct ustorm_rdma_task_ag_ctx ustorm_ag_context; 52627a9b6b8fSYuval Mintz }; 52637a9b6b8fSYuval Mintz 5264fe40a830SPrabhakar Kushwaha #define TOE_MAX_RAMROD_PER_PF 8 5265fe40a830SPrabhakar Kushwaha #define TOE_TX_PAGE_SIZE_BYTES 4096 5266fe40a830SPrabhakar Kushwaha #define TOE_GRQ_PAGE_SIZE_BYTES 4096 5267fe40a830SPrabhakar Kushwaha #define TOE_RX_CQ_PAGE_SIZE_BYTES 4096 5268fe40a830SPrabhakar Kushwaha 5269fe40a830SPrabhakar Kushwaha #define TOE_RX_MAX_RSS_CHAINS 64 5270fe40a830SPrabhakar Kushwaha #define TOE_TX_MAX_TSS_CHAINS 64 5271fe40a830SPrabhakar Kushwaha #define TOE_RSS_INDIRECTION_TABLE_SIZE 128 5272fe40a830SPrabhakar Kushwaha 5273fe40a830SPrabhakar Kushwaha /* The toe storm context of Mstorm */ 5274fe40a830SPrabhakar Kushwaha struct mstorm_toe_conn_st_ctx { 5275fe40a830SPrabhakar Kushwaha __le32 reserved[24]; 5276fe40a830SPrabhakar Kushwaha }; 5277fe40a830SPrabhakar Kushwaha 5278fe40a830SPrabhakar Kushwaha /* The toe storm context of Pstorm */ 5279fe40a830SPrabhakar Kushwaha struct pstorm_toe_conn_st_ctx { 5280fe40a830SPrabhakar Kushwaha __le32 reserved[36]; 5281fe40a830SPrabhakar Kushwaha }; 5282fe40a830SPrabhakar Kushwaha 5283fe40a830SPrabhakar Kushwaha /* The toe storm context of Ystorm */ 5284fe40a830SPrabhakar Kushwaha struct ystorm_toe_conn_st_ctx { 5285fe40a830SPrabhakar Kushwaha __le32 reserved[8]; 5286fe40a830SPrabhakar Kushwaha }; 5287fe40a830SPrabhakar Kushwaha 5288fe40a830SPrabhakar Kushwaha /* The toe storm context of Xstorm */ 5289fe40a830SPrabhakar Kushwaha struct xstorm_toe_conn_st_ctx { 5290fe40a830SPrabhakar Kushwaha __le32 reserved[44]; 5291fe40a830SPrabhakar Kushwaha }; 5292fe40a830SPrabhakar Kushwaha 5293fe40a830SPrabhakar Kushwaha struct ystorm_toe_conn_ag_ctx { 5294fe40a830SPrabhakar Kushwaha u8 byte0; 5295fe40a830SPrabhakar Kushwaha u8 byte1; 5296fe40a830SPrabhakar Kushwaha u8 flags0; 5297fe40a830SPrabhakar Kushwaha #define YSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 5298fe40a830SPrabhakar Kushwaha #define YSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 5299fe40a830SPrabhakar Kushwaha #define YSTORM_TOE_CONN_AG_CTX_BIT1_MASK 0x1 5300fe40a830SPrabhakar Kushwaha #define YSTORM_TOE_CONN_AG_CTX_BIT1_SHIFT 1 5301fe40a830SPrabhakar Kushwaha #define YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_MASK 0x3 5302fe40a830SPrabhakar Kushwaha #define YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_SHIFT 2 5303fe40a830SPrabhakar Kushwaha #define YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_MASK 0x3 5304fe40a830SPrabhakar Kushwaha #define YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_SHIFT 4 5305fe40a830SPrabhakar Kushwaha #define YSTORM_TOE_CONN_AG_CTX_CF2_MASK 0x3 5306fe40a830SPrabhakar Kushwaha #define YSTORM_TOE_CONN_AG_CTX_CF2_SHIFT 6 5307fe40a830SPrabhakar Kushwaha u8 flags1; 5308fe40a830SPrabhakar Kushwaha #define YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_MASK 0x1 5309fe40a830SPrabhakar Kushwaha #define YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_SHIFT 0 5310fe40a830SPrabhakar Kushwaha #define YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_EN_MASK 0x1 5311fe40a830SPrabhakar Kushwaha #define YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_EN_SHIFT 1 5312fe40a830SPrabhakar Kushwaha #define YSTORM_TOE_CONN_AG_CTX_CF2EN_MASK 0x1 5313fe40a830SPrabhakar Kushwaha #define YSTORM_TOE_CONN_AG_CTX_CF2EN_SHIFT 2 5314fe40a830SPrabhakar Kushwaha #define YSTORM_TOE_CONN_AG_CTX_REL_SEQ_EN_MASK 0x1 5315fe40a830SPrabhakar Kushwaha #define YSTORM_TOE_CONN_AG_CTX_REL_SEQ_EN_SHIFT 3 5316fe40a830SPrabhakar Kushwaha #define YSTORM_TOE_CONN_AG_CTX_RULE1EN_MASK 0x1 5317fe40a830SPrabhakar Kushwaha #define YSTORM_TOE_CONN_AG_CTX_RULE1EN_SHIFT 4 5318fe40a830SPrabhakar Kushwaha #define YSTORM_TOE_CONN_AG_CTX_RULE2EN_MASK 0x1 5319fe40a830SPrabhakar Kushwaha #define YSTORM_TOE_CONN_AG_CTX_RULE2EN_SHIFT 5 5320fe40a830SPrabhakar Kushwaha #define YSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK 0x1 5321fe40a830SPrabhakar Kushwaha #define YSTORM_TOE_CONN_AG_CTX_RULE3EN_SHIFT 6 5322fe40a830SPrabhakar Kushwaha #define YSTORM_TOE_CONN_AG_CTX_CONS_PROD_EN_MASK 0x1 5323fe40a830SPrabhakar Kushwaha #define YSTORM_TOE_CONN_AG_CTX_CONS_PROD_EN_SHIFT 7 5324fe40a830SPrabhakar Kushwaha u8 completion_opcode; 5325fe40a830SPrabhakar Kushwaha u8 byte3; 5326fe40a830SPrabhakar Kushwaha __le16 word0; 5327fe40a830SPrabhakar Kushwaha __le32 rel_seq; 5328fe40a830SPrabhakar Kushwaha __le32 rel_seq_threshold; 5329fe40a830SPrabhakar Kushwaha __le16 app_prod; 5330fe40a830SPrabhakar Kushwaha __le16 app_cons; 5331fe40a830SPrabhakar Kushwaha __le16 word3; 5332fe40a830SPrabhakar Kushwaha __le16 word4; 5333fe40a830SPrabhakar Kushwaha __le32 reg2; 5334fe40a830SPrabhakar Kushwaha __le32 reg3; 5335fe40a830SPrabhakar Kushwaha }; 5336fe40a830SPrabhakar Kushwaha 5337fe40a830SPrabhakar Kushwaha struct xstorm_toe_conn_ag_ctx { 5338fe40a830SPrabhakar Kushwaha u8 reserved0; 5339fe40a830SPrabhakar Kushwaha u8 state; 5340fe40a830SPrabhakar Kushwaha u8 flags0; 5341fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 5342fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 5343fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1 5344fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1 5345fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RESERVED1_MASK 0x1 5346fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RESERVED1_SHIFT 2 5347fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 5348fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 5349fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_TX_DEC_RULE_RES_MASK 0x1 5350fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_TX_DEC_RULE_RES_SHIFT 4 5351fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RESERVED2_MASK 0x1 5352fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RESERVED2_SHIFT 5 5353fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT6_MASK 0x1 5354fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT6_SHIFT 6 5355fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT7_MASK 0x1 5356fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT7_SHIFT 7 5357fe40a830SPrabhakar Kushwaha u8 flags1; 5358fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT8_MASK 0x1 5359fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT8_SHIFT 0 5360fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT9_MASK 0x1 5361fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT9_SHIFT 1 5362fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT10_MASK 0x1 5363fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT10_SHIFT 2 5364fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT11_MASK 0x1 5365fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT11_SHIFT 3 5366fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT12_MASK 0x1 5367fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT12_SHIFT 4 5368fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT13_MASK 0x1 5369fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT13_SHIFT 5 5370fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT14_MASK 0x1 5371fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT14_SHIFT 6 5372fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT15_MASK 0x1 5373fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT15_SHIFT 7 5374fe40a830SPrabhakar Kushwaha u8 flags2; 5375fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF0_MASK 0x3 5376fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF0_SHIFT 0 5377fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF1_MASK 0x3 5378fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF1_SHIFT 2 5379fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF2_MASK 0x3 5380fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF2_SHIFT 4 5381fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 5382fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6 5383fe40a830SPrabhakar Kushwaha u8 flags3; 5384fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF4_MASK 0x3 5385fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF4_SHIFT 0 5386fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF5_MASK 0x3 5387fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF5_SHIFT 2 5388fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF6_MASK 0x3 5389fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF6_SHIFT 4 5390fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF7_MASK 0x3 5391fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF7_SHIFT 6 5392fe40a830SPrabhakar Kushwaha u8 flags4; 5393fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF8_MASK 0x3 5394fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF8_SHIFT 0 5395fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF9_MASK 0x3 5396fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF9_SHIFT 2 5397fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF10_MASK 0x3 5398fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF10_SHIFT 4 5399fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF11_MASK 0x3 5400fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF11_SHIFT 6 5401fe40a830SPrabhakar Kushwaha u8 flags5; 5402fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF12_MASK 0x3 5403fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF12_SHIFT 0 5404fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF13_MASK 0x3 5405fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF13_SHIFT 2 5406fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF14_MASK 0x3 5407fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF14_SHIFT 4 5408fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF15_MASK 0x3 5409fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF15_SHIFT 6 5410fe40a830SPrabhakar Kushwaha u8 flags6; 5411fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF16_MASK 0x3 5412fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF16_SHIFT 0 5413fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF17_MASK 0x3 5414fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF17_SHIFT 2 5415fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF18_MASK 0x3 5416fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF18_SHIFT 4 5417fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_MASK 0x3 5418fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_SHIFT 6 5419fe40a830SPrabhakar Kushwaha u8 flags7; 5420fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 5421fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 5422fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_MASK 0x3 5423fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_SHIFT 2 5424fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 5425fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 5426fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF0EN_MASK 0x1 5427fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF0EN_SHIFT 6 5428fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF1EN_MASK 0x1 5429fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF1EN_SHIFT 7 5430fe40a830SPrabhakar Kushwaha u8 flags8; 5431fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF2EN_MASK 0x1 5432fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF2EN_SHIFT 0 5433fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 5434fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1 5435fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF4EN_MASK 0x1 5436fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF4EN_SHIFT 2 5437fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF5EN_MASK 0x1 5438fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF5EN_SHIFT 3 5439fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF6EN_MASK 0x1 5440fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF6EN_SHIFT 4 5441fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF7EN_MASK 0x1 5442fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF7EN_SHIFT 5 5443fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF8EN_MASK 0x1 5444fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF8EN_SHIFT 6 5445fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF9EN_MASK 0x1 5446fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF9EN_SHIFT 7 5447fe40a830SPrabhakar Kushwaha u8 flags9; 5448fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF10EN_MASK 0x1 5449fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF10EN_SHIFT 0 5450fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF11EN_MASK 0x1 5451fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF11EN_SHIFT 1 5452fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF12EN_MASK 0x1 5453fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF12EN_SHIFT 2 5454fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF13EN_MASK 0x1 5455fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF13EN_SHIFT 3 5456fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF14EN_MASK 0x1 5457fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF14EN_SHIFT 4 5458fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF15EN_MASK 0x1 5459fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF15EN_SHIFT 5 5460fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF16EN_MASK 0x1 5461fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF16EN_SHIFT 6 5462fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF17EN_MASK 0x1 5463fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF17EN_SHIFT 7 5464fe40a830SPrabhakar Kushwaha u8 flags10; 5465fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF18EN_MASK 0x1 5466fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF18EN_SHIFT 0 5467fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1 5468fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1 5469fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 5470fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 5471fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1 5472fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT 3 5473fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 5474fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 5475fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF23EN_MASK 0x1 5476fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF23EN_SHIFT 5 5477fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RULE0EN_MASK 0x1 5478fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RULE0EN_SHIFT 6 5479fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1 5480fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT 7 5481fe40a830SPrabhakar Kushwaha u8 flags11; 5482fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1 5483fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0 5484fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK 0x1 5485fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RULE3EN_SHIFT 1 5486fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RESERVED3_MASK 0x1 5487fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RESERVED3_SHIFT 2 5488fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RULE5EN_MASK 0x1 5489fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RULE5EN_SHIFT 3 5490fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RULE6EN_MASK 0x1 5491fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RULE6EN_SHIFT 4 5492fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RULE7EN_MASK 0x1 5493fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RULE7EN_SHIFT 5 5494fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 5495fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 5496fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RULE9EN_MASK 0x1 5497fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RULE9EN_SHIFT 7 5498fe40a830SPrabhakar Kushwaha u8 flags12; 5499fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RULE10EN_MASK 0x1 5500fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RULE10EN_SHIFT 0 5501fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RULE11EN_MASK 0x1 5502fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RULE11EN_SHIFT 1 5503fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 5504fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 5505fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 5506fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 5507fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RULE14EN_MASK 0x1 5508fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RULE14EN_SHIFT 4 5509fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RULE15EN_MASK 0x1 5510fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RULE15EN_SHIFT 5 5511fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RULE16EN_MASK 0x1 5512fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RULE16EN_SHIFT 6 5513fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RULE17EN_MASK 0x1 5514fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RULE17EN_SHIFT 7 5515fe40a830SPrabhakar Kushwaha u8 flags13; 5516fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RULE18EN_MASK 0x1 5517fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RULE18EN_SHIFT 0 5518fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RULE19EN_MASK 0x1 5519fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_RULE19EN_SHIFT 1 5520fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 5521fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 5522fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 5523fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 5524fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 5525fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 5526fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 5527fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 5528fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 5529fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 5530fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 5531fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 5532fe40a830SPrabhakar Kushwaha u8 flags14; 5533fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT16_MASK 0x1 5534fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT16_SHIFT 0 5535fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT17_MASK 0x1 5536fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT17_SHIFT 1 5537fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT18_MASK 0x1 5538fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT18_SHIFT 2 5539fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT19_MASK 0x1 5540fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT19_SHIFT 3 5541fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT20_MASK 0x1 5542fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT20_SHIFT 4 5543fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT21_MASK 0x1 5544fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_BIT21_SHIFT 5 5545fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF23_MASK 0x3 5546fe40a830SPrabhakar Kushwaha #define XSTORM_TOE_CONN_AG_CTX_CF23_SHIFT 6 5547fe40a830SPrabhakar Kushwaha u8 byte2; 5548fe40a830SPrabhakar Kushwaha __le16 physical_q0; 5549fe40a830SPrabhakar Kushwaha __le16 physical_q1; 5550fe40a830SPrabhakar Kushwaha __le16 word2; 5551fe40a830SPrabhakar Kushwaha __le16 word3; 5552fe40a830SPrabhakar Kushwaha __le16 bd_prod; 5553fe40a830SPrabhakar Kushwaha __le16 word5; 5554fe40a830SPrabhakar Kushwaha __le16 word6; 5555fe40a830SPrabhakar Kushwaha u8 byte3; 5556fe40a830SPrabhakar Kushwaha u8 byte4; 5557fe40a830SPrabhakar Kushwaha u8 byte5; 5558fe40a830SPrabhakar Kushwaha u8 byte6; 5559fe40a830SPrabhakar Kushwaha __le32 reg0; 5560fe40a830SPrabhakar Kushwaha __le32 reg1; 5561fe40a830SPrabhakar Kushwaha __le32 reg2; 5562fe40a830SPrabhakar Kushwaha __le32 more_to_send_seq; 5563fe40a830SPrabhakar Kushwaha __le32 local_adv_wnd_seq; 5564fe40a830SPrabhakar Kushwaha __le32 reg5; 5565fe40a830SPrabhakar Kushwaha __le32 reg6; 5566fe40a830SPrabhakar Kushwaha __le16 word7; 5567fe40a830SPrabhakar Kushwaha __le16 word8; 5568fe40a830SPrabhakar Kushwaha __le16 word9; 5569fe40a830SPrabhakar Kushwaha __le16 word10; 5570fe40a830SPrabhakar Kushwaha __le32 reg7; 5571fe40a830SPrabhakar Kushwaha __le32 reg8; 5572fe40a830SPrabhakar Kushwaha __le32 reg9; 5573fe40a830SPrabhakar Kushwaha u8 byte7; 5574fe40a830SPrabhakar Kushwaha u8 byte8; 5575fe40a830SPrabhakar Kushwaha u8 byte9; 5576fe40a830SPrabhakar Kushwaha u8 byte10; 5577fe40a830SPrabhakar Kushwaha u8 byte11; 5578fe40a830SPrabhakar Kushwaha u8 byte12; 5579fe40a830SPrabhakar Kushwaha u8 byte13; 5580fe40a830SPrabhakar Kushwaha u8 byte14; 5581fe40a830SPrabhakar Kushwaha u8 byte15; 5582fe40a830SPrabhakar Kushwaha u8 e5_reserved; 5583fe40a830SPrabhakar Kushwaha __le16 word11; 5584fe40a830SPrabhakar Kushwaha __le32 reg10; 5585fe40a830SPrabhakar Kushwaha __le32 reg11; 5586fe40a830SPrabhakar Kushwaha __le32 reg12; 5587fe40a830SPrabhakar Kushwaha __le32 reg13; 5588fe40a830SPrabhakar Kushwaha __le32 reg14; 5589fe40a830SPrabhakar Kushwaha __le32 reg15; 5590fe40a830SPrabhakar Kushwaha __le32 reg16; 5591fe40a830SPrabhakar Kushwaha __le32 reg17; 5592fe40a830SPrabhakar Kushwaha }; 5593fe40a830SPrabhakar Kushwaha 5594fe40a830SPrabhakar Kushwaha struct tstorm_toe_conn_ag_ctx { 5595fe40a830SPrabhakar Kushwaha u8 reserved0; 5596fe40a830SPrabhakar Kushwaha u8 byte1; 5597fe40a830SPrabhakar Kushwaha u8 flags0; 5598fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 5599fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 5600fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_BIT1_MASK 0x1 5601fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_BIT1_SHIFT 1 5602fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_BIT2_MASK 0x1 5603fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_BIT2_SHIFT 2 5604fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_BIT3_MASK 0x1 5605fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_BIT3_SHIFT 3 5606fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_BIT4_MASK 0x1 5607fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_BIT4_SHIFT 4 5608fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_BIT5_MASK 0x1 5609fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_BIT5_SHIFT 5 5610fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_MASK 0x3 5611fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_SHIFT 6 5612fe40a830SPrabhakar Kushwaha u8 flags1; 5613fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF1_MASK 0x3 5614fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF1_SHIFT 0 5615fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF2_MASK 0x3 5616fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF2_SHIFT 2 5617fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 5618fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4 5619fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF4_MASK 0x3 5620fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF4_SHIFT 6 5621fe40a830SPrabhakar Kushwaha u8 flags2; 5622fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF5_MASK 0x3 5623fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF5_SHIFT 0 5624fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF6_MASK 0x3 5625fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF6_SHIFT 2 5626fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF7_MASK 0x3 5627fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF7_SHIFT 4 5628fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF8_MASK 0x3 5629fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF8_SHIFT 6 5630fe40a830SPrabhakar Kushwaha u8 flags3; 5631fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 5632fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 5633fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF10_MASK 0x3 5634fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF10_SHIFT 2 5635fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_EN_MASK 0x1 5636fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_EN_SHIFT 4 5637fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF1EN_MASK 0x1 5638fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF1EN_SHIFT 5 5639fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF2EN_MASK 0x1 5640fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF2EN_SHIFT 6 5641fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 5642fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7 5643fe40a830SPrabhakar Kushwaha u8 flags4; 5644fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF4EN_MASK 0x1 5645fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF4EN_SHIFT 0 5646fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF5EN_MASK 0x1 5647fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF5EN_SHIFT 1 5648fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF6EN_MASK 0x1 5649fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF6EN_SHIFT 2 5650fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF7EN_MASK 0x1 5651fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF7EN_SHIFT 3 5652fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF8EN_MASK 0x1 5653fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF8EN_SHIFT 4 5654fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 5655fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5 5656fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF10EN_MASK 0x1 5657fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_CF10EN_SHIFT 6 5658fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_RULE0EN_MASK 0x1 5659fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_RULE0EN_SHIFT 7 5660fe40a830SPrabhakar Kushwaha u8 flags5; 5661fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_RULE1EN_MASK 0x1 5662fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_RULE1EN_SHIFT 0 5663fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_RULE2EN_MASK 0x1 5664fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_RULE2EN_SHIFT 1 5665fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK 0x1 5666fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_RULE3EN_SHIFT 2 5667fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_RULE4EN_MASK 0x1 5668fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_RULE4EN_SHIFT 3 5669fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_RULE5EN_MASK 0x1 5670fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_RULE5EN_SHIFT 4 5671fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_RULE6EN_MASK 0x1 5672fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_RULE6EN_SHIFT 5 5673fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_RULE7EN_MASK 0x1 5674fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_RULE7EN_SHIFT 6 5675fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_RULE8EN_MASK 0x1 5676fe40a830SPrabhakar Kushwaha #define TSTORM_TOE_CONN_AG_CTX_RULE8EN_SHIFT 7 5677fe40a830SPrabhakar Kushwaha __le32 reg0; 5678fe40a830SPrabhakar Kushwaha __le32 reg1; 5679fe40a830SPrabhakar Kushwaha __le32 reg2; 5680fe40a830SPrabhakar Kushwaha __le32 reg3; 5681fe40a830SPrabhakar Kushwaha __le32 reg4; 5682fe40a830SPrabhakar Kushwaha __le32 reg5; 5683fe40a830SPrabhakar Kushwaha __le32 reg6; 5684fe40a830SPrabhakar Kushwaha __le32 reg7; 5685fe40a830SPrabhakar Kushwaha __le32 reg8; 5686fe40a830SPrabhakar Kushwaha u8 byte2; 5687fe40a830SPrabhakar Kushwaha u8 byte3; 5688fe40a830SPrabhakar Kushwaha __le16 word0; 5689fe40a830SPrabhakar Kushwaha }; 5690fe40a830SPrabhakar Kushwaha 5691fe40a830SPrabhakar Kushwaha struct ustorm_toe_conn_ag_ctx { 5692fe40a830SPrabhakar Kushwaha u8 reserved; 5693fe40a830SPrabhakar Kushwaha u8 byte1; 5694fe40a830SPrabhakar Kushwaha u8 flags0; 5695fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 5696fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 5697fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_BIT1_MASK 0x1 5698fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_BIT1_SHIFT 1 5699fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_CF0_MASK 0x3 5700fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_CF0_SHIFT 2 5701fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_CF1_MASK 0x3 5702fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_CF1_SHIFT 4 5703fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_MASK 0x3 5704fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_SHIFT 6 5705fe40a830SPrabhakar Kushwaha u8 flags1; 5706fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 5707fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 0 5708fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_MASK 0x3 5709fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_SHIFT 2 5710fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_DQ_CF_MASK 0x3 5711fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_DQ_CF_SHIFT 4 5712fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_CF6_MASK 0x3 5713fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_CF6_SHIFT 6 5714fe40a830SPrabhakar Kushwaha u8 flags2; 5715fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_CF0EN_MASK 0x1 5716fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_CF0EN_SHIFT 0 5717fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_CF1EN_MASK 0x1 5718fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_CF1EN_SHIFT 1 5719fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_EN_MASK 0x1 5720fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_EN_SHIFT 2 5721fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 5722fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 3 5723fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_MASK 0x1 5724fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_SHIFT 4 5725fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 5726fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_DQ_CF_EN_SHIFT 5 5727fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_CF6EN_MASK 0x1 5728fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_CF6EN_SHIFT 6 5729fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_RULE0EN_MASK 0x1 5730fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_RULE0EN_SHIFT 7 5731fe40a830SPrabhakar Kushwaha u8 flags3; 5732fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_RULE1EN_MASK 0x1 5733fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_RULE1EN_SHIFT 0 5734fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_RULE2EN_MASK 0x1 5735fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_RULE2EN_SHIFT 1 5736fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_RULE3EN_MASK 0x1 5737fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_RULE3EN_SHIFT 2 5738fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_RULE4EN_MASK 0x1 5739fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_RULE4EN_SHIFT 3 5740fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_RULE5EN_MASK 0x1 5741fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_RULE5EN_SHIFT 4 5742fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_RULE6EN_MASK 0x1 5743fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_RULE6EN_SHIFT 5 5744fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_RULE7EN_MASK 0x1 5745fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_RULE7EN_SHIFT 6 5746fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_RULE8EN_MASK 0x1 5747fe40a830SPrabhakar Kushwaha #define USTORM_TOE_CONN_AG_CTX_RULE8EN_SHIFT 7 5748fe40a830SPrabhakar Kushwaha u8 byte2; 5749fe40a830SPrabhakar Kushwaha u8 byte3; 5750fe40a830SPrabhakar Kushwaha __le16 word0; 5751fe40a830SPrabhakar Kushwaha __le16 word1; 5752fe40a830SPrabhakar Kushwaha __le32 reg0; 5753fe40a830SPrabhakar Kushwaha __le32 reg1; 5754fe40a830SPrabhakar Kushwaha __le32 reg2; 5755fe40a830SPrabhakar Kushwaha __le32 reg3; 5756fe40a830SPrabhakar Kushwaha __le16 word2; 5757fe40a830SPrabhakar Kushwaha __le16 word3; 5758fe40a830SPrabhakar Kushwaha }; 5759fe40a830SPrabhakar Kushwaha 5760fe40a830SPrabhakar Kushwaha /* The toe storm context of Tstorm */ 5761fe40a830SPrabhakar Kushwaha struct tstorm_toe_conn_st_ctx { 5762fe40a830SPrabhakar Kushwaha __le32 reserved[16]; 5763fe40a830SPrabhakar Kushwaha }; 5764fe40a830SPrabhakar Kushwaha 5765fe40a830SPrabhakar Kushwaha /* The toe storm context of Ustorm */ 5766fe40a830SPrabhakar Kushwaha struct ustorm_toe_conn_st_ctx { 5767fe40a830SPrabhakar Kushwaha __le32 reserved[52]; 5768fe40a830SPrabhakar Kushwaha }; 5769fe40a830SPrabhakar Kushwaha 5770fe40a830SPrabhakar Kushwaha /* toe connection context */ 5771fe40a830SPrabhakar Kushwaha struct toe_conn_context { 5772fe40a830SPrabhakar Kushwaha struct ystorm_toe_conn_st_ctx ystorm_st_context; 5773fe40a830SPrabhakar Kushwaha struct pstorm_toe_conn_st_ctx pstorm_st_context; 5774fe40a830SPrabhakar Kushwaha struct regpair pstorm_st_padding[2]; 5775fe40a830SPrabhakar Kushwaha struct xstorm_toe_conn_st_ctx xstorm_st_context; 5776fe40a830SPrabhakar Kushwaha struct regpair xstorm_st_padding[2]; 5777fe40a830SPrabhakar Kushwaha struct ystorm_toe_conn_ag_ctx ystorm_ag_context; 5778fe40a830SPrabhakar Kushwaha struct xstorm_toe_conn_ag_ctx xstorm_ag_context; 5779fe40a830SPrabhakar Kushwaha struct tstorm_toe_conn_ag_ctx tstorm_ag_context; 5780fe40a830SPrabhakar Kushwaha struct regpair tstorm_ag_padding[2]; 5781fe40a830SPrabhakar Kushwaha struct timers_context timer_context; 5782fe40a830SPrabhakar Kushwaha struct ustorm_toe_conn_ag_ctx ustorm_ag_context; 5783fe40a830SPrabhakar Kushwaha struct tstorm_toe_conn_st_ctx tstorm_st_context; 5784fe40a830SPrabhakar Kushwaha struct mstorm_toe_conn_st_ctx mstorm_st_context; 5785fe40a830SPrabhakar Kushwaha struct ustorm_toe_conn_st_ctx ustorm_st_context; 5786fe40a830SPrabhakar Kushwaha }; 5787fe40a830SPrabhakar Kushwaha 5788fe40a830SPrabhakar Kushwaha /* toe init ramrod header */ 5789fe40a830SPrabhakar Kushwaha struct toe_init_ramrod_header { 5790fe40a830SPrabhakar Kushwaha u8 first_rss; 5791fe40a830SPrabhakar Kushwaha u8 num_rss; 5792fe40a830SPrabhakar Kushwaha u8 reserved[6]; 5793fe40a830SPrabhakar Kushwaha }; 5794fe40a830SPrabhakar Kushwaha 5795fe40a830SPrabhakar Kushwaha /* toe pf init parameters */ 5796fe40a830SPrabhakar Kushwaha struct toe_pf_init_params { 5797fe40a830SPrabhakar Kushwaha __le32 push_timeout; 5798fe40a830SPrabhakar Kushwaha __le16 grq_buffer_size; 5799fe40a830SPrabhakar Kushwaha __le16 grq_sb_id; 5800fe40a830SPrabhakar Kushwaha u8 grq_sb_index; 5801fe40a830SPrabhakar Kushwaha u8 max_seg_retransmit; 5802fe40a830SPrabhakar Kushwaha u8 doubt_reachability; 5803fe40a830SPrabhakar Kushwaha u8 ll2_rx_queue_id; 5804fe40a830SPrabhakar Kushwaha __le16 grq_fetch_threshold; 5805fe40a830SPrabhakar Kushwaha u8 reserved1[2]; 5806fe40a830SPrabhakar Kushwaha struct regpair grq_page_addr; 5807fe40a830SPrabhakar Kushwaha }; 5808fe40a830SPrabhakar Kushwaha 5809fe40a830SPrabhakar Kushwaha /* toe tss parameters */ 5810fe40a830SPrabhakar Kushwaha struct toe_tss_params { 5811fe40a830SPrabhakar Kushwaha struct regpair curr_page_addr; 5812fe40a830SPrabhakar Kushwaha struct regpair next_page_addr; 5813fe40a830SPrabhakar Kushwaha u8 reserved0; 5814fe40a830SPrabhakar Kushwaha u8 status_block_index; 5815fe40a830SPrabhakar Kushwaha __le16 status_block_id; 5816fe40a830SPrabhakar Kushwaha __le16 reserved1[2]; 5817fe40a830SPrabhakar Kushwaha }; 5818fe40a830SPrabhakar Kushwaha 5819fe40a830SPrabhakar Kushwaha /* toe rss parameters */ 5820fe40a830SPrabhakar Kushwaha struct toe_rss_params { 5821fe40a830SPrabhakar Kushwaha struct regpair curr_page_addr; 5822fe40a830SPrabhakar Kushwaha struct regpair next_page_addr; 5823fe40a830SPrabhakar Kushwaha u8 reserved0; 5824fe40a830SPrabhakar Kushwaha u8 status_block_index; 5825fe40a830SPrabhakar Kushwaha __le16 status_block_id; 5826fe40a830SPrabhakar Kushwaha __le16 reserved1[2]; 5827fe40a830SPrabhakar Kushwaha }; 5828fe40a830SPrabhakar Kushwaha 5829fe40a830SPrabhakar Kushwaha /* toe init ramrod data */ 5830fe40a830SPrabhakar Kushwaha struct toe_init_ramrod_data { 5831fe40a830SPrabhakar Kushwaha struct toe_init_ramrod_header hdr; 5832fe40a830SPrabhakar Kushwaha struct tcp_init_params tcp_params; 5833fe40a830SPrabhakar Kushwaha struct toe_pf_init_params pf_params; 5834fe40a830SPrabhakar Kushwaha struct toe_tss_params tss_params[TOE_TX_MAX_TSS_CHAINS]; 5835fe40a830SPrabhakar Kushwaha struct toe_rss_params rss_params[TOE_RX_MAX_RSS_CHAINS]; 5836fe40a830SPrabhakar Kushwaha }; 5837fe40a830SPrabhakar Kushwaha 5838fe40a830SPrabhakar Kushwaha /* toe offload parameters */ 5839fe40a830SPrabhakar Kushwaha struct toe_offload_params { 5840fe40a830SPrabhakar Kushwaha struct regpair tx_bd_page_addr; 5841fe40a830SPrabhakar Kushwaha struct regpair tx_app_page_addr; 5842fe40a830SPrabhakar Kushwaha __le32 more_to_send_seq; 5843fe40a830SPrabhakar Kushwaha __le16 rcv_indication_size; 5844fe40a830SPrabhakar Kushwaha u8 rss_tss_id; 5845fe40a830SPrabhakar Kushwaha u8 ignore_grq_push; 5846fe40a830SPrabhakar Kushwaha struct regpair rx_db_data_ptr; 5847fe40a830SPrabhakar Kushwaha }; 5848fe40a830SPrabhakar Kushwaha 5849fe40a830SPrabhakar Kushwaha /* TOE offload ramrod data - DMAed by firmware */ 5850fe40a830SPrabhakar Kushwaha struct toe_offload_ramrod_data { 5851fe40a830SPrabhakar Kushwaha struct tcp_offload_params tcp_ofld_params; 5852fe40a830SPrabhakar Kushwaha struct toe_offload_params toe_ofld_params; 5853fe40a830SPrabhakar Kushwaha }; 5854fe40a830SPrabhakar Kushwaha 5855fe40a830SPrabhakar Kushwaha /* TOE ramrod command IDs */ 5856fe40a830SPrabhakar Kushwaha enum toe_ramrod_cmd_id { 5857fe40a830SPrabhakar Kushwaha TOE_RAMROD_UNUSED, 5858fe40a830SPrabhakar Kushwaha TOE_RAMROD_FUNC_INIT, 5859fe40a830SPrabhakar Kushwaha TOE_RAMROD_INITATE_OFFLOAD, 5860fe40a830SPrabhakar Kushwaha TOE_RAMROD_FUNC_CLOSE, 5861fe40a830SPrabhakar Kushwaha TOE_RAMROD_SEARCHER_DELETE, 5862fe40a830SPrabhakar Kushwaha TOE_RAMROD_TERMINATE, 5863fe40a830SPrabhakar Kushwaha TOE_RAMROD_QUERY, 5864fe40a830SPrabhakar Kushwaha TOE_RAMROD_UPDATE, 5865fe40a830SPrabhakar Kushwaha TOE_RAMROD_EMPTY, 5866fe40a830SPrabhakar Kushwaha TOE_RAMROD_RESET_SEND, 5867fe40a830SPrabhakar Kushwaha TOE_RAMROD_INVALIDATE, 5868fe40a830SPrabhakar Kushwaha MAX_TOE_RAMROD_CMD_ID 5869fe40a830SPrabhakar Kushwaha }; 5870fe40a830SPrabhakar Kushwaha 5871fe40a830SPrabhakar Kushwaha /* Toe RQ buffer descriptor */ 5872fe40a830SPrabhakar Kushwaha struct toe_rx_bd { 5873fe40a830SPrabhakar Kushwaha struct regpair addr; 5874fe40a830SPrabhakar Kushwaha __le16 size; 5875fe40a830SPrabhakar Kushwaha __le16 flags; 5876fe40a830SPrabhakar Kushwaha #define TOE_RX_BD_START_MASK 0x1 5877fe40a830SPrabhakar Kushwaha #define TOE_RX_BD_START_SHIFT 0 5878fe40a830SPrabhakar Kushwaha #define TOE_RX_BD_END_MASK 0x1 5879fe40a830SPrabhakar Kushwaha #define TOE_RX_BD_END_SHIFT 1 5880fe40a830SPrabhakar Kushwaha #define TOE_RX_BD_NO_PUSH_MASK 0x1 5881fe40a830SPrabhakar Kushwaha #define TOE_RX_BD_NO_PUSH_SHIFT 2 5882fe40a830SPrabhakar Kushwaha #define TOE_RX_BD_SPLIT_MASK 0x1 5883fe40a830SPrabhakar Kushwaha #define TOE_RX_BD_SPLIT_SHIFT 3 5884fe40a830SPrabhakar Kushwaha #define TOE_RX_BD_RESERVED0_MASK 0xFFF 5885fe40a830SPrabhakar Kushwaha #define TOE_RX_BD_RESERVED0_SHIFT 4 5886fe40a830SPrabhakar Kushwaha __le32 reserved1; 5887fe40a830SPrabhakar Kushwaha }; 5888fe40a830SPrabhakar Kushwaha 5889fe40a830SPrabhakar Kushwaha /* TOE RX completion queue opcodes (opcode 0 is illegal) */ 5890fe40a830SPrabhakar Kushwaha enum toe_rx_cmp_opcode { 5891fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_GA = 1, 5892fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_GR = 2, 5893fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_GNI = 3, 5894fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_GAIR = 4, 5895fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_GAIL = 5, 5896fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_GRI = 6, 5897fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_GJ = 7, 5898fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_DGI = 8, 5899fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_CMP = 9, 5900fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_REL = 10, 5901fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_SKP = 11, 5902fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_URG = 12, 5903fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_RT_TO = 13, 5904fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_KA_TO = 14, 5905fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_MAX_RT = 15, 5906fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_DBT_RE = 16, 5907fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_SYN = 17, 5908fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_OPT_ERR = 18, 5909fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_FW2_TO = 19, 5910fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_2WY_CLS = 20, 5911fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_RST_RCV = 21, 5912fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_FIN_RCV = 22, 5913fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_FIN_UPL = 23, 5914fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_INIT = 32, 5915fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_RSS_UPDATE = 33, 5916fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_CLOSE = 34, 5917fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_INITIATE_OFFLOAD = 80, 5918fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_SEARCHER_DELETE = 81, 5919fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_TERMINATE = 82, 5920fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_QUERY = 83, 5921fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_RESET_SEND = 84, 5922fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_INVALIDATE = 85, 5923fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_EMPTY = 86, 5924fe40a830SPrabhakar Kushwaha TOE_RX_CMP_OPCODE_UPDATE = 87, 5925fe40a830SPrabhakar Kushwaha MAX_TOE_RX_CMP_OPCODE 5926fe40a830SPrabhakar Kushwaha }; 5927fe40a830SPrabhakar Kushwaha 5928fe40a830SPrabhakar Kushwaha /* TOE rx ooo completion data */ 5929fe40a830SPrabhakar Kushwaha struct toe_rx_cqe_ooo_params { 5930fe40a830SPrabhakar Kushwaha __le32 nbytes; 5931fe40a830SPrabhakar Kushwaha __le16 grq_buff_id; 5932fe40a830SPrabhakar Kushwaha u8 isle_num; 5933fe40a830SPrabhakar Kushwaha u8 reserved0; 5934fe40a830SPrabhakar Kushwaha }; 5935fe40a830SPrabhakar Kushwaha 5936fe40a830SPrabhakar Kushwaha /* TOE rx in order completion data */ 5937fe40a830SPrabhakar Kushwaha struct toe_rx_cqe_in_order_params { 5938fe40a830SPrabhakar Kushwaha __le32 nbytes; 5939fe40a830SPrabhakar Kushwaha __le16 grq_buff_id; 5940fe40a830SPrabhakar Kushwaha __le16 reserved1; 5941fe40a830SPrabhakar Kushwaha }; 5942fe40a830SPrabhakar Kushwaha 5943fe40a830SPrabhakar Kushwaha /* Union for TOE rx completion data */ 5944fe40a830SPrabhakar Kushwaha union toe_rx_cqe_data_union { 5945fe40a830SPrabhakar Kushwaha struct toe_rx_cqe_ooo_params ooo_params; 5946fe40a830SPrabhakar Kushwaha struct toe_rx_cqe_in_order_params in_order_params; 5947fe40a830SPrabhakar Kushwaha struct regpair raw_data; 5948fe40a830SPrabhakar Kushwaha }; 5949fe40a830SPrabhakar Kushwaha 5950fe40a830SPrabhakar Kushwaha /* TOE rx completion element */ 5951fe40a830SPrabhakar Kushwaha struct toe_rx_cqe { 5952fe40a830SPrabhakar Kushwaha __le16 icid; 5953fe40a830SPrabhakar Kushwaha u8 completion_opcode; 5954fe40a830SPrabhakar Kushwaha u8 reserved0; 5955fe40a830SPrabhakar Kushwaha __le32 reserved1; 5956fe40a830SPrabhakar Kushwaha union toe_rx_cqe_data_union data; 5957fe40a830SPrabhakar Kushwaha }; 5958fe40a830SPrabhakar Kushwaha 5959fe40a830SPrabhakar Kushwaha /* toe RX doorbel data */ 5960fe40a830SPrabhakar Kushwaha struct toe_rx_db_data { 5961fe40a830SPrabhakar Kushwaha __le32 local_adv_wnd_seq; 5962fe40a830SPrabhakar Kushwaha __le32 reserved[3]; 5963fe40a830SPrabhakar Kushwaha }; 5964fe40a830SPrabhakar Kushwaha 5965fe40a830SPrabhakar Kushwaha /* Toe GRQ buffer descriptor */ 5966fe40a830SPrabhakar Kushwaha struct toe_rx_grq_bd { 5967fe40a830SPrabhakar Kushwaha struct regpair addr; 5968fe40a830SPrabhakar Kushwaha __le16 buff_id; 5969fe40a830SPrabhakar Kushwaha __le16 reserved0; 5970fe40a830SPrabhakar Kushwaha __le32 reserved1; 5971fe40a830SPrabhakar Kushwaha }; 5972fe40a830SPrabhakar Kushwaha 5973fe40a830SPrabhakar Kushwaha /* Toe transmission application buffer descriptor */ 5974fe40a830SPrabhakar Kushwaha struct toe_tx_app_buff_desc { 5975fe40a830SPrabhakar Kushwaha __le32 next_buffer_start_seq; 5976fe40a830SPrabhakar Kushwaha __le32 reserved; 5977fe40a830SPrabhakar Kushwaha }; 5978fe40a830SPrabhakar Kushwaha 5979fe40a830SPrabhakar Kushwaha /* Toe transmission application buffer descriptor page pointer */ 5980fe40a830SPrabhakar Kushwaha struct toe_tx_app_buff_page_pointer { 5981fe40a830SPrabhakar Kushwaha struct regpair next_page_addr; 5982fe40a830SPrabhakar Kushwaha }; 5983fe40a830SPrabhakar Kushwaha 5984fe40a830SPrabhakar Kushwaha /* Toe transmission buffer descriptor */ 5985fe40a830SPrabhakar Kushwaha struct toe_tx_bd { 5986fe40a830SPrabhakar Kushwaha struct regpair addr; 5987fe40a830SPrabhakar Kushwaha __le16 size; 5988fe40a830SPrabhakar Kushwaha __le16 flags; 5989fe40a830SPrabhakar Kushwaha #define TOE_TX_BD_PUSH_MASK 0x1 5990fe40a830SPrabhakar Kushwaha #define TOE_TX_BD_PUSH_SHIFT 0 5991fe40a830SPrabhakar Kushwaha #define TOE_TX_BD_NOTIFY_MASK 0x1 5992fe40a830SPrabhakar Kushwaha #define TOE_TX_BD_NOTIFY_SHIFT 1 5993fe40a830SPrabhakar Kushwaha #define TOE_TX_BD_LARGE_IO_MASK 0x1 5994fe40a830SPrabhakar Kushwaha #define TOE_TX_BD_LARGE_IO_SHIFT 2 5995fe40a830SPrabhakar Kushwaha #define TOE_TX_BD_BD_CONS_MASK 0x1FFF 5996fe40a830SPrabhakar Kushwaha #define TOE_TX_BD_BD_CONS_SHIFT 3 5997fe40a830SPrabhakar Kushwaha __le32 next_bd_start_seq; 5998fe40a830SPrabhakar Kushwaha }; 5999fe40a830SPrabhakar Kushwaha 6000fe40a830SPrabhakar Kushwaha /* TOE completion opcodes */ 6001fe40a830SPrabhakar Kushwaha enum toe_tx_cmp_opcode { 6002fe40a830SPrabhakar Kushwaha TOE_TX_CMP_OPCODE_DATA, 6003fe40a830SPrabhakar Kushwaha TOE_TX_CMP_OPCODE_TERMINATE, 6004fe40a830SPrabhakar Kushwaha TOE_TX_CMP_OPCODE_EMPTY, 6005fe40a830SPrabhakar Kushwaha TOE_TX_CMP_OPCODE_RESET_SEND, 6006fe40a830SPrabhakar Kushwaha TOE_TX_CMP_OPCODE_INVALIDATE, 6007fe40a830SPrabhakar Kushwaha TOE_TX_CMP_OPCODE_RST_RCV, 6008fe40a830SPrabhakar Kushwaha MAX_TOE_TX_CMP_OPCODE 6009fe40a830SPrabhakar Kushwaha }; 6010fe40a830SPrabhakar Kushwaha 6011fe40a830SPrabhakar Kushwaha /* Toe transmission completion element */ 6012fe40a830SPrabhakar Kushwaha struct toe_tx_cqe { 6013fe40a830SPrabhakar Kushwaha __le16 icid; 6014fe40a830SPrabhakar Kushwaha u8 opcode; 6015fe40a830SPrabhakar Kushwaha u8 reserved; 6016fe40a830SPrabhakar Kushwaha __le32 size; 6017fe40a830SPrabhakar Kushwaha }; 6018fe40a830SPrabhakar Kushwaha 6019fe40a830SPrabhakar Kushwaha /* Toe transmission page pointer bd */ 6020fe40a830SPrabhakar Kushwaha struct toe_tx_page_pointer_bd { 6021fe40a830SPrabhakar Kushwaha struct regpair next_page_addr; 6022fe40a830SPrabhakar Kushwaha struct regpair prev_page_addr; 6023fe40a830SPrabhakar Kushwaha }; 6024fe40a830SPrabhakar Kushwaha 6025fe40a830SPrabhakar Kushwaha /* Toe transmission completion element page pointer */ 6026fe40a830SPrabhakar Kushwaha struct toe_tx_page_pointer_cqe { 6027fe40a830SPrabhakar Kushwaha struct regpair next_page_addr; 6028fe40a830SPrabhakar Kushwaha }; 6029fe40a830SPrabhakar Kushwaha 6030fe40a830SPrabhakar Kushwaha /* toe update parameters */ 6031fe40a830SPrabhakar Kushwaha struct toe_update_params { 6032fe40a830SPrabhakar Kushwaha __le16 flags; 6033fe40a830SPrabhakar Kushwaha #define TOE_UPDATE_PARAMS_RCV_INDICATION_SIZE_CHANGED_MASK 0x1 6034fe40a830SPrabhakar Kushwaha #define TOE_UPDATE_PARAMS_RCV_INDICATION_SIZE_CHANGED_SHIFT 0 6035fe40a830SPrabhakar Kushwaha #define TOE_UPDATE_PARAMS_RESERVED_MASK 0x7FFF 6036fe40a830SPrabhakar Kushwaha #define TOE_UPDATE_PARAMS_RESERVED_SHIFT 1 6037fe40a830SPrabhakar Kushwaha __le16 rcv_indication_size; 6038fe40a830SPrabhakar Kushwaha __le16 reserved1[2]; 6039fe40a830SPrabhakar Kushwaha }; 6040fe40a830SPrabhakar Kushwaha 6041fe40a830SPrabhakar Kushwaha /* TOE update ramrod data - DMAed by firmware */ 6042fe40a830SPrabhakar Kushwaha struct toe_update_ramrod_data { 6043fe40a830SPrabhakar Kushwaha struct tcp_update_params tcp_upd_params; 6044fe40a830SPrabhakar Kushwaha struct toe_update_params toe_upd_params; 6045fe40a830SPrabhakar Kushwaha }; 6046fe40a830SPrabhakar Kushwaha 6047fe40a830SPrabhakar Kushwaha struct mstorm_toe_conn_ag_ctx { 6048fe40a830SPrabhakar Kushwaha u8 byte0; 6049fe40a830SPrabhakar Kushwaha u8 byte1; 6050fe40a830SPrabhakar Kushwaha u8 flags0; 6051fe40a830SPrabhakar Kushwaha #define MSTORM_TOE_CONN_AG_CTX_BIT0_MASK 0x1 6052fe40a830SPrabhakar Kushwaha #define MSTORM_TOE_CONN_AG_CTX_BIT0_SHIFT 0 6053fe40a830SPrabhakar Kushwaha #define MSTORM_TOE_CONN_AG_CTX_BIT1_MASK 0x1 6054fe40a830SPrabhakar Kushwaha #define MSTORM_TOE_CONN_AG_CTX_BIT1_SHIFT 1 6055fe40a830SPrabhakar Kushwaha #define MSTORM_TOE_CONN_AG_CTX_CF0_MASK 0x3 6056fe40a830SPrabhakar Kushwaha #define MSTORM_TOE_CONN_AG_CTX_CF0_SHIFT 2 6057fe40a830SPrabhakar Kushwaha #define MSTORM_TOE_CONN_AG_CTX_CF1_MASK 0x3 6058fe40a830SPrabhakar Kushwaha #define MSTORM_TOE_CONN_AG_CTX_CF1_SHIFT 4 6059fe40a830SPrabhakar Kushwaha #define MSTORM_TOE_CONN_AG_CTX_CF2_MASK 0x3 6060fe40a830SPrabhakar Kushwaha #define MSTORM_TOE_CONN_AG_CTX_CF2_SHIFT 6 6061fe40a830SPrabhakar Kushwaha u8 flags1; 6062fe40a830SPrabhakar Kushwaha #define MSTORM_TOE_CONN_AG_CTX_CF0EN_MASK 0x1 6063fe40a830SPrabhakar Kushwaha #define MSTORM_TOE_CONN_AG_CTX_CF0EN_SHIFT 0 6064fe40a830SPrabhakar Kushwaha #define MSTORM_TOE_CONN_AG_CTX_CF1EN_MASK 0x1 6065fe40a830SPrabhakar Kushwaha #define MSTORM_TOE_CONN_AG_CTX_CF1EN_SHIFT 1 6066fe40a830SPrabhakar Kushwaha #define MSTORM_TOE_CONN_AG_CTX_CF2EN_MASK 0x1 6067fe40a830SPrabhakar Kushwaha #define MSTORM_TOE_CONN_AG_CTX_CF2EN_SHIFT 2 6068fe40a830SPrabhakar Kushwaha #define MSTORM_TOE_CONN_AG_CTX_RULE0EN_MASK 0x1 6069fe40a830SPrabhakar Kushwaha #define MSTORM_TOE_CONN_AG_CTX_RULE0EN_SHIFT 3 6070fe40a830SPrabhakar Kushwaha #define MSTORM_TOE_CONN_AG_CTX_RULE1EN_MASK 0x1 6071fe40a830SPrabhakar Kushwaha #define MSTORM_TOE_CONN_AG_CTX_RULE1EN_SHIFT 4 6072fe40a830SPrabhakar Kushwaha #define MSTORM_TOE_CONN_AG_CTX_RULE2EN_MASK 0x1 6073fe40a830SPrabhakar Kushwaha #define MSTORM_TOE_CONN_AG_CTX_RULE2EN_SHIFT 5 6074fe40a830SPrabhakar Kushwaha #define MSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK 0x1 6075fe40a830SPrabhakar Kushwaha #define MSTORM_TOE_CONN_AG_CTX_RULE3EN_SHIFT 6 6076fe40a830SPrabhakar Kushwaha #define MSTORM_TOE_CONN_AG_CTX_RULE4EN_MASK 0x1 6077fe40a830SPrabhakar Kushwaha #define MSTORM_TOE_CONN_AG_CTX_RULE4EN_SHIFT 7 6078fe40a830SPrabhakar Kushwaha __le16 word0; 6079fe40a830SPrabhakar Kushwaha __le16 word1; 6080fe40a830SPrabhakar Kushwaha __le32 reg0; 6081fe40a830SPrabhakar Kushwaha __le32 reg1; 6082fe40a830SPrabhakar Kushwaha }; 6083fe40a830SPrabhakar Kushwaha 6084fe40a830SPrabhakar Kushwaha /* TOE doorbell data */ 6085fe40a830SPrabhakar Kushwaha struct toe_db_data { 6086fe40a830SPrabhakar Kushwaha u8 params; 6087fe40a830SPrabhakar Kushwaha #define TOE_DB_DATA_DEST_MASK 0x3 6088fe40a830SPrabhakar Kushwaha #define TOE_DB_DATA_DEST_SHIFT 0 6089fe40a830SPrabhakar Kushwaha #define TOE_DB_DATA_AGG_CMD_MASK 0x3 6090fe40a830SPrabhakar Kushwaha #define TOE_DB_DATA_AGG_CMD_SHIFT 2 6091fe40a830SPrabhakar Kushwaha #define TOE_DB_DATA_BYPASS_EN_MASK 0x1 6092fe40a830SPrabhakar Kushwaha #define TOE_DB_DATA_BYPASS_EN_SHIFT 4 6093fe40a830SPrabhakar Kushwaha #define TOE_DB_DATA_RESERVED_MASK 0x1 6094fe40a830SPrabhakar Kushwaha #define TOE_DB_DATA_RESERVED_SHIFT 5 6095fe40a830SPrabhakar Kushwaha #define TOE_DB_DATA_AGG_VAL_SEL_MASK 0x3 6096fe40a830SPrabhakar Kushwaha #define TOE_DB_DATA_AGG_VAL_SEL_SHIFT 6 6097fe40a830SPrabhakar Kushwaha u8 agg_flags; 6098fe40a830SPrabhakar Kushwaha __le16 bd_prod; 6099fe40a830SPrabhakar Kushwaha }; 6100fe40a830SPrabhakar Kushwaha 6101a2e7699eSTomer Tayar /* rdma function init ramrod data */ 6102a2e7699eSTomer Tayar struct rdma_close_func_ramrod_data { 6103a2e7699eSTomer Tayar u8 cnq_start_offset; 6104a2e7699eSTomer Tayar u8 num_cnqs; 6105a2e7699eSTomer Tayar u8 vf_id; 6106a2e7699eSTomer Tayar u8 vf_valid; 6107a2e7699eSTomer Tayar u8 reserved[4]; 6108a2e7699eSTomer Tayar }; 6109a2e7699eSTomer Tayar 6110a2e7699eSTomer Tayar /* rdma function init CNQ parameters */ 6111a2e7699eSTomer Tayar struct rdma_cnq_params { 6112a2e7699eSTomer Tayar __le16 sb_num; 6113a2e7699eSTomer Tayar u8 sb_index; 6114a2e7699eSTomer Tayar u8 num_pbl_pages; 6115a2e7699eSTomer Tayar __le32 reserved; 6116a2e7699eSTomer Tayar struct regpair pbl_base_addr; 6117a2e7699eSTomer Tayar __le16 queue_zone_num; 6118a2e7699eSTomer Tayar u8 reserved1[6]; 6119a2e7699eSTomer Tayar }; 6120a2e7699eSTomer Tayar 6121a2e7699eSTomer Tayar /* rdma create cq ramrod data */ 6122a2e7699eSTomer Tayar struct rdma_create_cq_ramrod_data { 6123a2e7699eSTomer Tayar struct regpair cq_handle; 6124a2e7699eSTomer Tayar struct regpair pbl_addr; 6125a2e7699eSTomer Tayar __le32 max_cqes; 6126a2e7699eSTomer Tayar __le16 pbl_num_pages; 6127a2e7699eSTomer Tayar __le16 dpi; 6128a2e7699eSTomer Tayar u8 is_two_level_pbl; 6129a2e7699eSTomer Tayar u8 cnq_id; 6130a2e7699eSTomer Tayar u8 pbl_log_page_size; 6131a2e7699eSTomer Tayar u8 toggle_bit; 6132a2e7699eSTomer Tayar __le16 int_timeout; 61330500a70dSMichal Kalderon u8 vf_id; 61340500a70dSMichal Kalderon u8 flags; 61350500a70dSMichal Kalderon #define RDMA_CREATE_CQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1 61360500a70dSMichal Kalderon #define RDMA_CREATE_CQ_RAMROD_DATA_VF_ID_VALID_SHIFT 0 61370500a70dSMichal Kalderon #define RDMA_CREATE_CQ_RAMROD_DATA_RESERVED1_MASK 0x7F 61380500a70dSMichal Kalderon #define RDMA_CREATE_CQ_RAMROD_DATA_RESERVED1_SHIFT 1 6139a2e7699eSTomer Tayar }; 6140a2e7699eSTomer Tayar 6141a2e7699eSTomer Tayar /* rdma deregister tid ramrod data */ 6142a2e7699eSTomer Tayar struct rdma_deregister_tid_ramrod_data { 6143a2e7699eSTomer Tayar __le32 itid; 6144a2e7699eSTomer Tayar __le32 reserved; 6145a2e7699eSTomer Tayar }; 6146a2e7699eSTomer Tayar 6147a2e7699eSTomer Tayar /* rdma destroy cq output params */ 6148a2e7699eSTomer Tayar struct rdma_destroy_cq_output_params { 6149a2e7699eSTomer Tayar __le16 cnq_num; 6150a2e7699eSTomer Tayar __le16 reserved0; 6151a2e7699eSTomer Tayar __le32 reserved1; 6152a2e7699eSTomer Tayar }; 6153a2e7699eSTomer Tayar 6154a2e7699eSTomer Tayar /* rdma destroy cq ramrod data */ 6155a2e7699eSTomer Tayar struct rdma_destroy_cq_ramrod_data { 6156a2e7699eSTomer Tayar struct regpair output_params_addr; 6157a2e7699eSTomer Tayar }; 6158a2e7699eSTomer Tayar 6159a2e7699eSTomer Tayar /* RDMA slow path EQ cmd IDs */ 6160a2e7699eSTomer Tayar enum rdma_event_opcode { 6161a2e7699eSTomer Tayar RDMA_EVENT_UNUSED, 6162a2e7699eSTomer Tayar RDMA_EVENT_FUNC_INIT, 6163a2e7699eSTomer Tayar RDMA_EVENT_FUNC_CLOSE, 6164a2e7699eSTomer Tayar RDMA_EVENT_REGISTER_MR, 6165a2e7699eSTomer Tayar RDMA_EVENT_DEREGISTER_MR, 6166a2e7699eSTomer Tayar RDMA_EVENT_CREATE_CQ, 6167a2e7699eSTomer Tayar RDMA_EVENT_RESIZE_CQ, 6168a2e7699eSTomer Tayar RDMA_EVENT_DESTROY_CQ, 6169a2e7699eSTomer Tayar RDMA_EVENT_CREATE_SRQ, 6170a2e7699eSTomer Tayar RDMA_EVENT_MODIFY_SRQ, 6171a2e7699eSTomer Tayar RDMA_EVENT_DESTROY_SRQ, 6172fe40a830SPrabhakar Kushwaha RDMA_EVENT_START_NAMESPACE_TRACKING, 6173fe40a830SPrabhakar Kushwaha RDMA_EVENT_STOP_NAMESPACE_TRACKING, 6174a2e7699eSTomer Tayar MAX_RDMA_EVENT_OPCODE 6175a2e7699eSTomer Tayar }; 6176a2e7699eSTomer Tayar 6177a2e7699eSTomer Tayar /* RDMA FW return code for slow path ramrods */ 6178a2e7699eSTomer Tayar enum rdma_fw_return_code { 6179a2e7699eSTomer Tayar RDMA_RETURN_OK = 0, 6180a2e7699eSTomer Tayar RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR, 6181a2e7699eSTomer Tayar RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR, 6182a2e7699eSTomer Tayar RDMA_RETURN_RESIZE_CQ_ERR, 6183a2e7699eSTomer Tayar RDMA_RETURN_NIG_DRAIN_REQ, 61840500a70dSMichal Kalderon RDMA_RETURN_GENERAL_ERR, 6185a2e7699eSTomer Tayar MAX_RDMA_FW_RETURN_CODE 6186a2e7699eSTomer Tayar }; 6187a2e7699eSTomer Tayar 6188a2e7699eSTomer Tayar /* rdma function init header */ 6189a2e7699eSTomer Tayar struct rdma_init_func_hdr { 6190a2e7699eSTomer Tayar u8 cnq_start_offset; 6191a2e7699eSTomer Tayar u8 num_cnqs; 6192a2e7699eSTomer Tayar u8 cq_ring_mode; 6193a2e7699eSTomer Tayar u8 vf_id; 6194a2e7699eSTomer Tayar u8 vf_valid; 6195da090917STomer Tayar u8 relaxed_ordering; 619650bc60cbSMichal Kalderon __le16 first_reg_srq_id; 619750bc60cbSMichal Kalderon __le32 reg_srq_base_addr; 6198fe40a830SPrabhakar Kushwaha u8 flags; 6199fe40a830SPrabhakar Kushwaha #define RDMA_INIT_FUNC_HDR_SEARCHER_MODE_MASK 0x1 6200fe40a830SPrabhakar Kushwaha #define RDMA_INIT_FUNC_HDR_SEARCHER_MODE_SHIFT 0 6201fe40a830SPrabhakar Kushwaha #define RDMA_INIT_FUNC_HDR_PVRDMA_MODE_MASK 0x1 6202fe40a830SPrabhakar Kushwaha #define RDMA_INIT_FUNC_HDR_PVRDMA_MODE_SHIFT 1 6203fe40a830SPrabhakar Kushwaha #define RDMA_INIT_FUNC_HDR_DPT_MODE_MASK 0x1 6204fe40a830SPrabhakar Kushwaha #define RDMA_INIT_FUNC_HDR_DPT_MODE_SHIFT 2 6205fe40a830SPrabhakar Kushwaha #define RDMA_INIT_FUNC_HDR_RESERVED0_MASK 0x1F 6206fe40a830SPrabhakar Kushwaha #define RDMA_INIT_FUNC_HDR_RESERVED0_SHIFT 3 6207fe40a830SPrabhakar Kushwaha u8 dpt_byte_threshold_log; 6208fe40a830SPrabhakar Kushwaha u8 dpt_common_queue_id; 62090500a70dSMichal Kalderon u8 max_num_ns_log; 6210a2e7699eSTomer Tayar }; 6211a2e7699eSTomer Tayar 6212a2e7699eSTomer Tayar /* rdma function init ramrod data */ 6213a2e7699eSTomer Tayar struct rdma_init_func_ramrod_data { 6214a2e7699eSTomer Tayar struct rdma_init_func_hdr params_header; 6215fe40a830SPrabhakar Kushwaha struct rdma_cnq_params dptq_params; 6216a2e7699eSTomer Tayar struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES]; 6217a2e7699eSTomer Tayar }; 6218a2e7699eSTomer Tayar 6219fe40a830SPrabhakar Kushwaha /* rdma namespace tracking ramrod data */ 6220fe40a830SPrabhakar Kushwaha struct rdma_namespace_tracking_ramrod_data { 6221fe40a830SPrabhakar Kushwaha u8 name_space; 6222fe40a830SPrabhakar Kushwaha u8 reserved[7]; 6223fe40a830SPrabhakar Kushwaha }; 6224fe40a830SPrabhakar Kushwaha 6225a2e7699eSTomer Tayar /* RDMA ramrod command IDs */ 6226a2e7699eSTomer Tayar enum rdma_ramrod_cmd_id { 6227a2e7699eSTomer Tayar RDMA_RAMROD_UNUSED, 6228a2e7699eSTomer Tayar RDMA_RAMROD_FUNC_INIT, 6229a2e7699eSTomer Tayar RDMA_RAMROD_FUNC_CLOSE, 6230a2e7699eSTomer Tayar RDMA_RAMROD_REGISTER_MR, 6231a2e7699eSTomer Tayar RDMA_RAMROD_DEREGISTER_MR, 6232a2e7699eSTomer Tayar RDMA_RAMROD_CREATE_CQ, 6233a2e7699eSTomer Tayar RDMA_RAMROD_RESIZE_CQ, 6234a2e7699eSTomer Tayar RDMA_RAMROD_DESTROY_CQ, 6235a2e7699eSTomer Tayar RDMA_RAMROD_CREATE_SRQ, 6236a2e7699eSTomer Tayar RDMA_RAMROD_MODIFY_SRQ, 6237a2e7699eSTomer Tayar RDMA_RAMROD_DESTROY_SRQ, 6238fe40a830SPrabhakar Kushwaha RDMA_RAMROD_START_NS_TRACKING, 6239fe40a830SPrabhakar Kushwaha RDMA_RAMROD_STOP_NS_TRACKING, 6240a2e7699eSTomer Tayar MAX_RDMA_RAMROD_CMD_ID 6241a2e7699eSTomer Tayar }; 6242a2e7699eSTomer Tayar 6243a2e7699eSTomer Tayar /* rdma register tid ramrod data */ 6244a2e7699eSTomer Tayar struct rdma_register_tid_ramrod_data { 6245a2e7699eSTomer Tayar __le16 flags; 6246a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK 0x1F 6247a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT 0 6248a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK 0x1 6249a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT 5 6250a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK 0x1 6251a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT 6 6252a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK 0x1 6253a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT 7 6254a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK 0x1 6255a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT 8 6256a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK 0x1 6257a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT 9 6258a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK 0x1 6259a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT 10 6260a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK 0x1 6261a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT 11 6262a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK 0x1 6263a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT 12 6264a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK 0x1 6265a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT 13 6266a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_MASK 0x3 6267a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_SHIFT 14 6268a2e7699eSTomer Tayar u8 flags1; 6269a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK 0x1F 6270a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0 6271a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK 0x7 6272a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT 5 6273a2e7699eSTomer Tayar u8 flags2; 6274a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK 0x1 6275a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT 0 6276a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK 0x1 6277a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT 1 6278a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK 0x3F 6279a2e7699eSTomer Tayar #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT 2 6280a2e7699eSTomer Tayar u8 key; 6281a2e7699eSTomer Tayar u8 length_hi; 6282a2e7699eSTomer Tayar u8 vf_id; 6283a2e7699eSTomer Tayar u8 vf_valid; 6284a2e7699eSTomer Tayar __le16 pd; 6285a2e7699eSTomer Tayar __le16 reserved2; 6286a2e7699eSTomer Tayar __le32 length_lo; 6287a2e7699eSTomer Tayar __le32 itid; 6288a2e7699eSTomer Tayar __le32 reserved3; 6289a2e7699eSTomer Tayar struct regpair va; 6290a2e7699eSTomer Tayar struct regpair pbl_base; 6291a2e7699eSTomer Tayar struct regpair dif_error_addr; 6292d52c89f1SMichal Kalderon __le32 reserved4[4]; 6293a2e7699eSTomer Tayar }; 6294a2e7699eSTomer Tayar 6295a2e7699eSTomer Tayar /* rdma resize cq output params */ 6296a2e7699eSTomer Tayar struct rdma_resize_cq_output_params { 6297a2e7699eSTomer Tayar __le32 old_cq_cons; 6298a2e7699eSTomer Tayar __le32 old_cq_prod; 6299a2e7699eSTomer Tayar }; 6300a2e7699eSTomer Tayar 6301a2e7699eSTomer Tayar /* rdma resize cq ramrod data */ 6302a2e7699eSTomer Tayar struct rdma_resize_cq_ramrod_data { 6303a2e7699eSTomer Tayar u8 flags; 6304a2e7699eSTomer Tayar #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK 0x1 6305a2e7699eSTomer Tayar #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT 0 6306a2e7699eSTomer Tayar #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK 0x1 6307a2e7699eSTomer Tayar #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1 63080500a70dSMichal Kalderon #define RDMA_RESIZE_CQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1 63090500a70dSMichal Kalderon #define RDMA_RESIZE_CQ_RAMROD_DATA_VF_ID_VALID_SHIFT 2 63100500a70dSMichal Kalderon #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x1F 63110500a70dSMichal Kalderon #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT 3 6312a2e7699eSTomer Tayar u8 pbl_log_page_size; 6313a2e7699eSTomer Tayar __le16 pbl_num_pages; 6314a2e7699eSTomer Tayar __le32 max_cqes; 6315a2e7699eSTomer Tayar struct regpair pbl_addr; 6316a2e7699eSTomer Tayar struct regpair output_params_addr; 63170500a70dSMichal Kalderon u8 vf_id; 63180500a70dSMichal Kalderon u8 reserved1[7]; 6319a2e7699eSTomer Tayar }; 6320a2e7699eSTomer Tayar 63210500a70dSMichal Kalderon /* The rdma SRQ context */ 6322a2e7699eSTomer Tayar struct rdma_srq_context { 6323a2e7699eSTomer Tayar struct regpair temp[8]; 6324a2e7699eSTomer Tayar }; 6325a2e7699eSTomer Tayar 6326a2e7699eSTomer Tayar /* rdma create qp requester ramrod data */ 6327a2e7699eSTomer Tayar struct rdma_srq_create_ramrod_data { 632850bc60cbSMichal Kalderon u8 flags; 632950bc60cbSMichal Kalderon #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_MASK 0x1 633050bc60cbSMichal Kalderon #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_SHIFT 0 633150bc60cbSMichal Kalderon #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1 633250bc60cbSMichal Kalderon #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 1 633350bc60cbSMichal Kalderon #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_MASK 0x3F 633450bc60cbSMichal Kalderon #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_SHIFT 2 633550bc60cbSMichal Kalderon u8 reserved2; 633650bc60cbSMichal Kalderon __le16 xrc_domain; 633750bc60cbSMichal Kalderon __le32 xrc_srq_cq_cid; 6338a2e7699eSTomer Tayar struct regpair pbl_base_addr; 6339a2e7699eSTomer Tayar __le16 pages_in_srq_pbl; 6340a2e7699eSTomer Tayar __le16 pd_id; 6341a2e7699eSTomer Tayar struct rdma_srq_id srq_id; 6342a2e7699eSTomer Tayar __le16 page_size; 634350bc60cbSMichal Kalderon __le16 reserved3; 634450bc60cbSMichal Kalderon __le32 reserved4; 6345a2e7699eSTomer Tayar struct regpair producers_addr; 6346a2e7699eSTomer Tayar }; 6347a2e7699eSTomer Tayar 6348a2e7699eSTomer Tayar /* rdma create qp requester ramrod data */ 6349a2e7699eSTomer Tayar struct rdma_srq_destroy_ramrod_data { 6350a2e7699eSTomer Tayar struct rdma_srq_id srq_id; 6351a2e7699eSTomer Tayar __le32 reserved; 6352a2e7699eSTomer Tayar }; 6353a2e7699eSTomer Tayar 6354a2e7699eSTomer Tayar /* rdma create qp requester ramrod data */ 6355a2e7699eSTomer Tayar struct rdma_srq_modify_ramrod_data { 6356a2e7699eSTomer Tayar struct rdma_srq_id srq_id; 6357a2e7699eSTomer Tayar __le32 wqe_limit; 6358a2e7699eSTomer Tayar }; 6359a2e7699eSTomer Tayar 6360a2e7699eSTomer Tayar /* RDMA Tid type enumeration (for register_tid ramrod) */ 63617a9b6b8fSYuval Mintz enum rdma_tid_type { 63627a9b6b8fSYuval Mintz RDMA_TID_REGISTERED_MR, 63637a9b6b8fSYuval Mintz RDMA_TID_FMR, 6364d52c89f1SMichal Kalderon RDMA_TID_MW, 63657a9b6b8fSYuval Mintz MAX_RDMA_TID_TYPE 63667a9b6b8fSYuval Mintz }; 63677a9b6b8fSYuval Mintz 63680500a70dSMichal Kalderon /* The rdma XRC SRQ context */ 636950bc60cbSMichal Kalderon struct rdma_xrc_srq_context { 637050bc60cbSMichal Kalderon struct regpair temp[9]; 63717a9b6b8fSYuval Mintz }; 63727a9b6b8fSYuval Mintz 6373fb09a1edSShai Malin struct tstorm_rdma_task_ag_ctx { 63747a9b6b8fSYuval Mintz u8 byte0; 63757a9b6b8fSYuval Mintz u8 byte1; 63767a9b6b8fSYuval Mintz __le16 word0; 63777a9b6b8fSYuval Mintz u8 flags0; 6378fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF 6379fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0 6380fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1 6381fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4 6382fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 6383fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 6384fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 6385fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 6386fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 6387fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 63887a9b6b8fSYuval Mintz u8 flags1; 6389fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 6390fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 6391fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1 6392fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1 6393fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 6394fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2 6395fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 6396fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4 6397fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 6398fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6 63997a9b6b8fSYuval Mintz u8 flags2; 6400fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 6401fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0 6402fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3 6403fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2 6404fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3 6405fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4 6406fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3 6407fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6 64087a9b6b8fSYuval Mintz u8 flags3; 6409fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3 6410fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0 6411fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 6412fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2 6413fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 6414fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3 6415fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 6416fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4 6417fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 6418fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5 6419fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1 6420fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6 6421fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1 6422fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7 64237a9b6b8fSYuval Mintz u8 flags4; 6424fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1 6425fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0 6426fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1 6427fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1 6428fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 6429fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2 6430fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 6431fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3 6432fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 6433fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4 6434fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 6435fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5 6436fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 6437fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6 6438fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 6439fb09a1edSShai Malin #define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7 64407a9b6b8fSYuval Mintz u8 byte2; 64417a9b6b8fSYuval Mintz __le16 word1; 64427a9b6b8fSYuval Mintz __le32 reg0; 64437a9b6b8fSYuval Mintz u8 byte3; 64447a9b6b8fSYuval Mintz u8 byte4; 64457a9b6b8fSYuval Mintz __le16 word2; 64467a9b6b8fSYuval Mintz __le16 word3; 64477a9b6b8fSYuval Mintz __le16 word4; 64487a9b6b8fSYuval Mintz __le32 reg1; 64497a9b6b8fSYuval Mintz __le32 reg2; 64507a9b6b8fSYuval Mintz }; 64517a9b6b8fSYuval Mintz 6452fb09a1edSShai Malin struct ustorm_rdma_conn_ag_ctx { 64537a9b6b8fSYuval Mintz u8 reserved; 64547a9b6b8fSYuval Mintz u8 byte1; 64557a9b6b8fSYuval Mintz u8 flags0; 6456fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 6457fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 6458fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_DIF_ERROR_REPORTED_MASK 0x1 6459fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_DIF_ERROR_REPORTED_SHIFT 1 6460fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 6461fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2 6462fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 6463fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 6464fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 6465fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 64667a9b6b8fSYuval Mintz u8 flags1; 6467fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 6468fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0 6469fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 6470fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 6471fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 6472fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 6473fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 6474fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6 64757a9b6b8fSYuval Mintz u8 flags2; 6476fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 6477fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 6478fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 6479fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 6480fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 6481fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 6482fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 6483fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3 6484fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 6485fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 6486fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 6487fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 6488fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 6489fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6 6490fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 6491fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 64927a9b6b8fSYuval Mintz u8 flags3; 6493fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1 6494fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0 6495fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 6496fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1 6497fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 6498fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2 6499fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 6500fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3 6501fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 6502fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4 6503fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 6504fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5 6505fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 6506fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6 6507fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 6508fb09a1edSShai Malin #define USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7 65097a9b6b8fSYuval Mintz u8 byte2; 6510a3f72307SDenis Bolotin u8 nvmf_only; 65117a9b6b8fSYuval Mintz __le16 conn_dpi; 65127a9b6b8fSYuval Mintz __le16 word1; 65137a9b6b8fSYuval Mintz __le32 cq_cons; 65147a9b6b8fSYuval Mintz __le32 cq_se_prod; 65157a9b6b8fSYuval Mintz __le32 cq_prod; 65167a9b6b8fSYuval Mintz __le32 reg3; 65177a9b6b8fSYuval Mintz __le16 int_timeout; 65187a9b6b8fSYuval Mintz __le16 word3; 65197a9b6b8fSYuval Mintz }; 65207a9b6b8fSYuval Mintz 6521fb09a1edSShai Malin struct xstorm_roce_conn_ag_ctx { 65227a9b6b8fSYuval Mintz u8 reserved0; 65237a9b6b8fSYuval Mintz u8 state; 65247a9b6b8fSYuval Mintz u8 flags0; 6525fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 6526fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 6527fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1 6528fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1 6529fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_BIT2_MASK 0x1 6530fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_BIT2_SHIFT 2 6531fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 6532fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 6533fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_BIT4_MASK 0x1 6534fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_BIT4_SHIFT 4 6535fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_BIT5_MASK 0x1 6536fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_BIT5_SHIFT 5 6537fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_BIT6_MASK 0x1 6538fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_BIT6_SHIFT 6 6539fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_BIT7_MASK 0x1 6540fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_BIT7_SHIFT 7 65417a9b6b8fSYuval Mintz u8 flags1; 6542fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_BIT8_MASK 0x1 6543fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_BIT8_SHIFT 0 6544fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_BIT9_MASK 0x1 6545fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_BIT9_SHIFT 1 6546fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_BIT10_MASK 0x1 6547fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_BIT10_SHIFT 2 6548fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_BIT11_MASK 0x1 6549fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_BIT11_SHIFT 3 6550fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1 6551fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_SHIFT 4 6552fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1 6553fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_SHIFT 5 6554fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_BIT14_MASK 0x1 6555fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_BIT14_SHIFT 6 6556fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 6557fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 65587a9b6b8fSYuval Mintz u8 flags2; 6559fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3 6560fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 0 6561fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3 6562fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT 2 6563fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3 6564fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 4 6565fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF3_MASK 0x3 6566fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF3_SHIFT 6 65677a9b6b8fSYuval Mintz u8 flags3; 6568fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF4_MASK 0x3 6569fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF4_SHIFT 0 6570fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF5_MASK 0x3 6571fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF5_SHIFT 2 6572fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF6_MASK 0x3 6573fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF6_SHIFT 4 6574fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 6575fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 65767a9b6b8fSYuval Mintz u8 flags4; 6577fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF8_MASK 0x3 6578fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF8_SHIFT 0 6579fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF9_MASK 0x3 6580fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF9_SHIFT 2 6581fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF10_MASK 0x3 6582fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF10_SHIFT 4 6583fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF11_MASK 0x3 6584fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF11_SHIFT 6 65857a9b6b8fSYuval Mintz u8 flags5; 6586fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF12_MASK 0x3 6587fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF12_SHIFT 0 6588fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF13_MASK 0x3 6589fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF13_SHIFT 2 6590fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF14_MASK 0x3 6591fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF14_SHIFT 4 6592fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF15_MASK 0x3 6593fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF15_SHIFT 6 65947a9b6b8fSYuval Mintz u8 flags6; 6595fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF16_MASK 0x3 6596fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF16_SHIFT 0 6597fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF17_MASK 0x3 6598fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF17_SHIFT 2 6599fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF18_MASK 0x3 6600fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF18_SHIFT 4 6601fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF19_MASK 0x3 6602fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF19_SHIFT 6 66037a9b6b8fSYuval Mintz u8 flags7; 6604fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF20_MASK 0x3 6605fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF20_SHIFT 0 6606fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF21_MASK 0x3 6607fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF21_SHIFT 2 6608fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 6609fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 6610fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1 6611fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 6 6612fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1 6613fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT 7 66147a9b6b8fSYuval Mintz u8 flags8; 6615fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1 6616fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 0 6617fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF3EN_MASK 0x1 6618fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF3EN_SHIFT 1 6619fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF4EN_MASK 0x1 6620fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF4EN_SHIFT 2 6621fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK 0x1 6622fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF5EN_SHIFT 3 6623fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK 0x1 6624fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF6EN_SHIFT 4 6625fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 6626fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 6627fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK 0x1 6628fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF8EN_SHIFT 6 6629fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK 0x1 6630fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF9EN_SHIFT 7 66317a9b6b8fSYuval Mintz u8 flags9; 6632fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK 0x1 6633fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF10EN_SHIFT 0 6634fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF11EN_MASK 0x1 6635fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF11EN_SHIFT 1 6636fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF12EN_MASK 0x1 6637fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF12EN_SHIFT 2 6638fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF13EN_MASK 0x1 6639fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF13EN_SHIFT 3 6640fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF14EN_MASK 0x1 6641fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF14EN_SHIFT 4 6642fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF15EN_MASK 0x1 6643fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF15EN_SHIFT 5 6644fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF16EN_MASK 0x1 6645fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF16EN_SHIFT 6 6646fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF17EN_MASK 0x1 6647fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF17EN_SHIFT 7 66487a9b6b8fSYuval Mintz u8 flags10; 6649fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF18EN_MASK 0x1 6650fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF18EN_SHIFT 0 6651fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF19EN_MASK 0x1 6652fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF19EN_SHIFT 1 6653fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF20EN_MASK 0x1 6654fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF20EN_SHIFT 2 6655fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF21EN_MASK 0x1 6656fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF21EN_SHIFT 3 6657fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 6658fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 6659fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF23EN_MASK 0x1 6660fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF23EN_SHIFT 5 6661fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1 6662fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 6 6663fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1 6664fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 7 66657a9b6b8fSYuval Mintz u8 flags11; 6666fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1 6667fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 0 6668fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1 6669fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 1 6670fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1 6671fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 2 6672fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK 0x1 6673fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE5EN_SHIFT 3 6674fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK 0x1 6675fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE6EN_SHIFT 4 6676fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK 0x1 6677fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE7EN_SHIFT 5 6678fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 6679fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 6680fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE9EN_MASK 0x1 6681fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE9EN_SHIFT 7 66827a9b6b8fSYuval Mintz u8 flags12; 6683fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE10EN_MASK 0x1 6684fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE10EN_SHIFT 0 6685fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE11EN_MASK 0x1 6686fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE11EN_SHIFT 1 6687fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 6688fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 6689fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 6690fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 6691fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE14EN_MASK 0x1 6692fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE14EN_SHIFT 4 6693fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE15EN_MASK 0x1 6694fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE15EN_SHIFT 5 6695fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE16EN_MASK 0x1 6696fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE16EN_SHIFT 6 6697fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE17EN_MASK 0x1 6698fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE17EN_SHIFT 7 66997a9b6b8fSYuval Mintz u8 flags13; 6700fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE18EN_MASK 0x1 6701fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE18EN_SHIFT 0 6702fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE19EN_MASK 0x1 6703fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RULE19EN_SHIFT 1 6704fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 6705fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 6706fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 6707fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 6708fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 6709fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 6710fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 6711fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 6712fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 6713fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 6714fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 6715fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 67167a9b6b8fSYuval Mintz u8 flags14; 6717fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_MIGRATION_MASK 0x1 6718fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_MIGRATION_SHIFT 0 6719fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_BIT17_MASK 0x1 6720fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_BIT17_SHIFT 1 6721fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 6722fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 6723fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RESERVED_MASK 0x1 6724fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_RESERVED_SHIFT 4 6725fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 6726fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 6727fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF23_MASK 0x3 6728fb09a1edSShai Malin #define XSTORM_ROCE_CONN_AG_CTX_CF23_SHIFT 6 67297a9b6b8fSYuval Mintz u8 byte2; 67307a9b6b8fSYuval Mintz __le16 physical_q0; 67317a9b6b8fSYuval Mintz __le16 word1; 67327a9b6b8fSYuval Mintz __le16 word2; 67337a9b6b8fSYuval Mintz __le16 word3; 67347a9b6b8fSYuval Mintz __le16 word4; 67357a9b6b8fSYuval Mintz __le16 word5; 67367a9b6b8fSYuval Mintz __le16 conn_dpi; 67377a9b6b8fSYuval Mintz u8 byte3; 67387a9b6b8fSYuval Mintz u8 byte4; 67397a9b6b8fSYuval Mintz u8 byte5; 67407a9b6b8fSYuval Mintz u8 byte6; 67417a9b6b8fSYuval Mintz __le32 reg0; 67427a9b6b8fSYuval Mintz __le32 reg1; 67437a9b6b8fSYuval Mintz __le32 reg2; 67447a9b6b8fSYuval Mintz __le32 snd_nxt_psn; 67457a9b6b8fSYuval Mintz __le32 reg4; 67467a9b6b8fSYuval Mintz __le32 reg5; 67477a9b6b8fSYuval Mintz __le32 reg6; 67487a9b6b8fSYuval Mintz }; 67497a9b6b8fSYuval Mintz 6750fb09a1edSShai Malin struct tstorm_roce_conn_ag_ctx { 675150bc60cbSMichal Kalderon u8 reserved0; 67527a9b6b8fSYuval Mintz u8 byte1; 67537a9b6b8fSYuval Mintz u8 flags0; 6754fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 6755fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 6756fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1 6757fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1 6758fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_BIT2_MASK 0x1 6759fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_BIT2_SHIFT 2 6760fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_BIT3_MASK 0x1 6761fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_BIT3_SHIFT 3 6762fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_BIT4_MASK 0x1 6763fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_BIT4_SHIFT 4 6764fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_BIT5_MASK 0x1 6765fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_BIT5_SHIFT 5 6766fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3 6767fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 6 67687a9b6b8fSYuval Mintz u8 flags1; 6769fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 6770fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 6771fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3 6772fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 2 6773fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 6774fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 6775fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 6776fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 677750bc60cbSMichal Kalderon u8 flags2; 6778fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF5_MASK 0x3 6779fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF5_SHIFT 0 6780fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF6_MASK 0x3 6781fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF6_SHIFT 2 6782fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF7_MASK 0x3 6783fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF7_SHIFT 4 6784fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF8_MASK 0x3 6785fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF8_SHIFT 6 678650bc60cbSMichal Kalderon u8 flags3; 6787fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF9_MASK 0x3 6788fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF9_SHIFT 0 6789fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF10_MASK 0x3 6790fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF10_SHIFT 2 6791fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1 6792fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 4 6793fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 6794fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 5 6795fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1 6796fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 6 6797fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 6798fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 679950bc60cbSMichal Kalderon u8 flags4; 6800fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 6801fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 6802fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK 0x1 6803fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF5EN_SHIFT 1 6804fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK 0x1 6805fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF6EN_SHIFT 2 6806fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF7EN_MASK 0x1 6807fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF7EN_SHIFT 3 6808fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK 0x1 6809fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF8EN_SHIFT 4 6810fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK 0x1 6811fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF9EN_SHIFT 5 6812fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK 0x1 6813fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_CF10EN_SHIFT 6 6814fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1 6815fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 7 681650bc60cbSMichal Kalderon u8 flags5; 6817fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1 6818fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 0 6819fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1 6820fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 1 6821fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1 6822fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 2 6823fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1 6824fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 3 6825fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK 0x1 6826fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_RULE5EN_SHIFT 4 6827fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK 0x1 6828fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_RULE6EN_SHIFT 5 6829fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK 0x1 6830fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_RULE7EN_SHIFT 6 6831fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_RULE8EN_MASK 0x1 6832fb09a1edSShai Malin #define TSTORM_ROCE_CONN_AG_CTX_RULE8EN_SHIFT 7 683350bc60cbSMichal Kalderon __le32 reg0; 683450bc60cbSMichal Kalderon __le32 reg1; 683550bc60cbSMichal Kalderon __le32 reg2; 683650bc60cbSMichal Kalderon __le32 reg3; 683750bc60cbSMichal Kalderon __le32 reg4; 683850bc60cbSMichal Kalderon __le32 reg5; 683950bc60cbSMichal Kalderon __le32 reg6; 684050bc60cbSMichal Kalderon __le32 reg7; 684150bc60cbSMichal Kalderon __le32 reg8; 68427a9b6b8fSYuval Mintz u8 byte2; 68437a9b6b8fSYuval Mintz u8 byte3; 68447a9b6b8fSYuval Mintz __le16 word0; 684550bc60cbSMichal Kalderon u8 byte4; 684650bc60cbSMichal Kalderon u8 byte5; 68477a9b6b8fSYuval Mintz __le16 word1; 68487a9b6b8fSYuval Mintz __le16 word2; 68497a9b6b8fSYuval Mintz __le16 word3; 685050bc60cbSMichal Kalderon __le32 reg9; 685150bc60cbSMichal Kalderon __le32 reg10; 68527a9b6b8fSYuval Mintz }; 68537a9b6b8fSYuval Mintz 6854a2e7699eSTomer Tayar /* The roce storm context of Ystorm */ 68557a9b6b8fSYuval Mintz struct ystorm_roce_conn_st_ctx { 68567a9b6b8fSYuval Mintz struct regpair temp[2]; 68577a9b6b8fSYuval Mintz }; 68587a9b6b8fSYuval Mintz 6859a2e7699eSTomer Tayar /* The roce storm context of Mstorm */ 6860a2e7699eSTomer Tayar struct pstorm_roce_conn_st_ctx { 6861a2e7699eSTomer Tayar struct regpair temp[16]; 6862a2e7699eSTomer Tayar }; 6863a2e7699eSTomer Tayar 6864a2e7699eSTomer Tayar /* The roce storm context of Xstorm */ 68657a9b6b8fSYuval Mintz struct xstorm_roce_conn_st_ctx { 6866be086e7cSMintz, Yuval struct regpair temp[24]; 68677a9b6b8fSYuval Mintz }; 68687a9b6b8fSYuval Mintz 6869a2e7699eSTomer Tayar /* The roce storm context of Tstorm */ 68707a9b6b8fSYuval Mintz struct tstorm_roce_conn_st_ctx { 68717a9b6b8fSYuval Mintz struct regpair temp[30]; 68727a9b6b8fSYuval Mintz }; 68737a9b6b8fSYuval Mintz 6874a2e7699eSTomer Tayar /* The roce storm context of Mstorm */ 6875a2e7699eSTomer Tayar struct mstorm_roce_conn_st_ctx { 6876a2e7699eSTomer Tayar struct regpair temp[6]; 6877a2e7699eSTomer Tayar }; 6878a2e7699eSTomer Tayar 68790500a70dSMichal Kalderon /* The roce storm context of Ustorm */ 68807a9b6b8fSYuval Mintz struct ustorm_roce_conn_st_ctx { 68810500a70dSMichal Kalderon struct regpair temp[14]; 68827a9b6b8fSYuval Mintz }; 68837a9b6b8fSYuval Mintz 6884a2e7699eSTomer Tayar /* roce connection context */ 6885fb09a1edSShai Malin struct roce_conn_context { 68867a9b6b8fSYuval Mintz struct ystorm_roce_conn_st_ctx ystorm_st_context; 68877a9b6b8fSYuval Mintz struct regpair ystorm_st_padding[2]; 68887a9b6b8fSYuval Mintz struct pstorm_roce_conn_st_ctx pstorm_st_context; 68897a9b6b8fSYuval Mintz struct xstorm_roce_conn_st_ctx xstorm_st_context; 6890fb09a1edSShai Malin struct xstorm_roce_conn_ag_ctx xstorm_ag_context; 6891fb09a1edSShai Malin struct tstorm_roce_conn_ag_ctx tstorm_ag_context; 68927a9b6b8fSYuval Mintz struct timers_context timer_context; 6893fb09a1edSShai Malin struct ustorm_rdma_conn_ag_ctx ustorm_ag_context; 68947a9b6b8fSYuval Mintz struct tstorm_roce_conn_st_ctx tstorm_st_context; 689550bc60cbSMichal Kalderon struct regpair tstorm_st_padding[2]; 68967a9b6b8fSYuval Mintz struct mstorm_roce_conn_st_ctx mstorm_st_context; 689750bc60cbSMichal Kalderon struct regpair mstorm_st_padding[2]; 68987a9b6b8fSYuval Mintz struct ustorm_roce_conn_st_ctx ustorm_st_context; 68990500a70dSMichal Kalderon struct regpair ustorm_st_padding[2]; 69007a9b6b8fSYuval Mintz }; 69017a9b6b8fSYuval Mintz 6902d52c89f1SMichal Kalderon /* roce cqes statistics */ 6903d52c89f1SMichal Kalderon struct roce_cqe_stats { 6904d52c89f1SMichal Kalderon __le32 req_cqe_error; 6905d52c89f1SMichal Kalderon __le32 req_remote_access_errors; 6906d52c89f1SMichal Kalderon __le32 req_remote_invalid_request; 6907d52c89f1SMichal Kalderon __le32 resp_cqe_error; 6908d52c89f1SMichal Kalderon __le32 resp_local_length_error; 6909d52c89f1SMichal Kalderon __le32 reserved; 6910d52c89f1SMichal Kalderon }; 6911d52c89f1SMichal Kalderon 6912a2e7699eSTomer Tayar /* roce create qp requester ramrod data */ 69137a9b6b8fSYuval Mintz struct roce_create_qp_req_ramrod_data { 69147a9b6b8fSYuval Mintz __le16 flags; 69157a9b6b8fSYuval Mintz #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 69167a9b6b8fSYuval Mintz #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0 69177a9b6b8fSYuval Mintz #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1 69187a9b6b8fSYuval Mintz #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 2 69197a9b6b8fSYuval Mintz #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1 69207a9b6b8fSYuval Mintz #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT 3 69217a9b6b8fSYuval Mintz #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK 0x7 69227a9b6b8fSYuval Mintz #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT 4 692350bc60cbSMichal Kalderon #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_MASK 0x1 692450bc60cbSMichal Kalderon #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_SHIFT 7 69257a9b6b8fSYuval Mintz #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF 69267a9b6b8fSYuval Mintz #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 8 69277a9b6b8fSYuval Mintz #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF 69287a9b6b8fSYuval Mintz #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 12 69297a9b6b8fSYuval Mintz u8 max_ord; 69307a9b6b8fSYuval Mintz u8 traffic_class; 69317a9b6b8fSYuval Mintz u8 hop_limit; 69327a9b6b8fSYuval Mintz u8 orq_num_pages; 69337a9b6b8fSYuval Mintz __le16 p_key; 69347a9b6b8fSYuval Mintz __le32 flow_label; 69357a9b6b8fSYuval Mintz __le32 dst_qp_id; 69367a9b6b8fSYuval Mintz __le32 ack_timeout_val; 69377a9b6b8fSYuval Mintz __le32 initial_psn; 69387a9b6b8fSYuval Mintz __le16 mtu; 69397a9b6b8fSYuval Mintz __le16 pd; 69407a9b6b8fSYuval Mintz __le16 sq_num_pages; 6941be086e7cSMintz, Yuval __le16 low_latency_phy_queue; 69427a9b6b8fSYuval Mintz struct regpair sq_pbl_addr; 69437a9b6b8fSYuval Mintz struct regpair orq_pbl_addr; 69447a9b6b8fSYuval Mintz __le16 local_mac_addr[3]; 69457a9b6b8fSYuval Mintz __le16 remote_mac_addr[3]; 69467a9b6b8fSYuval Mintz __le16 vlan_id; 69477a9b6b8fSYuval Mintz __le16 udp_src_port; 69487a9b6b8fSYuval Mintz __le32 src_gid[4]; 69497a9b6b8fSYuval Mintz __le32 dst_gid[4]; 695050bc60cbSMichal Kalderon __le32 cq_cid; 69517a9b6b8fSYuval Mintz struct regpair qp_handle_for_cqe; 69527a9b6b8fSYuval Mintz struct regpair qp_handle_for_async; 69537a9b6b8fSYuval Mintz u8 stats_counter_id; 69540500a70dSMichal Kalderon u8 vf_id; 69550500a70dSMichal Kalderon u8 vport_id; 6956a3f72307SDenis Bolotin u8 flags2; 6957a3f72307SDenis Bolotin #define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_MASK 0x1 6958a3f72307SDenis Bolotin #define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_SHIFT 0 69590500a70dSMichal Kalderon #define ROCE_CREATE_QP_REQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1 69600500a70dSMichal Kalderon #define ROCE_CREATE_QP_REQ_RAMROD_DATA_VF_ID_VALID_SHIFT 1 6961fe40a830SPrabhakar Kushwaha #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FORCE_LB_MASK 0x1 6962fe40a830SPrabhakar Kushwaha #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FORCE_LB_SHIFT 2 6963fe40a830SPrabhakar Kushwaha #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK 0x1F 6964fe40a830SPrabhakar Kushwaha #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_SHIFT 3 69650500a70dSMichal Kalderon u8 name_space; 69660500a70dSMichal Kalderon u8 reserved3[3]; 6967be086e7cSMintz, Yuval __le16 regular_latency_phy_queue; 69687a9b6b8fSYuval Mintz __le16 dpi; 69697a9b6b8fSYuval Mintz }; 69707a9b6b8fSYuval Mintz 6971a2e7699eSTomer Tayar /* roce create qp responder ramrod data */ 69727a9b6b8fSYuval Mintz struct roce_create_qp_resp_ramrod_data { 697350bc60cbSMichal Kalderon __le32 flags; 69747a9b6b8fSYuval Mintz #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 69757a9b6b8fSYuval Mintz #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0 69767a9b6b8fSYuval Mintz #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 69777a9b6b8fSYuval Mintz #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2 69787a9b6b8fSYuval Mintz #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 69797a9b6b8fSYuval Mintz #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3 69807a9b6b8fSYuval Mintz #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 69817a9b6b8fSYuval Mintz #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 4 69827a9b6b8fSYuval Mintz #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK 0x1 69837a9b6b8fSYuval Mintz #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT 5 69847a9b6b8fSYuval Mintz #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1 69857a9b6b8fSYuval Mintz #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT 6 698605fafbfbSYuval Mintz #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1 698705fafbfbSYuval Mintz #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 7 69887a9b6b8fSYuval Mintz #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK 0x7 69897a9b6b8fSYuval Mintz #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT 8 69907a9b6b8fSYuval Mintz #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F 69917a9b6b8fSYuval Mintz #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 11 699250bc60cbSMichal Kalderon #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_MASK 0x1 699350bc60cbSMichal Kalderon #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_SHIFT 16 69940500a70dSMichal Kalderon #define ROCE_CREATE_QP_RESP_RAMROD_DATA_VF_ID_VALID_MASK 0x1 69950500a70dSMichal Kalderon #define ROCE_CREATE_QP_RESP_RAMROD_DATA_VF_ID_VALID_SHIFT 17 6996fe40a830SPrabhakar Kushwaha #define ROCE_CREATE_QP_RESP_RAMROD_DATA_FORCE_LB_MASK 0x1 6997fe40a830SPrabhakar Kushwaha #define ROCE_CREATE_QP_RESP_RAMROD_DATA_FORCE_LB_SHIFT 18 6998fe40a830SPrabhakar Kushwaha #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_MASK 0x1FFF 6999fe40a830SPrabhakar Kushwaha #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_SHIFT 19 700050bc60cbSMichal Kalderon __le16 xrc_domain; 70017a9b6b8fSYuval Mintz u8 max_ird; 70027a9b6b8fSYuval Mintz u8 traffic_class; 70037a9b6b8fSYuval Mintz u8 hop_limit; 70047a9b6b8fSYuval Mintz u8 irq_num_pages; 70057a9b6b8fSYuval Mintz __le16 p_key; 70067a9b6b8fSYuval Mintz __le32 flow_label; 70077a9b6b8fSYuval Mintz __le32 dst_qp_id; 70087a9b6b8fSYuval Mintz u8 stats_counter_id; 70097a9b6b8fSYuval Mintz u8 reserved1; 70107a9b6b8fSYuval Mintz __le16 mtu; 70117a9b6b8fSYuval Mintz __le32 initial_psn; 70127a9b6b8fSYuval Mintz __le16 pd; 70137a9b6b8fSYuval Mintz __le16 rq_num_pages; 70147a9b6b8fSYuval Mintz struct rdma_srq_id srq_id; 70157a9b6b8fSYuval Mintz struct regpair rq_pbl_addr; 70167a9b6b8fSYuval Mintz struct regpair irq_pbl_addr; 70177a9b6b8fSYuval Mintz __le16 local_mac_addr[3]; 70187a9b6b8fSYuval Mintz __le16 remote_mac_addr[3]; 70197a9b6b8fSYuval Mintz __le16 vlan_id; 70207a9b6b8fSYuval Mintz __le16 udp_src_port; 70217a9b6b8fSYuval Mintz __le32 src_gid[4]; 70227a9b6b8fSYuval Mintz __le32 dst_gid[4]; 70237a9b6b8fSYuval Mintz struct regpair qp_handle_for_cqe; 70247a9b6b8fSYuval Mintz struct regpair qp_handle_for_async; 7025be086e7cSMintz, Yuval __le16 low_latency_phy_queue; 70260500a70dSMichal Kalderon u8 vf_id; 70270500a70dSMichal Kalderon u8 vport_id; 70287a9b6b8fSYuval Mintz __le32 cq_cid; 7029be086e7cSMintz, Yuval __le16 regular_latency_phy_queue; 70307a9b6b8fSYuval Mintz __le16 dpi; 70310500a70dSMichal Kalderon __le32 src_qp_id; 70320500a70dSMichal Kalderon u8 name_space; 70330500a70dSMichal Kalderon u8 reserved3[3]; 70347a9b6b8fSYuval Mintz }; 70357a9b6b8fSYuval Mintz 7036fe40a830SPrabhakar Kushwaha /* RoCE Create Suspended qp requester runtime ramrod data */ 7037fe40a830SPrabhakar Kushwaha struct roce_create_suspended_qp_req_runtime_ramrod_data { 7038fe40a830SPrabhakar Kushwaha __le32 flags; 7039fe40a830SPrabhakar Kushwaha #define ROCE_CREATE_SUSPENDED_QP_REQ_RUNTIME_RAMROD_DATA_ERR_FLG_MASK 0x1 7040fe40a830SPrabhakar Kushwaha #define ROCE_CREATE_SUSPENDED_QP_REQ_RUNTIME_RAMROD_DATA_ERR_FLG_SHIFT 0 7041fe40a830SPrabhakar Kushwaha #define ROCE_CREATE_SUSPENDED_QP_REQ_RUNTIME_RAMROD_DATA_RESERVED0_MASK \ 7042fe40a830SPrabhakar Kushwaha 0x7FFFFFFF 7043fe40a830SPrabhakar Kushwaha #define ROCE_CREATE_SUSPENDED_QP_REQ_RUNTIME_RAMROD_DATA_RESERVED0_SHIFT 1 7044fe40a830SPrabhakar Kushwaha __le32 send_msg_psn; 7045fe40a830SPrabhakar Kushwaha __le32 inflight_sends; 7046fe40a830SPrabhakar Kushwaha __le32 ssn; 7047fe40a830SPrabhakar Kushwaha }; 7048fe40a830SPrabhakar Kushwaha 7049fe40a830SPrabhakar Kushwaha /* RoCE Create Suspended QP requester ramrod data */ 7050fe40a830SPrabhakar Kushwaha struct roce_create_suspended_qp_req_ramrod_data { 7051fe40a830SPrabhakar Kushwaha struct roce_create_qp_req_ramrod_data qp_params; 7052fe40a830SPrabhakar Kushwaha struct roce_create_suspended_qp_req_runtime_ramrod_data 7053fe40a830SPrabhakar Kushwaha qp_runtime_params; 7054fe40a830SPrabhakar Kushwaha }; 7055fe40a830SPrabhakar Kushwaha 7056fe40a830SPrabhakar Kushwaha /* RoCE Create Suspended QP responder runtime params */ 7057fe40a830SPrabhakar Kushwaha struct roce_create_suspended_qp_resp_runtime_params { 7058fe40a830SPrabhakar Kushwaha __le32 flags; 7059fe40a830SPrabhakar Kushwaha #define ROCE_CREATE_SUSPENDED_QP_RESP_RUNTIME_PARAMS_ERR_FLG_MASK 0x1 7060fe40a830SPrabhakar Kushwaha #define ROCE_CREATE_SUSPENDED_QP_RESP_RUNTIME_PARAMS_ERR_FLG_SHIFT 0 7061fe40a830SPrabhakar Kushwaha #define ROCE_CREATE_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RDMA_ACTIVE_MASK 0x1 7062fe40a830SPrabhakar Kushwaha #define ROCE_CREATE_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RDMA_ACTIVE_SHIFT 1 7063fe40a830SPrabhakar Kushwaha #define ROCE_CREATE_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RESERVED0_MASK 0x3FFFFFFF 7064fe40a830SPrabhakar Kushwaha #define ROCE_CREATE_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RESERVED0_SHIFT 2 7065fe40a830SPrabhakar Kushwaha __le32 receive_msg_psn; 7066fe40a830SPrabhakar Kushwaha __le32 inflight_receives; 7067fe40a830SPrabhakar Kushwaha __le32 rmsn; 7068fe40a830SPrabhakar Kushwaha __le32 rdma_key; 7069fe40a830SPrabhakar Kushwaha struct regpair rdma_va; 7070fe40a830SPrabhakar Kushwaha __le32 rdma_length; 7071fe40a830SPrabhakar Kushwaha __le32 num_rdb_entries; 7072fe40a830SPrabhakar Kushwaha __le32 resreved; 7073fe40a830SPrabhakar Kushwaha }; 7074fe40a830SPrabhakar Kushwaha 7075fe40a830SPrabhakar Kushwaha /* RoCE RDB array entry */ 7076fe40a830SPrabhakar Kushwaha struct roce_resp_qp_rdb_entry { 7077fe40a830SPrabhakar Kushwaha struct regpair atomic_data; 7078fe40a830SPrabhakar Kushwaha struct regpair va; 7079fe40a830SPrabhakar Kushwaha __le32 psn; 7080fe40a830SPrabhakar Kushwaha __le32 rkey; 7081fe40a830SPrabhakar Kushwaha __le32 byte_count; 7082fe40a830SPrabhakar Kushwaha u8 op_type; 7083fe40a830SPrabhakar Kushwaha u8 reserved[3]; 7084fe40a830SPrabhakar Kushwaha }; 7085fe40a830SPrabhakar Kushwaha 7086fe40a830SPrabhakar Kushwaha /* RoCE Create Suspended QP responder runtime ramrod data */ 7087fe40a830SPrabhakar Kushwaha struct roce_create_suspended_qp_resp_runtime_ramrod_data { 7088fe40a830SPrabhakar Kushwaha struct roce_create_suspended_qp_resp_runtime_params params; 7089fe40a830SPrabhakar Kushwaha struct roce_resp_qp_rdb_entry 7090fe40a830SPrabhakar Kushwaha rdb_array_entries[RDMA_MAX_IRQ_ELEMS_IN_PAGE]; 7091fe40a830SPrabhakar Kushwaha }; 7092fe40a830SPrabhakar Kushwaha 7093fe40a830SPrabhakar Kushwaha /* RoCE Create Suspended QP responder ramrod data */ 7094fe40a830SPrabhakar Kushwaha struct roce_create_suspended_qp_resp_ramrod_data { 7095fe40a830SPrabhakar Kushwaha struct roce_create_qp_resp_ramrod_data 7096fe40a830SPrabhakar Kushwaha qp_params; 7097fe40a830SPrabhakar Kushwaha struct roce_create_suspended_qp_resp_runtime_ramrod_data 7098fe40a830SPrabhakar Kushwaha qp_runtime_params; 7099fe40a830SPrabhakar Kushwaha }; 7100fe40a830SPrabhakar Kushwaha 7101fe40a830SPrabhakar Kushwaha /* RoCE create ud qp ramrod data */ 7102fe40a830SPrabhakar Kushwaha struct roce_create_ud_qp_ramrod_data { 7103fe40a830SPrabhakar Kushwaha __le16 local_mac_addr[3]; 7104fe40a830SPrabhakar Kushwaha __le16 vlan_id; 7105fe40a830SPrabhakar Kushwaha __le32 src_qp_id; 7106fe40a830SPrabhakar Kushwaha u8 name_space; 7107fe40a830SPrabhakar Kushwaha u8 reserved[3]; 7108fe40a830SPrabhakar Kushwaha }; 7109fe40a830SPrabhakar Kushwaha 7110da090917STomer Tayar /* roce DCQCN received statistics */ 7111da090917STomer Tayar struct roce_dcqcn_received_stats { 7112da090917STomer Tayar struct regpair ecn_pkt_rcv; 7113da090917STomer Tayar struct regpair cnp_pkt_rcv; 7114fe40a830SPrabhakar Kushwaha struct regpair cnp_pkt_reject; 7115da090917STomer Tayar }; 7116da090917STomer Tayar 7117da090917STomer Tayar /* roce DCQCN sent statistics */ 7118da090917STomer Tayar struct roce_dcqcn_sent_stats { 7119da090917STomer Tayar struct regpair cnp_pkt_sent; 7120da090917STomer Tayar }; 7121da090917STomer Tayar 7122a2e7699eSTomer Tayar /* RoCE destroy qp requester output params */ 71237a9b6b8fSYuval Mintz struct roce_destroy_qp_req_output_params { 7124be086e7cSMintz, Yuval __le32 cq_prod; 7125d52c89f1SMichal Kalderon __le32 reserved; 71267a9b6b8fSYuval Mintz }; 71277a9b6b8fSYuval Mintz 7128a2e7699eSTomer Tayar /* RoCE destroy qp requester ramrod data */ 71297a9b6b8fSYuval Mintz struct roce_destroy_qp_req_ramrod_data { 71307a9b6b8fSYuval Mintz struct regpair output_params_addr; 71317a9b6b8fSYuval Mintz }; 71327a9b6b8fSYuval Mintz 7133a2e7699eSTomer Tayar /* RoCE destroy qp responder output params */ 71347a9b6b8fSYuval Mintz struct roce_destroy_qp_resp_output_params { 7135be086e7cSMintz, Yuval __le32 cq_prod; 7136d52c89f1SMichal Kalderon __le32 reserved; 71377a9b6b8fSYuval Mintz }; 71387a9b6b8fSYuval Mintz 7139a2e7699eSTomer Tayar /* RoCE destroy qp responder ramrod data */ 71407a9b6b8fSYuval Mintz struct roce_destroy_qp_resp_ramrod_data { 71417a9b6b8fSYuval Mintz struct regpair output_params_addr; 71420500a70dSMichal Kalderon __le32 src_qp_id; 71430500a70dSMichal Kalderon __le32 reserved; 71447a9b6b8fSYuval Mintz }; 71457a9b6b8fSYuval Mintz 7146fe40a830SPrabhakar Kushwaha /* RoCE destroy ud qp ramrod data */ 7147fe40a830SPrabhakar Kushwaha struct roce_destroy_ud_qp_ramrod_data { 7148fe40a830SPrabhakar Kushwaha __le32 src_qp_id; 7149fe40a830SPrabhakar Kushwaha __le32 reserved; 7150fe40a830SPrabhakar Kushwaha }; 7151fe40a830SPrabhakar Kushwaha 7152d52c89f1SMichal Kalderon /* roce error statistics */ 7153d52c89f1SMichal Kalderon struct roce_error_stats { 7154d52c89f1SMichal Kalderon __le32 resp_remote_access_errors; 71557b6859fbSMintz, Yuval __le32 reserved; 71567b6859fbSMintz, Yuval }; 71577b6859fbSMintz, Yuval 7158d52c89f1SMichal Kalderon /* roce special events statistics */ 7159d52c89f1SMichal Kalderon struct roce_events_stats { 7160d52c89f1SMichal Kalderon __le32 silent_drops; 7161d52c89f1SMichal Kalderon __le32 rnr_naks_sent; 7162d52c89f1SMichal Kalderon __le32 retransmit_count; 7163d52c89f1SMichal Kalderon __le32 icrc_error_count; 7164d52c89f1SMichal Kalderon __le32 implied_nak_seq_err; 7165d52c89f1SMichal Kalderon __le32 duplicate_request; 7166d52c89f1SMichal Kalderon __le32 local_ack_timeout_err; 7167d52c89f1SMichal Kalderon __le32 out_of_sequence; 7168d52c89f1SMichal Kalderon __le32 packet_seq_err; 7169d52c89f1SMichal Kalderon __le32 rnr_nak_retry_err; 7170d52c89f1SMichal Kalderon }; 7171d52c89f1SMichal Kalderon 7172d52c89f1SMichal Kalderon /* roce slow path EQ cmd IDs */ 71737a9b6b8fSYuval Mintz enum roce_event_opcode { 7174fe40a830SPrabhakar Kushwaha ROCE_EVENT_CREATE_QP = 13, 71757a9b6b8fSYuval Mintz ROCE_EVENT_MODIFY_QP, 71767a9b6b8fSYuval Mintz ROCE_EVENT_QUERY_QP, 71777a9b6b8fSYuval Mintz ROCE_EVENT_DESTROY_QP, 71787b6859fbSMintz, Yuval ROCE_EVENT_CREATE_UD_QP, 71797b6859fbSMintz, Yuval ROCE_EVENT_DESTROY_UD_QP, 7180a3f72307SDenis Bolotin ROCE_EVENT_FUNC_UPDATE, 7181fe40a830SPrabhakar Kushwaha ROCE_EVENT_SUSPEND_QP, 7182fe40a830SPrabhakar Kushwaha ROCE_EVENT_QUERY_SUSPENDED_QP, 7183fe40a830SPrabhakar Kushwaha ROCE_EVENT_CREATE_SUSPENDED_QP, 7184fe40a830SPrabhakar Kushwaha ROCE_EVENT_RESUME_QP, 7185fe40a830SPrabhakar Kushwaha ROCE_EVENT_SUSPEND_UD_QP, 7186fe40a830SPrabhakar Kushwaha ROCE_EVENT_RESUME_UD_QP, 7187fe40a830SPrabhakar Kushwaha ROCE_EVENT_CREATE_SUSPENDED_UD_QP, 7188fe40a830SPrabhakar Kushwaha ROCE_EVENT_FLUSH_DPT_QP, 71897a9b6b8fSYuval Mintz MAX_ROCE_EVENT_OPCODE 71907a9b6b8fSYuval Mintz }; 71917a9b6b8fSYuval Mintz 7192a2e7699eSTomer Tayar /* roce func init ramrod data */ 71937b6859fbSMintz, Yuval struct roce_init_func_params { 71947b6859fbSMintz, Yuval u8 ll2_queue_id; 71957b6859fbSMintz, Yuval u8 cnp_vlan_priority; 71967b6859fbSMintz, Yuval u8 cnp_dscp; 7197a3f72307SDenis Bolotin u8 flags; 7198a3f72307SDenis Bolotin #define ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_MASK 0x1 7199a3f72307SDenis Bolotin #define ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_SHIFT 0 7200a3f72307SDenis Bolotin #define ROCE_INIT_FUNC_PARAMS_DCQCN_RP_EN_MASK 0x1 7201a3f72307SDenis Bolotin #define ROCE_INIT_FUNC_PARAMS_DCQCN_RP_EN_SHIFT 1 7202a3f72307SDenis Bolotin #define ROCE_INIT_FUNC_PARAMS_RESERVED0_MASK 0x3F 7203a3f72307SDenis Bolotin #define ROCE_INIT_FUNC_PARAMS_RESERVED0_SHIFT 2 72047b6859fbSMintz, Yuval __le32 cnp_send_timeout; 7205d52c89f1SMichal Kalderon __le16 rl_offset; 7206d52c89f1SMichal Kalderon u8 rl_count_log; 7207d52c89f1SMichal Kalderon u8 reserved1[5]; 72087b6859fbSMintz, Yuval }; 72097b6859fbSMintz, Yuval 7210a2e7699eSTomer Tayar /* roce func init ramrod data */ 721105fafbfbSYuval Mintz struct roce_init_func_ramrod_data { 721205fafbfbSYuval Mintz struct rdma_init_func_ramrod_data rdma; 72137b6859fbSMintz, Yuval struct roce_init_func_params roce; 721405fafbfbSYuval Mintz }; 721505fafbfbSYuval Mintz 7216fe40a830SPrabhakar Kushwaha /* roce_ll2_cqe_data */ 7217fe40a830SPrabhakar Kushwaha struct roce_ll2_cqe_data { 7218fe40a830SPrabhakar Kushwaha u8 name_space; 7219fe40a830SPrabhakar Kushwaha u8 flags; 7220fe40a830SPrabhakar Kushwaha #define ROCE_LL2_CQE_DATA_QP_SUSPENDED_MASK 0x1 7221fe40a830SPrabhakar Kushwaha #define ROCE_LL2_CQE_DATA_QP_SUSPENDED_SHIFT 0 7222fe40a830SPrabhakar Kushwaha #define ROCE_LL2_CQE_DATA_RESERVED0_MASK 0x7F 7223fe40a830SPrabhakar Kushwaha #define ROCE_LL2_CQE_DATA_RESERVED0_SHIFT 1 7224fe40a830SPrabhakar Kushwaha u8 reserved1[2]; 7225fe40a830SPrabhakar Kushwaha __le32 cid; 7226fe40a830SPrabhakar Kushwaha }; 7227fe40a830SPrabhakar Kushwaha 7228a2e7699eSTomer Tayar /* roce modify qp requester ramrod data */ 72297a9b6b8fSYuval Mintz struct roce_modify_qp_req_ramrod_data { 72307a9b6b8fSYuval Mintz __le16 flags; 72317a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1 72327a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0 72337a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK 0x1 72347a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT 1 72357a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK 0x1 72367a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT 2 72377a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK 0x1 72387a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT 3 72397a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1 72407a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 4 72417a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK 0x1 72427a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT 5 72437a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK 0x1 72447a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT 6 72457a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK 0x1 72467a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT 7 72477a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK 0x1 72487a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT 8 72497a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK 0x1 72507a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT 9 72517a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK 0x7 72527a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT 10 72530500a70dSMichal Kalderon #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1 72540500a70dSMichal Kalderon #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT 13 7255fe40a830SPrabhakar Kushwaha #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_FORCE_LB_MASK 0x1 7256fe40a830SPrabhakar Kushwaha #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_FORCE_LB_SHIFT 14 7257fe40a830SPrabhakar Kushwaha #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x1 7258fe40a830SPrabhakar Kushwaha #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT 15 72597a9b6b8fSYuval Mintz u8 fields; 72607a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF 72617a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 0 72627a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF 72637a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 4 72647a9b6b8fSYuval Mintz u8 max_ord; 72657a9b6b8fSYuval Mintz u8 traffic_class; 72667a9b6b8fSYuval Mintz u8 hop_limit; 72677a9b6b8fSYuval Mintz __le16 p_key; 72687a9b6b8fSYuval Mintz __le32 flow_label; 72697a9b6b8fSYuval Mintz __le32 ack_timeout_val; 72707a9b6b8fSYuval Mintz __le16 mtu; 72717a9b6b8fSYuval Mintz __le16 reserved2; 7272da090917STomer Tayar __le32 reserved3[2]; 7273da090917STomer Tayar __le16 low_latency_phy_queue; 7274da090917STomer Tayar __le16 regular_latency_phy_queue; 72757a9b6b8fSYuval Mintz __le32 src_gid[4]; 72767a9b6b8fSYuval Mintz __le32 dst_gid[4]; 72777a9b6b8fSYuval Mintz }; 72787a9b6b8fSYuval Mintz 7279a2e7699eSTomer Tayar /* roce modify qp responder ramrod data */ 72807a9b6b8fSYuval Mintz struct roce_modify_qp_resp_ramrod_data { 72817a9b6b8fSYuval Mintz __le16 flags; 72827a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1 72837a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0 72847a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 72857a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 1 72867a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 72877a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 2 72887a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 72897a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 3 72907a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK 0x1 72917a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT 4 72927a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1 72937a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 5 72947a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK 0x1 72957a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT 6 72967a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK 0x1 72977a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT 7 72987a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK 0x1 72997a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT 8 73007a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1 73017a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 9 73020500a70dSMichal Kalderon #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1 73030500a70dSMichal Kalderon #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT 10 7304fe40a830SPrabhakar Kushwaha #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_FORCE_LB_MASK 0x1 7305fe40a830SPrabhakar Kushwaha #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_FORCE_LB_SHIFT 11 7306fe40a830SPrabhakar Kushwaha #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK 0xF 7307fe40a830SPrabhakar Kushwaha #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT 12 73087a9b6b8fSYuval Mintz u8 fields; 73097a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK 0x7 73107a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT 0 73117a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F 73127a9b6b8fSYuval Mintz #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 3 73137a9b6b8fSYuval Mintz u8 max_ird; 73147a9b6b8fSYuval Mintz u8 traffic_class; 73157a9b6b8fSYuval Mintz u8 hop_limit; 73167a9b6b8fSYuval Mintz __le16 p_key; 73177a9b6b8fSYuval Mintz __le32 flow_label; 73187a9b6b8fSYuval Mintz __le16 mtu; 7319da090917STomer Tayar __le16 low_latency_phy_queue; 7320da090917STomer Tayar __le16 regular_latency_phy_queue; 7321da090917STomer Tayar u8 reserved2[6]; 73227a9b6b8fSYuval Mintz __le32 src_gid[4]; 73237a9b6b8fSYuval Mintz __le32 dst_gid[4]; 73247a9b6b8fSYuval Mintz }; 73257a9b6b8fSYuval Mintz 7326a2e7699eSTomer Tayar /* RoCE query qp requester output params */ 73277a9b6b8fSYuval Mintz struct roce_query_qp_req_output_params { 73287a9b6b8fSYuval Mintz __le32 psn; 73297a9b6b8fSYuval Mintz __le32 flags; 73307a9b6b8fSYuval Mintz #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1 73317a9b6b8fSYuval Mintz #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT 0 73327a9b6b8fSYuval Mintz #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK 0x1 73337a9b6b8fSYuval Mintz #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT 1 73347a9b6b8fSYuval Mintz #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x3FFFFFFF 73357a9b6b8fSYuval Mintz #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT 2 73367a9b6b8fSYuval Mintz }; 73377a9b6b8fSYuval Mintz 7338a2e7699eSTomer Tayar /* RoCE query qp requester ramrod data */ 73397a9b6b8fSYuval Mintz struct roce_query_qp_req_ramrod_data { 73407a9b6b8fSYuval Mintz struct regpair output_params_addr; 73417a9b6b8fSYuval Mintz }; 73427a9b6b8fSYuval Mintz 7343a2e7699eSTomer Tayar /* RoCE query qp responder output params */ 73447a9b6b8fSYuval Mintz struct roce_query_qp_resp_output_params { 73457a9b6b8fSYuval Mintz __le32 psn; 73460500a70dSMichal Kalderon __le32 flags; 73477a9b6b8fSYuval Mintz #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1 73487a9b6b8fSYuval Mintz #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0 73497a9b6b8fSYuval Mintz #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF 73507a9b6b8fSYuval Mintz #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT 1 73517a9b6b8fSYuval Mintz }; 73527a9b6b8fSYuval Mintz 7353a2e7699eSTomer Tayar /* RoCE query qp responder ramrod data */ 73547a9b6b8fSYuval Mintz struct roce_query_qp_resp_ramrod_data { 73557a9b6b8fSYuval Mintz struct regpair output_params_addr; 73567a9b6b8fSYuval Mintz }; 73577a9b6b8fSYuval Mintz 7358fe40a830SPrabhakar Kushwaha /* RoCE Query Suspended QP requester output params */ 7359fe40a830SPrabhakar Kushwaha struct roce_query_suspended_qp_req_output_params { 7360fe40a830SPrabhakar Kushwaha __le32 psn; 7361fe40a830SPrabhakar Kushwaha __le32 flags; 7362fe40a830SPrabhakar Kushwaha #define ROCE_QUERY_SUSPENDED_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1 7363fe40a830SPrabhakar Kushwaha #define ROCE_QUERY_SUSPENDED_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT 0 7364fe40a830SPrabhakar Kushwaha #define ROCE_QUERY_SUSPENDED_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF 7365fe40a830SPrabhakar Kushwaha #define ROCE_QUERY_SUSPENDED_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT 1 7366fe40a830SPrabhakar Kushwaha __le32 send_msg_psn; 7367fe40a830SPrabhakar Kushwaha __le32 inflight_sends; 7368fe40a830SPrabhakar Kushwaha __le32 ssn; 7369fe40a830SPrabhakar Kushwaha __le32 reserved; 7370fe40a830SPrabhakar Kushwaha }; 7371fe40a830SPrabhakar Kushwaha 7372fe40a830SPrabhakar Kushwaha /* RoCE Query Suspended QP requester ramrod data */ 7373fe40a830SPrabhakar Kushwaha struct roce_query_suspended_qp_req_ramrod_data { 7374fe40a830SPrabhakar Kushwaha struct regpair output_params_addr; 7375fe40a830SPrabhakar Kushwaha }; 7376fe40a830SPrabhakar Kushwaha 7377fe40a830SPrabhakar Kushwaha /* RoCE Query Suspended QP responder runtime params */ 7378fe40a830SPrabhakar Kushwaha struct roce_query_suspended_qp_resp_runtime_params { 7379fe40a830SPrabhakar Kushwaha __le32 psn; 7380fe40a830SPrabhakar Kushwaha __le32 flags; 7381fe40a830SPrabhakar Kushwaha #define ROCE_QUERY_SUSPENDED_QP_RESP_RUNTIME_PARAMS_ERR_FLG_MASK 0x1 7382fe40a830SPrabhakar Kushwaha #define ROCE_QUERY_SUSPENDED_QP_RESP_RUNTIME_PARAMS_ERR_FLG_SHIFT 0 7383fe40a830SPrabhakar Kushwaha #define ROCE_QUERY_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RDMA_ACTIVE_MASK 0x1 7384fe40a830SPrabhakar Kushwaha #define ROCE_QUERY_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RDMA_ACTIVE_SHIFT 1 7385fe40a830SPrabhakar Kushwaha #define ROCE_QUERY_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RESERVED0_MASK 0x3FFFFFFF 7386fe40a830SPrabhakar Kushwaha #define ROCE_QUERY_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RESERVED0_SHIFT 2 7387fe40a830SPrabhakar Kushwaha __le32 receive_msg_psn; 7388fe40a830SPrabhakar Kushwaha __le32 inflight_receives; 7389fe40a830SPrabhakar Kushwaha __le32 rmsn; 7390fe40a830SPrabhakar Kushwaha __le32 rdma_key; 7391fe40a830SPrabhakar Kushwaha struct regpair rdma_va; 7392fe40a830SPrabhakar Kushwaha __le32 rdma_length; 7393fe40a830SPrabhakar Kushwaha __le32 num_rdb_entries; 7394fe40a830SPrabhakar Kushwaha }; 7395fe40a830SPrabhakar Kushwaha 7396fe40a830SPrabhakar Kushwaha /* RoCE Query Suspended QP responder output params */ 7397fe40a830SPrabhakar Kushwaha struct roce_query_suspended_qp_resp_output_params { 7398fe40a830SPrabhakar Kushwaha struct roce_query_suspended_qp_resp_runtime_params runtime_params; 7399fe40a830SPrabhakar Kushwaha struct roce_resp_qp_rdb_entry 7400fe40a830SPrabhakar Kushwaha rdb_array_entries[RDMA_MAX_IRQ_ELEMS_IN_PAGE]; 7401fe40a830SPrabhakar Kushwaha }; 7402fe40a830SPrabhakar Kushwaha 7403fe40a830SPrabhakar Kushwaha /* RoCE Query Suspended QP responder ramrod data */ 7404fe40a830SPrabhakar Kushwaha struct roce_query_suspended_qp_resp_ramrod_data { 7405fe40a830SPrabhakar Kushwaha struct regpair output_params_addr; 7406fe40a830SPrabhakar Kushwaha }; 7407fe40a830SPrabhakar Kushwaha 7408a2e7699eSTomer Tayar /* ROCE ramrod command IDs */ 74097a9b6b8fSYuval Mintz enum roce_ramrod_cmd_id { 7410fe40a830SPrabhakar Kushwaha ROCE_RAMROD_CREATE_QP = 13, 74117a9b6b8fSYuval Mintz ROCE_RAMROD_MODIFY_QP, 74127a9b6b8fSYuval Mintz ROCE_RAMROD_QUERY_QP, 74137a9b6b8fSYuval Mintz ROCE_RAMROD_DESTROY_QP, 74147b6859fbSMintz, Yuval ROCE_RAMROD_CREATE_UD_QP, 74157b6859fbSMintz, Yuval ROCE_RAMROD_DESTROY_UD_QP, 7416a3f72307SDenis Bolotin ROCE_RAMROD_FUNC_UPDATE, 7417fe40a830SPrabhakar Kushwaha ROCE_RAMROD_SUSPEND_QP, 7418fe40a830SPrabhakar Kushwaha ROCE_RAMROD_QUERY_SUSPENDED_QP, 7419fe40a830SPrabhakar Kushwaha ROCE_RAMROD_CREATE_SUSPENDED_QP, 7420fe40a830SPrabhakar Kushwaha ROCE_RAMROD_RESUME_QP, 7421fe40a830SPrabhakar Kushwaha ROCE_RAMROD_SUSPEND_UD_QP, 7422fe40a830SPrabhakar Kushwaha ROCE_RAMROD_RESUME_UD_QP, 7423fe40a830SPrabhakar Kushwaha ROCE_RAMROD_CREATE_SUSPENDED_UD_QP, 7424fe40a830SPrabhakar Kushwaha ROCE_RAMROD_FLUSH_DPT_QP, 74257a9b6b8fSYuval Mintz MAX_ROCE_RAMROD_CMD_ID 74267a9b6b8fSYuval Mintz }; 74277a9b6b8fSYuval Mintz 7428fe40a830SPrabhakar Kushwaha /* ROCE RDB array entry type */ 7429fe40a830SPrabhakar Kushwaha enum roce_resp_qp_rdb_entry_type { 7430fe40a830SPrabhakar Kushwaha ROCE_QP_RDB_ENTRY_RDMA_RESPONSE = 0, 7431fe40a830SPrabhakar Kushwaha ROCE_QP_RDB_ENTRY_ATOMIC_RESPONSE = 1, 7432fe40a830SPrabhakar Kushwaha ROCE_QP_RDB_ENTRY_INVALID = 2, 7433fe40a830SPrabhakar Kushwaha MAX_ROCE_RESP_QP_RDB_ENTRY_TYPE 7434fe40a830SPrabhakar Kushwaha }; 7435fe40a830SPrabhakar Kushwaha 7436a3f72307SDenis Bolotin /* RoCE func init ramrod data */ 7437a3f72307SDenis Bolotin struct roce_update_func_params { 7438a3f72307SDenis Bolotin u8 cnp_vlan_priority; 7439a3f72307SDenis Bolotin u8 cnp_dscp; 7440a3f72307SDenis Bolotin __le16 flags; 7441a3f72307SDenis Bolotin #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_MASK 0x1 7442a3f72307SDenis Bolotin #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_SHIFT 0 7443a3f72307SDenis Bolotin #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_RP_EN_MASK 0x1 7444a3f72307SDenis Bolotin #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_RP_EN_SHIFT 1 7445a3f72307SDenis Bolotin #define ROCE_UPDATE_FUNC_PARAMS_RESERVED0_MASK 0x3FFF 7446a3f72307SDenis Bolotin #define ROCE_UPDATE_FUNC_PARAMS_RESERVED0_SHIFT 2 7447a3f72307SDenis Bolotin __le32 cnp_send_timeout; 7448a3f72307SDenis Bolotin }; 7449a3f72307SDenis Bolotin 7450fb09a1edSShai Malin struct xstorm_roce_conn_ag_ctx_dq_ext_ld_part { 745150bc60cbSMichal Kalderon u8 reserved0; 745250bc60cbSMichal Kalderon u8 state; 745350bc60cbSMichal Kalderon u8 flags0; 745450bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 745550bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 745650bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1 745750bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT 1 745850bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1 745950bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT 2 746050bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 746150bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 746250bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1 746350bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT 4 746450bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1 746550bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT 5 746650bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1 746750bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT 6 746850bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1 746950bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT 7 747050bc60cbSMichal Kalderon u8 flags1; 747150bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1 747250bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0 747350bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1 747450bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT 1 747550bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1 747650bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2 747750bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 747850bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 74790500a70dSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_MASK 0x1 74800500a70dSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_SHIFT 4 748150bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_MASK 0x1 748250bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_SHIFT 5 74830500a70dSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1 74840500a70dSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT 6 748550bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1 748650bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7 748750bc60cbSMichal Kalderon u8 flags2; 748850bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3 748950bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0 749050bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3 749150bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2 749250bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3 749350bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4 749450bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3 749550bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6 749650bc60cbSMichal Kalderon u8 flags3; 749750bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3 749850bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0 749950bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3 750050bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT 2 750150bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3 750250bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT 4 750350bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3 750450bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6 750550bc60cbSMichal Kalderon u8 flags4; 750650bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3 750750bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0 750850bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3 750950bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2 751050bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3 751150bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4 751250bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3 751350bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6 751450bc60cbSMichal Kalderon u8 flags5; 751550bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3 751650bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0 751750bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3 751850bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2 751950bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3 752050bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT 4 752150bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3 752250bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6 752350bc60cbSMichal Kalderon u8 flags6; 752450bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3 752550bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0 752650bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3 752750bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2 752850bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3 752950bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4 753050bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3 753150bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6 753250bc60cbSMichal Kalderon u8 flags7; 753350bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3 753450bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0 753550bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3 753650bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2 753750bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 753850bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 753950bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 754050bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 754150bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 754250bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 754350bc60cbSMichal Kalderon u8 flags8; 754450bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 754550bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 754650bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 754750bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 754850bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 754950bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2 755050bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 755150bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3 755250bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 755350bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4 755450bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1 755550bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5 755650bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 755750bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 755850bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 755950bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 756050bc60cbSMichal Kalderon u8 flags9; 756150bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 756250bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 756350bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 756450bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 756550bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 756650bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 756750bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 756850bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 756950bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 757050bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4 757150bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 757250bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 757350bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1 757450bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6 757550bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1 757650bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7 757750bc60cbSMichal Kalderon u8 flags10; 757850bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1 757950bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0 758050bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1 758150bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1 758250bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1 758350bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2 758450bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1 758550bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3 758650bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 758750bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 758850bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1 758950bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5 759050bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1 759150bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6 759250bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1 759350bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7 759450bc60cbSMichal Kalderon u8 flags11; 759550bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1 759650bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0 759750bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1 759850bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1 759950bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1 760050bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2 760150bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 760250bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 760350bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 760450bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 760550bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 760650bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5 760750bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 760850bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 760950bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 761050bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 761150bc60cbSMichal Kalderon u8 flags12; 761250bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 761350bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0 761450bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 761550bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 761650bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 761750bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 761850bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 761950bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 762050bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 762150bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4 762250bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 762350bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 762450bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 762550bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6 762650bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 762750bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7 762850bc60cbSMichal Kalderon u8 flags13; 762950bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 763050bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 763150bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 763250bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 763350bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 763450bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 763550bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 763650bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 763750bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 763850bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 763950bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 764050bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 764150bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 764250bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 764350bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 764450bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 764550bc60cbSMichal Kalderon u8 flags14; 764650bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1 764750bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0 764850bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1 764950bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1 765050bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3 765150bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2 765250bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1 765350bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4 765450bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 765550bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 765650bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3 765750bc60cbSMichal Kalderon #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6 765850bc60cbSMichal Kalderon u8 byte2; 765950bc60cbSMichal Kalderon __le16 physical_q0; 766050bc60cbSMichal Kalderon __le16 word1; 766150bc60cbSMichal Kalderon __le16 word2; 766250bc60cbSMichal Kalderon __le16 word3; 766350bc60cbSMichal Kalderon __le16 word4; 766450bc60cbSMichal Kalderon __le16 word5; 766550bc60cbSMichal Kalderon __le16 conn_dpi; 766650bc60cbSMichal Kalderon u8 byte3; 766750bc60cbSMichal Kalderon u8 byte4; 766850bc60cbSMichal Kalderon u8 byte5; 766950bc60cbSMichal Kalderon u8 byte6; 767050bc60cbSMichal Kalderon __le32 reg0; 767150bc60cbSMichal Kalderon __le32 reg1; 767250bc60cbSMichal Kalderon __le32 reg2; 767350bc60cbSMichal Kalderon __le32 snd_nxt_psn; 767450bc60cbSMichal Kalderon __le32 reg4; 767550bc60cbSMichal Kalderon }; 767650bc60cbSMichal Kalderon 7677fb09a1edSShai Malin struct mstorm_roce_conn_ag_ctx { 767850bc60cbSMichal Kalderon u8 byte0; 767950bc60cbSMichal Kalderon u8 byte1; 768050bc60cbSMichal Kalderon u8 flags0; 7681fb09a1edSShai Malin #define MSTORM_ROCE_CONN_AG_CTX_BIT0_MASK 0x1 7682fb09a1edSShai Malin #define MSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT 0 7683fb09a1edSShai Malin #define MSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1 7684fb09a1edSShai Malin #define MSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1 7685fb09a1edSShai Malin #define MSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3 7686fb09a1edSShai Malin #define MSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 2 7687fb09a1edSShai Malin #define MSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3 7688fb09a1edSShai Malin #define MSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT 4 7689fb09a1edSShai Malin #define MSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3 7690fb09a1edSShai Malin #define MSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 6 769150bc60cbSMichal Kalderon u8 flags1; 7692fb09a1edSShai Malin #define MSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1 7693fb09a1edSShai Malin #define MSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 0 7694fb09a1edSShai Malin #define MSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1 7695fb09a1edSShai Malin #define MSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT 1 7696fb09a1edSShai Malin #define MSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1 7697fb09a1edSShai Malin #define MSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 2 7698fb09a1edSShai Malin #define MSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1 7699fb09a1edSShai Malin #define MSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 3 7700fb09a1edSShai Malin #define MSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1 7701fb09a1edSShai Malin #define MSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 4 7702fb09a1edSShai Malin #define MSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1 7703fb09a1edSShai Malin #define MSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 5 7704fb09a1edSShai Malin #define MSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1 7705fb09a1edSShai Malin #define MSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 6 7706fb09a1edSShai Malin #define MSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1 7707fb09a1edSShai Malin #define MSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 7 770850bc60cbSMichal Kalderon __le16 word0; 770950bc60cbSMichal Kalderon __le16 word1; 771050bc60cbSMichal Kalderon __le32 reg0; 771150bc60cbSMichal Kalderon __le32 reg1; 771250bc60cbSMichal Kalderon }; 771350bc60cbSMichal Kalderon 7714fb09a1edSShai Malin struct mstorm_roce_req_conn_ag_ctx { 77157a9b6b8fSYuval Mintz u8 byte0; 77167a9b6b8fSYuval Mintz u8 byte1; 77177a9b6b8fSYuval Mintz u8 flags0; 7718fb09a1edSShai Malin #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 7719fb09a1edSShai Malin #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 7720fb09a1edSShai Malin #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 7721fb09a1edSShai Malin #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 7722fb09a1edSShai Malin #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 7723fb09a1edSShai Malin #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 7724fb09a1edSShai Malin #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 7725fb09a1edSShai Malin #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 7726fb09a1edSShai Malin #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 7727fb09a1edSShai Malin #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 77287a9b6b8fSYuval Mintz u8 flags1; 7729fb09a1edSShai Malin #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 7730fb09a1edSShai Malin #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 7731fb09a1edSShai Malin #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 7732fb09a1edSShai Malin #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 7733fb09a1edSShai Malin #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 7734fb09a1edSShai Malin #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 7735fb09a1edSShai Malin #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 7736fb09a1edSShai Malin #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3 7737fb09a1edSShai Malin #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 7738fb09a1edSShai Malin #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4 7739fb09a1edSShai Malin #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 7740fb09a1edSShai Malin #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5 7741fb09a1edSShai Malin #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 7742fb09a1edSShai Malin #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6 7743fb09a1edSShai Malin #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 7744fb09a1edSShai Malin #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7 77457a9b6b8fSYuval Mintz __le16 word0; 77467a9b6b8fSYuval Mintz __le16 word1; 77477a9b6b8fSYuval Mintz __le32 reg0; 77487a9b6b8fSYuval Mintz __le32 reg1; 77497a9b6b8fSYuval Mintz }; 77507a9b6b8fSYuval Mintz 7751fb09a1edSShai Malin struct mstorm_roce_resp_conn_ag_ctx { 77527a9b6b8fSYuval Mintz u8 byte0; 77537a9b6b8fSYuval Mintz u8 byte1; 77547a9b6b8fSYuval Mintz u8 flags0; 7755fb09a1edSShai Malin #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 7756fb09a1edSShai Malin #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 7757fb09a1edSShai Malin #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 7758fb09a1edSShai Malin #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 7759fb09a1edSShai Malin #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 7760fb09a1edSShai Malin #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 7761fb09a1edSShai Malin #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 7762fb09a1edSShai Malin #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 7763fb09a1edSShai Malin #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 7764fb09a1edSShai Malin #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 77657a9b6b8fSYuval Mintz u8 flags1; 7766fb09a1edSShai Malin #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 7767fb09a1edSShai Malin #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 7768fb09a1edSShai Malin #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 7769fb09a1edSShai Malin #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 7770fb09a1edSShai Malin #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 7771fb09a1edSShai Malin #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 7772fb09a1edSShai Malin #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 7773fb09a1edSShai Malin #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3 7774fb09a1edSShai Malin #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 7775fb09a1edSShai Malin #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4 7776fb09a1edSShai Malin #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 7777fb09a1edSShai Malin #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5 7778fb09a1edSShai Malin #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 7779fb09a1edSShai Malin #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6 7780fb09a1edSShai Malin #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 7781fb09a1edSShai Malin #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7 77827a9b6b8fSYuval Mintz __le16 word0; 77837a9b6b8fSYuval Mintz __le16 word1; 77847a9b6b8fSYuval Mintz __le32 reg0; 77857a9b6b8fSYuval Mintz __le32 reg1; 77867a9b6b8fSYuval Mintz }; 77877a9b6b8fSYuval Mintz 7788fb09a1edSShai Malin struct tstorm_roce_req_conn_ag_ctx { 77897a9b6b8fSYuval Mintz u8 reserved0; 77907a9b6b8fSYuval Mintz u8 state; 77917a9b6b8fSYuval Mintz u8 flags0; 7792fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 7793fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 7794fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_MASK 0x1 7795fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_SHIFT 1 7796fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_MASK 0x1 7797fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_SHIFT 2 7798fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1 7799fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT 3 7800fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 7801fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4 7802fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 7803fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT 5 7804fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3 7805fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6 78067a9b6b8fSYuval Mintz u8 flags1; 7807fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 7808fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 7809fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3 7810fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2 7811fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 7812fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 7813fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 7814fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 78157a9b6b8fSYuval Mintz u8 flags2; 7816fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_MASK 0x3 7817fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_SHIFT 0 7818fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3 7819fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2 7820fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3 7821fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT 4 7822fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3 7823fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT 6 78247a9b6b8fSYuval Mintz u8 flags3; 7825fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3 7826fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0 7827fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3 7828fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2 7829fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1 7830fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4 7831fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 7832fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 5 7833fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1 7834fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6 7835fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 7836fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 78377a9b6b8fSYuval Mintz u8 flags4; 7838fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 7839fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 7840fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_EN_MASK 0x1 7841fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_EN_SHIFT 1 7842fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1 7843fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2 7844fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1 7845fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT 3 7846fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1 7847fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT 4 7848fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1 7849fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5 7850fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1 7851fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT 6 7852fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 7853fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7 78547a9b6b8fSYuval Mintz u8 flags5; 7855fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 7856fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0 7857fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_DIF_CNT_EN_MASK 0x1 7858fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_DIF_CNT_EN_SHIFT 1 7859fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 7860fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2 7861fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 7862fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3 7863fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 7864fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4 7865fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1 7866fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT 5 7867fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 7868fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6 7869fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 7870fb09a1edSShai Malin #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7 78710500a70dSMichal Kalderon __le32 dif_rxmit_cnt; 78727a9b6b8fSYuval Mintz __le32 snd_nxt_psn; 78737a9b6b8fSYuval Mintz __le32 snd_max_psn; 78747a9b6b8fSYuval Mintz __le32 orq_prod; 78757a9b6b8fSYuval Mintz __le32 reg4; 78760500a70dSMichal Kalderon __le32 dif_acked_cnt; 78770500a70dSMichal Kalderon __le32 dif_cnt; 78787a9b6b8fSYuval Mintz __le32 reg7; 78797a9b6b8fSYuval Mintz __le32 reg8; 78807a9b6b8fSYuval Mintz u8 tx_cqe_error_type; 78817a9b6b8fSYuval Mintz u8 orq_cache_idx; 78827a9b6b8fSYuval Mintz __le16 snd_sq_cons_th; 78837a9b6b8fSYuval Mintz u8 byte4; 78847a9b6b8fSYuval Mintz u8 byte5; 78857a9b6b8fSYuval Mintz __le16 snd_sq_cons; 7886da090917STomer Tayar __le16 conn_dpi; 788750bc60cbSMichal Kalderon __le16 force_comp_cons; 78880500a70dSMichal Kalderon __le32 dif_rxmit_acked_cnt; 78897a9b6b8fSYuval Mintz __le32 reg10; 78907a9b6b8fSYuval Mintz }; 78917a9b6b8fSYuval Mintz 7892fb09a1edSShai Malin struct tstorm_roce_resp_conn_ag_ctx { 78937a9b6b8fSYuval Mintz u8 byte0; 78947a9b6b8fSYuval Mintz u8 state; 78957a9b6b8fSYuval Mintz u8 flags0; 7896fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 7897fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 7898fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK 0x1 7899fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT 1 7900fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1 7901fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT 2 7902fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1 7903fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT 3 7904fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 7905fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4 7906fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1 7907fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT 5 7908fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 7909fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6 79107a9b6b8fSYuval Mintz u8 flags1; 7911fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 7912fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 7913fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3 7914fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2 7915fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 7916fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 4 7917fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 7918fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 79197a9b6b8fSYuval Mintz u8 flags2; 7920fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 7921fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0 7922fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 7923fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2 7924fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3 7925fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT 4 7926fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 7927fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 6 79287a9b6b8fSYuval Mintz u8 flags3; 7929fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 7930fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0 7931fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 7932fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2 7933fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 7934fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4 7935fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 7936fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 5 7937fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1 7938fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6 7939fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 7940fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 7 79417a9b6b8fSYuval Mintz u8 flags4; 7942fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 7943fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 7944fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 7945fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 1 7946fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 7947fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2 7948fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1 7949fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT 3 7950fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 7951fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 4 7952fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 7953fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 5 7954fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 7955fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 6 7956fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 7957fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7 79587a9b6b8fSYuval Mintz u8 flags5; 7959fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 7960fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0 7961fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 7962fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1 7963fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 7964fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2 7965fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 7966fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3 7967fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 7968fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4 7969fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1 7970fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT 5 7971fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 7972fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6 7973fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 7974fb09a1edSShai Malin #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7 79757a9b6b8fSYuval Mintz __le32 psn_and_rxmit_id_echo; 79767a9b6b8fSYuval Mintz __le32 reg1; 79777a9b6b8fSYuval Mintz __le32 reg2; 79787a9b6b8fSYuval Mintz __le32 reg3; 79797a9b6b8fSYuval Mintz __le32 reg4; 79807a9b6b8fSYuval Mintz __le32 reg5; 79817a9b6b8fSYuval Mintz __le32 reg6; 79827a9b6b8fSYuval Mintz __le32 reg7; 79837a9b6b8fSYuval Mintz __le32 reg8; 79847a9b6b8fSYuval Mintz u8 tx_async_error_type; 79857a9b6b8fSYuval Mintz u8 byte3; 79867a9b6b8fSYuval Mintz __le16 rq_cons; 79877a9b6b8fSYuval Mintz u8 byte4; 79887a9b6b8fSYuval Mintz u8 byte5; 79897a9b6b8fSYuval Mintz __le16 rq_prod; 79907a9b6b8fSYuval Mintz __le16 conn_dpi; 79917a9b6b8fSYuval Mintz __le16 irq_cons; 7992d52c89f1SMichal Kalderon __le32 reg9; 79937a9b6b8fSYuval Mintz __le32 reg10; 79947a9b6b8fSYuval Mintz }; 79957a9b6b8fSYuval Mintz 7996fb09a1edSShai Malin struct ustorm_roce_req_conn_ag_ctx { 79977a9b6b8fSYuval Mintz u8 byte0; 79987a9b6b8fSYuval Mintz u8 byte1; 79997a9b6b8fSYuval Mintz u8 flags0; 8000fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 8001fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 8002fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 8003fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 8004fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 8005fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 8006fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 8007fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 8008fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 8009fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 80107a9b6b8fSYuval Mintz u8 flags1; 8011fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 8012fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0 8013fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3 8014fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT 2 8015fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3 8016fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT 4 8017fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3 8018fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT 6 80197a9b6b8fSYuval Mintz u8 flags2; 8020fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 8021fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 8022fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 8023fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 8024fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 8025fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 8026fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 8027fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 3 8028fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1 8029fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT 4 8030fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1 8031fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT 5 8032fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1 8033fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT 6 8034fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 8035fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7 80367a9b6b8fSYuval Mintz u8 flags3; 8037fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 8038fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0 8039fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 8040fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1 8041fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 8042fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2 8043fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 8044fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3 8045fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 8046fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4 8047fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 8048fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5 8049fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 8050fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6 8051fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 8052fb09a1edSShai Malin #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7 80537a9b6b8fSYuval Mintz u8 byte2; 80547a9b6b8fSYuval Mintz u8 byte3; 80557a9b6b8fSYuval Mintz __le16 word0; 80567a9b6b8fSYuval Mintz __le16 word1; 80577a9b6b8fSYuval Mintz __le32 reg0; 80587a9b6b8fSYuval Mintz __le32 reg1; 80597a9b6b8fSYuval Mintz __le32 reg2; 80607a9b6b8fSYuval Mintz __le32 reg3; 80617a9b6b8fSYuval Mintz __le16 word2; 80627a9b6b8fSYuval Mintz __le16 word3; 80637a9b6b8fSYuval Mintz }; 80647a9b6b8fSYuval Mintz 8065fb09a1edSShai Malin struct ustorm_roce_resp_conn_ag_ctx { 80667a9b6b8fSYuval Mintz u8 byte0; 80677a9b6b8fSYuval Mintz u8 byte1; 80687a9b6b8fSYuval Mintz u8 flags0; 8069fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 8070fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 8071fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 8072fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 8073fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 8074fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 8075fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 8076fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 8077fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 8078fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 80797a9b6b8fSYuval Mintz u8 flags1; 8080fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 8081fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0 8082fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3 8083fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT 2 8084fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3 8085fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT 4 8086fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 8087fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 6 80887a9b6b8fSYuval Mintz u8 flags2; 8089fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 8090fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 8091fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 8092fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 8093fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 8094fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 8095fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 8096fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 3 8097fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1 8098fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT 4 8099fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1 8100fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT 5 8101fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 8102fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 6 8103fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 8104fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7 81057a9b6b8fSYuval Mintz u8 flags3; 8106fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 8107fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0 8108fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 8109fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1 8110fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 8111fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2 8112fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 8113fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3 8114fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 8115fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4 8116fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 8117fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5 8118fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 8119fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6 8120fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 8121fb09a1edSShai Malin #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7 81227a9b6b8fSYuval Mintz u8 byte2; 81237a9b6b8fSYuval Mintz u8 byte3; 81247a9b6b8fSYuval Mintz __le16 word0; 81257a9b6b8fSYuval Mintz __le16 word1; 81267a9b6b8fSYuval Mintz __le32 reg0; 81277a9b6b8fSYuval Mintz __le32 reg1; 81287a9b6b8fSYuval Mintz __le32 reg2; 81297a9b6b8fSYuval Mintz __le32 reg3; 81307a9b6b8fSYuval Mintz __le16 word2; 81317a9b6b8fSYuval Mintz __le16 word3; 81327a9b6b8fSYuval Mintz }; 81337a9b6b8fSYuval Mintz 8134fb09a1edSShai Malin struct xstorm_roce_req_conn_ag_ctx { 81357a9b6b8fSYuval Mintz u8 reserved0; 81367a9b6b8fSYuval Mintz u8 state; 81377a9b6b8fSYuval Mintz u8 flags0; 8138fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 8139fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 8140fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1 8141fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT 1 8142fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1 8143fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT 2 8144fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 8145fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 8146fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1 8147fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT 4 8148fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1 8149fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT 5 8150fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1 8151fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT 6 8152fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1 8153fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT 7 81547a9b6b8fSYuval Mintz u8 flags1; 8155fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1 8156fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0 8157fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1 8158fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT 1 8159fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1 8160fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2 8161fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1 8162fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3 8163fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1 8164fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_MSDM_FLUSH_SHIFT 4 8165fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1 8166fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_MSEM_FLUSH_SHIFT 5 8167fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1 8168fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6 8169fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 8170fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 81717a9b6b8fSYuval Mintz u8 flags2; 8172fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 8173fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0 8174fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 8175fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 2 8176fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 8177fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 4 8178fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 8179fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 6 81807a9b6b8fSYuval Mintz u8 flags3; 8181fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 8182fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0 8183fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 8184fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2 8185fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3 8186fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 4 8187fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 8188fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 81897a9b6b8fSYuval Mintz u8 flags4; 8190fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_MASK 0x3 8191fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_SHIFT 0 8192fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_MASK 0x3 8193fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_SHIFT 2 8194fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3 8195fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4 8196fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3 8197fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT 6 81987a9b6b8fSYuval Mintz u8 flags5; 8199fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3 8200fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0 8201fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3 8202fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT 2 8203fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3 8204fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT 4 8205fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3 8206fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT 6 82077a9b6b8fSYuval Mintz u8 flags6; 8208fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3 8209fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0 8210fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3 8211fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT 2 8212fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3 8213fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT 4 8214fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3 8215fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT 6 82167a9b6b8fSYuval Mintz u8 flags7; 8217fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3 8218fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0 8219fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3 8220fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT 2 8221fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3 8222fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT 4 8223fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 8224fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 6 8225fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 8226fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 7 82277a9b6b8fSYuval Mintz u8 flags8; 8228fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 8229fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0 8230fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 8231fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 1 8232fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 8233fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 2 8234fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 8235fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3 8236fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1 8237fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4 8238fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 8239fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 8240fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 8241fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_EN_SHIFT 6 8242fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_EN_MASK 0x1 8243fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_EN_SHIFT 7 82447a9b6b8fSYuval Mintz u8 flags9; 8245fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1 8246fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0 8247fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1 8248fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT 1 8249fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1 8250fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT 2 8251fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1 8252fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT 3 8253fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1 8254fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT 4 8255fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1 8256fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT 5 8257fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1 8258fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT 6 8259fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1 8260fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT 7 82617a9b6b8fSYuval Mintz u8 flags10; 8262fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1 8263fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0 8264fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1 8265fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT 1 8266fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1 8267fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT 2 8268fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1 8269fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT 3 8270fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 8271fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 8272fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1 8273fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT 5 8274fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 8275fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 6 8276fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 8277fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 7 82787a9b6b8fSYuval Mintz u8 flags11; 8279fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 8280fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0 8281fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 8282fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 1 8283fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 8284fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 2 8285fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 8286fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 3 8287fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 8288fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 4 8289fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1 8290fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5 8291fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 8292fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 8293fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1 8294fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT 7 82957a9b6b8fSYuval Mintz u8 flags12; 8296fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1 8297fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0 8298fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1 8299fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT 1 8300fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 8301fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 8302fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 8303fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 8304fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1 8305fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT 4 8306fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1 8307fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT 5 8308fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1 8309fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT 6 8310fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1 8311fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT 7 83127a9b6b8fSYuval Mintz u8 flags13; 8313fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1 8314fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0 8315fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1 8316fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT 1 8317fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 8318fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 8319fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 8320fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 8321fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 8322fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 8323fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 8324fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 8325fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 8326fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 8327fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 8328fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 83297a9b6b8fSYuval Mintz u8 flags14; 8330fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1 8331fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0 8332fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1 8333fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT 1 8334fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 8335fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 8336fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1 8337fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT 4 8338fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 8339fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 8340fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3 8341fb09a1edSShai Malin #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT 6 83427a9b6b8fSYuval Mintz u8 byte2; 83437a9b6b8fSYuval Mintz __le16 physical_q0; 83447a9b6b8fSYuval Mintz __le16 word1; 83457a9b6b8fSYuval Mintz __le16 sq_cmp_cons; 83467a9b6b8fSYuval Mintz __le16 sq_cons; 83477a9b6b8fSYuval Mintz __le16 sq_prod; 834850bc60cbSMichal Kalderon __le16 dif_error_first_sq_cons; 83497a9b6b8fSYuval Mintz __le16 conn_dpi; 835050bc60cbSMichal Kalderon u8 dif_error_sge_index; 83517a9b6b8fSYuval Mintz u8 byte4; 83527a9b6b8fSYuval Mintz u8 byte5; 83537a9b6b8fSYuval Mintz u8 byte6; 83547a9b6b8fSYuval Mintz __le32 lsn; 83557a9b6b8fSYuval Mintz __le32 ssn; 83567a9b6b8fSYuval Mintz __le32 snd_una_psn; 83577a9b6b8fSYuval Mintz __le32 snd_nxt_psn; 835850bc60cbSMichal Kalderon __le32 dif_error_offset; 83597a9b6b8fSYuval Mintz __le32 orq_cons_th; 83607a9b6b8fSYuval Mintz __le32 orq_cons; 83617a9b6b8fSYuval Mintz }; 83627a9b6b8fSYuval Mintz 8363fb09a1edSShai Malin struct xstorm_roce_resp_conn_ag_ctx { 83647a9b6b8fSYuval Mintz u8 reserved0; 83657a9b6b8fSYuval Mintz u8 state; 83667a9b6b8fSYuval Mintz u8 flags0; 8367fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 8368fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 8369fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1 8370fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT 1 8371fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1 8372fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT 2 8373fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 8374fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 8375fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1 8376fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT 4 8377fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1 8378fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT 5 8379fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1 8380fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT 6 8381fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1 8382fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT 7 83837a9b6b8fSYuval Mintz u8 flags1; 8384fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1 8385fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0 8386fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1 8387fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT 1 8388fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1 8389fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2 8390fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1 8391fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3 8392fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1 8393fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_MSDM_FLUSH_SHIFT 4 8394fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1 8395fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_MSEM_FLUSH_SHIFT 5 8396fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1 8397fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6 8398fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 8399fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 84007a9b6b8fSYuval Mintz u8 flags2; 8401fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 8402fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0 8403fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 8404fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 2 8405fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 8406fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 4 8407fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 8408fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 6 84097a9b6b8fSYuval Mintz u8 flags3; 8410fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3 8411fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0 8412fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 8413fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2 8414fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3 8415fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 4 8416fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 8417fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 84187a9b6b8fSYuval Mintz u8 flags4; 8419fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 8420fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0 8421fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 8422fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 2 8423fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 8424fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 4 8425fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3 8426fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT 6 84277a9b6b8fSYuval Mintz u8 flags5; 8428fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3 8429fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0 8430fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3 8431fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT 2 8432fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3 8433fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT 4 8434fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3 8435fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT 6 84367a9b6b8fSYuval Mintz u8 flags6; 8437fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3 8438fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0 8439fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3 8440fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT 2 8441fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3 8442fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT 4 8443fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3 8444fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT 6 84457a9b6b8fSYuval Mintz u8 flags7; 8446fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3 8447fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0 8448fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3 8449fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT 2 8450fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 8451fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4 8452fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 8453fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 6 8454fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 8455fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 7 84567a9b6b8fSYuval Mintz u8 flags8; 8457fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 8458fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0 8459fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 8460fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 1 8461fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1 8462fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT 2 8463fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 8464fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3 8465fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1 8466fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 4 8467fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 8468fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 8469fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 8470fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 6 8471fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 8472fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 7 84737a9b6b8fSYuval Mintz u8 flags9; 8474fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 8475fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0 8476fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1 8477fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT 1 8478fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1 8479fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT 2 8480fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1 8481fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT 3 8482fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1 8483fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT 4 8484fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1 8485fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT 5 8486fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1 8487fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT 6 8488fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1 8489fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT 7 84907a9b6b8fSYuval Mintz u8 flags10; 8491fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1 8492fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0 8493fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1 8494fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT 1 8495fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1 8496fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT 2 8497fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1 8498fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT 3 8499fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 8500fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 8501fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1 8502fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT 5 8503fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 8504fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 6 8505fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 8506fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 7 85077a9b6b8fSYuval Mintz u8 flags11; 8508fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 8509fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0 8510fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 8511fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 1 8512fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 8513fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 2 8514fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 8515fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 3 8516fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 8517fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 4 8518fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 8519fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 5 8520fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 8521fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 8522fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1 8523fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT 7 85247a9b6b8fSYuval Mintz u8 flags12; 8525fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1 8526fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 0 8527fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_MASK 0x1 8528fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_SHIFT 1 8529fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 8530fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 8531fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 8532fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 8533fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1 8534fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT 4 8535fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1 8536fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT 5 8537fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1 8538fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT 6 8539fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1 8540fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT 7 85417a9b6b8fSYuval Mintz u8 flags13; 8542fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1 8543fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0 8544fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1 8545fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT 1 8546fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 8547fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 8548fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 8549fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 8550fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 8551fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 8552fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 8553fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 8554fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 8555fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 8556fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 8557fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 85587a9b6b8fSYuval Mintz u8 flags14; 8559fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1 8560fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0 8561fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1 8562fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT 1 8563fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1 8564fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT 2 8565fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1 8566fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT 3 8567fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1 8568fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT 4 8569fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1 8570fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT 5 8571fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3 8572fb09a1edSShai Malin #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT 6 85737a9b6b8fSYuval Mintz u8 byte2; 85747a9b6b8fSYuval Mintz __le16 physical_q0; 8575da090917STomer Tayar __le16 irq_prod_shadow; 8576da090917STomer Tayar __le16 word2; 85777a9b6b8fSYuval Mintz __le16 irq_cons; 8578da090917STomer Tayar __le16 irq_prod; 8579da090917STomer Tayar __le16 e5_reserved1; 8580da090917STomer Tayar __le16 conn_dpi; 85817a9b6b8fSYuval Mintz u8 rxmit_opcode; 85827a9b6b8fSYuval Mintz u8 byte4; 85837a9b6b8fSYuval Mintz u8 byte5; 85847a9b6b8fSYuval Mintz u8 byte6; 85857a9b6b8fSYuval Mintz __le32 rxmit_psn_and_id; 85867a9b6b8fSYuval Mintz __le32 rxmit_bytes_length; 85877a9b6b8fSYuval Mintz __le32 psn; 85887a9b6b8fSYuval Mintz __le32 reg3; 85897a9b6b8fSYuval Mintz __le32 reg4; 85907a9b6b8fSYuval Mintz __le32 reg5; 85917a9b6b8fSYuval Mintz __le32 msn_and_syndrome; 85927a9b6b8fSYuval Mintz }; 85937a9b6b8fSYuval Mintz 8594fb09a1edSShai Malin struct ystorm_roce_conn_ag_ctx { 859550bc60cbSMichal Kalderon u8 byte0; 859650bc60cbSMichal Kalderon u8 byte1; 859750bc60cbSMichal Kalderon u8 flags0; 8598fb09a1edSShai Malin #define YSTORM_ROCE_CONN_AG_CTX_BIT0_MASK 0x1 8599fb09a1edSShai Malin #define YSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT 0 8600fb09a1edSShai Malin #define YSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1 8601fb09a1edSShai Malin #define YSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1 8602fb09a1edSShai Malin #define YSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3 8603fb09a1edSShai Malin #define YSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 2 8604fb09a1edSShai Malin #define YSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3 8605fb09a1edSShai Malin #define YSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT 4 8606fb09a1edSShai Malin #define YSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3 8607fb09a1edSShai Malin #define YSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 6 860850bc60cbSMichal Kalderon u8 flags1; 8609fb09a1edSShai Malin #define YSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1 8610fb09a1edSShai Malin #define YSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 0 8611fb09a1edSShai Malin #define YSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1 8612fb09a1edSShai Malin #define YSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT 1 8613fb09a1edSShai Malin #define YSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1 8614fb09a1edSShai Malin #define YSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 2 8615fb09a1edSShai Malin #define YSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1 8616fb09a1edSShai Malin #define YSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 3 8617fb09a1edSShai Malin #define YSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1 8618fb09a1edSShai Malin #define YSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 4 8619fb09a1edSShai Malin #define YSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1 8620fb09a1edSShai Malin #define YSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 5 8621fb09a1edSShai Malin #define YSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1 8622fb09a1edSShai Malin #define YSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 6 8623fb09a1edSShai Malin #define YSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1 8624fb09a1edSShai Malin #define YSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 7 862550bc60cbSMichal Kalderon u8 byte2; 862650bc60cbSMichal Kalderon u8 byte3; 862750bc60cbSMichal Kalderon __le16 word0; 862850bc60cbSMichal Kalderon __le32 reg0; 862950bc60cbSMichal Kalderon __le32 reg1; 863050bc60cbSMichal Kalderon __le16 word1; 863150bc60cbSMichal Kalderon __le16 word2; 863250bc60cbSMichal Kalderon __le16 word3; 863350bc60cbSMichal Kalderon __le16 word4; 863450bc60cbSMichal Kalderon __le32 reg2; 863550bc60cbSMichal Kalderon __le32 reg3; 863650bc60cbSMichal Kalderon }; 863750bc60cbSMichal Kalderon 8638fb09a1edSShai Malin struct ystorm_roce_req_conn_ag_ctx { 86397a9b6b8fSYuval Mintz u8 byte0; 86407a9b6b8fSYuval Mintz u8 byte1; 86417a9b6b8fSYuval Mintz u8 flags0; 8642fb09a1edSShai Malin #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 8643fb09a1edSShai Malin #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 8644fb09a1edSShai Malin #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 8645fb09a1edSShai Malin #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 8646fb09a1edSShai Malin #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 8647fb09a1edSShai Malin #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 8648fb09a1edSShai Malin #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 8649fb09a1edSShai Malin #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 8650fb09a1edSShai Malin #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 8651fb09a1edSShai Malin #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 86527a9b6b8fSYuval Mintz u8 flags1; 8653fb09a1edSShai Malin #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 8654fb09a1edSShai Malin #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 8655fb09a1edSShai Malin #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 8656fb09a1edSShai Malin #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 8657fb09a1edSShai Malin #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 8658fb09a1edSShai Malin #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 8659fb09a1edSShai Malin #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 8660fb09a1edSShai Malin #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3 8661fb09a1edSShai Malin #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 8662fb09a1edSShai Malin #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4 8663fb09a1edSShai Malin #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 8664fb09a1edSShai Malin #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5 8665fb09a1edSShai Malin #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 8666fb09a1edSShai Malin #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6 8667fb09a1edSShai Malin #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 8668fb09a1edSShai Malin #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7 86697a9b6b8fSYuval Mintz u8 byte2; 86707a9b6b8fSYuval Mintz u8 byte3; 86717a9b6b8fSYuval Mintz __le16 word0; 86727a9b6b8fSYuval Mintz __le32 reg0; 86737a9b6b8fSYuval Mintz __le32 reg1; 86747a9b6b8fSYuval Mintz __le16 word1; 86757a9b6b8fSYuval Mintz __le16 word2; 86767a9b6b8fSYuval Mintz __le16 word3; 86777a9b6b8fSYuval Mintz __le16 word4; 86787a9b6b8fSYuval Mintz __le32 reg2; 86797a9b6b8fSYuval Mintz __le32 reg3; 86807a9b6b8fSYuval Mintz }; 86817a9b6b8fSYuval Mintz 8682fb09a1edSShai Malin struct ystorm_roce_resp_conn_ag_ctx { 86837a9b6b8fSYuval Mintz u8 byte0; 86847a9b6b8fSYuval Mintz u8 byte1; 86857a9b6b8fSYuval Mintz u8 flags0; 8686fb09a1edSShai Malin #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 8687fb09a1edSShai Malin #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 8688fb09a1edSShai Malin #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 8689fb09a1edSShai Malin #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 8690fb09a1edSShai Malin #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 8691fb09a1edSShai Malin #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 8692fb09a1edSShai Malin #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 8693fb09a1edSShai Malin #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 8694fb09a1edSShai Malin #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 8695fb09a1edSShai Malin #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 86967a9b6b8fSYuval Mintz u8 flags1; 8697fb09a1edSShai Malin #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 8698fb09a1edSShai Malin #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 8699fb09a1edSShai Malin #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 8700fb09a1edSShai Malin #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 8701fb09a1edSShai Malin #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 8702fb09a1edSShai Malin #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 8703fb09a1edSShai Malin #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 8704fb09a1edSShai Malin #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3 8705fb09a1edSShai Malin #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 8706fb09a1edSShai Malin #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4 8707fb09a1edSShai Malin #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 8708fb09a1edSShai Malin #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5 8709fb09a1edSShai Malin #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 8710fb09a1edSShai Malin #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6 8711fb09a1edSShai Malin #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 8712fb09a1edSShai Malin #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7 87137a9b6b8fSYuval Mintz u8 byte2; 87147a9b6b8fSYuval Mintz u8 byte3; 87157a9b6b8fSYuval Mintz __le16 word0; 87167a9b6b8fSYuval Mintz __le32 reg0; 87177a9b6b8fSYuval Mintz __le32 reg1; 87187a9b6b8fSYuval Mintz __le16 word1; 87197a9b6b8fSYuval Mintz __le16 word2; 87207a9b6b8fSYuval Mintz __le16 word3; 87217a9b6b8fSYuval Mintz __le16 word4; 87227a9b6b8fSYuval Mintz __le32 reg2; 87237a9b6b8fSYuval Mintz __le32 reg3; 87247a9b6b8fSYuval Mintz }; 87257a9b6b8fSYuval Mintz 8726a2e7699eSTomer Tayar /* Roce doorbell data */ 87277b6859fbSMintz, Yuval enum roce_flavor { 87287b6859fbSMintz, Yuval PLAIN_ROCE, 87297b6859fbSMintz, Yuval RROCE_IPV4, 87307b6859fbSMintz, Yuval RROCE_IPV6, 87317b6859fbSMintz, Yuval MAX_ROCE_FLAVOR 87327b6859fbSMintz, Yuval }; 87337b6859fbSMintz, Yuval 8734a2e7699eSTomer Tayar /* The iwarp storm context of Ystorm */ 87357b6859fbSMintz, Yuval struct ystorm_iwarp_conn_st_ctx { 87367b6859fbSMintz, Yuval __le32 reserved[4]; 87377b6859fbSMintz, Yuval }; 87387b6859fbSMintz, Yuval 8739a2e7699eSTomer Tayar /* The iwarp storm context of Pstorm */ 87407b6859fbSMintz, Yuval struct pstorm_iwarp_conn_st_ctx { 87417b6859fbSMintz, Yuval __le32 reserved[36]; 87427b6859fbSMintz, Yuval }; 87437b6859fbSMintz, Yuval 8744a2e7699eSTomer Tayar /* The iwarp storm context of Xstorm */ 87457b6859fbSMintz, Yuval struct xstorm_iwarp_conn_st_ctx { 874650bc60cbSMichal Kalderon __le32 reserved[48]; 87477b6859fbSMintz, Yuval }; 87487b6859fbSMintz, Yuval 8749fb09a1edSShai Malin struct xstorm_iwarp_conn_ag_ctx { 87507b6859fbSMintz, Yuval u8 reserved0; 87517b6859fbSMintz, Yuval u8 state; 87527b6859fbSMintz, Yuval u8 flags0; 8753fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 8754fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 8755fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1 8756fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1 8757fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_MASK 0x1 8758fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_SHIFT 2 8759fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 8760fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 8761fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1 8762fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4 8763fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK 0x1 8764fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_RESERVED2_SHIFT 5 8765fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK 0x1 8766fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_BIT6_SHIFT 6 8767fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK 0x1 8768fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_BIT7_SHIFT 7 87697b6859fbSMintz, Yuval u8 flags1; 8770fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK 0x1 8771fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT 0 8772fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK 0x1 8773fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_BIT9_SHIFT 1 8774fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK 0x1 8775fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_BIT10_SHIFT 2 8776fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK 0x1 8777fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_BIT11_SHIFT 3 8778fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK 0x1 8779fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_BIT12_SHIFT 4 8780fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK 0x1 8781fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_BIT13_SHIFT 5 8782fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK 0x1 8783fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_BIT14_SHIFT 6 8784fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK 0x1 8785fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_SHIFT 7 87867b6859fbSMintz, Yuval u8 flags2; 8787fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 8788fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 0 8789fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 8790fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 2 8791fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 8792fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 4 8793fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 8794fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6 87957b6859fbSMintz, Yuval u8 flags3; 8796fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 8797fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 0 8798fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 8799fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 2 8800fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 8801fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 4 8802fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 8803fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 6 88047b6859fbSMintz, Yuval u8 flags4; 8805fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 8806fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 0 8807fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3 8808fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF9_SHIFT 2 8809fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3 8810fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT 4 8811fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3 8812fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF11_SHIFT 6 88137b6859fbSMintz, Yuval u8 flags5; 8814fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3 8815fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT 0 8816fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3 8817fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF13_SHIFT 2 8818fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 8819fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 4 8820fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3 8821fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF15_SHIFT 6 88227b6859fbSMintz, Yuval u8 flags6; 8823fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3 8824fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0 8825fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3 8826fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF17_SHIFT 2 8827fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3 8828fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF18_SHIFT 4 8829fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3 8830fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_SHIFT 6 88317b6859fbSMintz, Yuval u8 flags7; 8832fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 8833fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 8834fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3 8835fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_SHIFT 2 8836fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 8837fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_SHIFT 4 8838fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 8839fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 6 8840fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 8841fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 7 88427b6859fbSMintz, Yuval u8 flags8; 8843fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 8844fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 0 8845fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 8846fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1 8847fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1 8848fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 2 8849fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1 8850fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 3 8851fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 8852fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 4 8853fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1 8854fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 5 8855fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1 8856fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 6 8857fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK 0x1 8858fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF9EN_SHIFT 7 88597b6859fbSMintz, Yuval u8 flags9; 8860fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1 8861fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 0 8862fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK 0x1 8863fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF11EN_SHIFT 1 8864fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK 0x1 8865fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF12EN_SHIFT 2 8866fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK 0x1 8867fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF13EN_SHIFT 3 8868fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 8869fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 4 8870fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK 0x1 8871fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF15EN_SHIFT 5 8872fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1 8873fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_SHIFT 6 8874fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK 0x1 8875fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF17EN_SHIFT 7 88767b6859fbSMintz, Yuval u8 flags10; 8877fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK 0x1 8878fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT 0 8879fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1 8880fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1 8881fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 8882fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 8883fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1 8884fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT 3 8885fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 8886fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 8887fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_EN_MASK 0x1 8888fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_EN_SHIFT 5 8889fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 8890fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 6 8891fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1 8892fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT 7 88937b6859fbSMintz, Yuval u8 flags11; 8894fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1 8895fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0 8896fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 8897fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 1 8898fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK 0x1 8899fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_RESERVED3_SHIFT 2 8900fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 8901fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 3 8902fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1 8903fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 4 8904fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 8905fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 5 8906fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 8907fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 8908fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK 0x1 8909fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_RULE9EN_SHIFT 7 89107b6859fbSMintz, Yuval u8 flags12; 8911fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK 0x1 8912fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT 0 8913fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK 0x1 8914fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_RULE11EN_SHIFT 1 8915fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 8916fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 8917fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 8918fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 8919fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK 0x1 8920fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_SHIFT 4 8921fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK 0x1 8922fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_RULE15EN_SHIFT 5 8923fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK 0x1 8924fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_RULE16EN_SHIFT 6 8925fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK 0x1 8926fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_RULE17EN_SHIFT 7 89277b6859fbSMintz, Yuval u8 flags13; 8928fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK 0x1 8929fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT 0 8930fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK 0x1 8931fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_SHIFT 1 8932fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK 0x1 8933fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_SHIFT 2 8934fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK 0x1 8935fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_RULE21EN_SHIFT 3 8936fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 8937fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 8938fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK 0x1 8939fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_SHIFT 5 8940fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 8941fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 8942fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 8943fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 89447b6859fbSMintz, Yuval u8 flags14; 8945fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK 0x1 8946fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT 0 8947fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK 0x1 8948fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_BIT17_SHIFT 1 8949fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_BIT18_MASK 0x1 8950fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_BIT18_SHIFT 2 8951fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_MASK 0x1 8952fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_SHIFT 3 8953fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_MASK 0x1 8954fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_SHIFT 4 8955fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK 0x1 8956fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_SHIFT 5 8957fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_MASK 0x3 8958fb09a1edSShai Malin #define XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_SHIFT 6 89597b6859fbSMintz, Yuval u8 byte2; 89607b6859fbSMintz, Yuval __le16 physical_q0; 89617b6859fbSMintz, Yuval __le16 physical_q1; 89627b6859fbSMintz, Yuval __le16 sq_comp_cons; 89637b6859fbSMintz, Yuval __le16 sq_tx_cons; 89647b6859fbSMintz, Yuval __le16 sq_prod; 89657b6859fbSMintz, Yuval __le16 word5; 89667b6859fbSMintz, Yuval __le16 conn_dpi; 89677b6859fbSMintz, Yuval u8 byte3; 89687b6859fbSMintz, Yuval u8 byte4; 89697b6859fbSMintz, Yuval u8 byte5; 89707b6859fbSMintz, Yuval u8 byte6; 89717b6859fbSMintz, Yuval __le32 reg0; 89727b6859fbSMintz, Yuval __le32 reg1; 89737b6859fbSMintz, Yuval __le32 reg2; 89747b6859fbSMintz, Yuval __le32 more_to_send_seq; 89757b6859fbSMintz, Yuval __le32 reg4; 897650bc60cbSMichal Kalderon __le32 rewinded_snd_max_or_term_opcode; 89777b6859fbSMintz, Yuval __le32 rd_msn; 89787b6859fbSMintz, Yuval __le16 irq_prod_via_msdm; 89797b6859fbSMintz, Yuval __le16 irq_cons; 89807b6859fbSMintz, Yuval __le16 hq_cons_th_or_mpa_data; 89817b6859fbSMintz, Yuval __le16 hq_cons; 89827b6859fbSMintz, Yuval __le32 atom_msn; 89837b6859fbSMintz, Yuval __le32 orq_cons; 89847b6859fbSMintz, Yuval __le32 orq_cons_th; 89857b6859fbSMintz, Yuval u8 byte7; 89867b6859fbSMintz, Yuval u8 wqe_data_pad_bytes; 898750bc60cbSMichal Kalderon u8 max_ord; 89887b6859fbSMintz, Yuval u8 former_hq_prod; 89897b6859fbSMintz, Yuval u8 irq_prod_via_msem; 89907b6859fbSMintz, Yuval u8 byte12; 89917b6859fbSMintz, Yuval u8 max_pkt_pdu_size_lo; 89927b6859fbSMintz, Yuval u8 max_pkt_pdu_size_hi; 89937b6859fbSMintz, Yuval u8 byte15; 89947b6859fbSMintz, Yuval u8 e5_reserved; 89957b6859fbSMintz, Yuval __le16 e5_reserved4; 89967b6859fbSMintz, Yuval __le32 reg10; 89977b6859fbSMintz, Yuval __le32 reg11; 89987b6859fbSMintz, Yuval __le32 shared_queue_page_addr_lo; 89997b6859fbSMintz, Yuval __le32 shared_queue_page_addr_hi; 90007b6859fbSMintz, Yuval __le32 reg14; 90017b6859fbSMintz, Yuval __le32 reg15; 90027b6859fbSMintz, Yuval __le32 reg16; 90037b6859fbSMintz, Yuval __le32 reg17; 90047b6859fbSMintz, Yuval }; 90057b6859fbSMintz, Yuval 9006fb09a1edSShai Malin struct tstorm_iwarp_conn_ag_ctx { 90077b6859fbSMintz, Yuval u8 reserved0; 90087b6859fbSMintz, Yuval u8 state; 90097b6859fbSMintz, Yuval u8 flags0; 9010fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 9011fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 9012fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 9013fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 9014fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK 0x1 9015fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_BIT2_SHIFT 2 9016fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_OR_TERMINATE_SENT_MASK 0x1 9017fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_OR_TERMINATE_SENT_SHIFT 3 9018fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1 9019fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4 9020fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 9021fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_SHIFT 5 9022fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 9023fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 6 90247b6859fbSMintz, Yuval u8 flags1; 9025fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3 9026fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT 0 9027fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_MASK 0x3 9028fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_SHIFT 2 9029fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 9030fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4 9031fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 9032fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 6 90337b6859fbSMintz, Yuval u8 flags2; 9034fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 9035fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 0 9036fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 9037fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 2 9038fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 9039fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 4 9040fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 9041fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 6 90427b6859fbSMintz, Yuval u8 flags3; 9043fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_MASK 0x3 9044fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_SHIFT 0 9045fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3 9046fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_SHIFT 2 9047fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 9048fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 4 9049fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK 0x1 9050fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_SHIFT 5 9051fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_MASK 0x1 9052fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_SHIFT 6 9053fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 9054fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7 90557b6859fbSMintz, Yuval u8 flags4; 9056fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1 9057fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 0 9058fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1 9059fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 1 9060fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 9061fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 2 9062fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1 9063fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 3 9064fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1 9065fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 4 9066fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_MASK 0x1 9067fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_SHIFT 5 9068fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK 0x1 9069fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_SHIFT 6 9070fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 9071fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 7 90727b6859fbSMintz, Yuval u8 flags5; 9073fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 9074fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 0 9075fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 9076fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1 9077fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 9078fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2 9079fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 9080fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3 9081fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 9082fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4 9083fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK 0x1 9084fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_SHIFT 5 9085fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 9086fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6 9087fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1 9088fb09a1edSShai Malin #define TSTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7 90897b6859fbSMintz, Yuval __le32 reg0; 90907b6859fbSMintz, Yuval __le32 reg1; 90917b6859fbSMintz, Yuval __le32 unaligned_nxt_seq; 90927b6859fbSMintz, Yuval __le32 reg3; 90937b6859fbSMintz, Yuval __le32 reg4; 90947b6859fbSMintz, Yuval __le32 reg5; 90957b6859fbSMintz, Yuval __le32 reg6; 90967b6859fbSMintz, Yuval __le32 reg7; 90977b6859fbSMintz, Yuval __le32 reg8; 90987b6859fbSMintz, Yuval u8 orq_cache_idx; 90997b6859fbSMintz, Yuval u8 hq_prod; 91007b6859fbSMintz, Yuval __le16 sq_tx_cons_th; 91017b6859fbSMintz, Yuval u8 orq_prod; 91027b6859fbSMintz, Yuval u8 irq_cons; 91037b6859fbSMintz, Yuval __le16 sq_tx_cons; 91047b6859fbSMintz, Yuval __le16 conn_dpi; 91057b6859fbSMintz, Yuval __le16 rq_prod; 91067b6859fbSMintz, Yuval __le32 snd_seq; 91077b6859fbSMintz, Yuval __le32 last_hq_sequence; 91087b6859fbSMintz, Yuval }; 91097b6859fbSMintz, Yuval 9110a2e7699eSTomer Tayar /* The iwarp storm context of Tstorm */ 91117b6859fbSMintz, Yuval struct tstorm_iwarp_conn_st_ctx { 91127b6859fbSMintz, Yuval __le32 reserved[60]; 91137b6859fbSMintz, Yuval }; 91147b6859fbSMintz, Yuval 9115a2e7699eSTomer Tayar /* The iwarp storm context of Mstorm */ 91167b6859fbSMintz, Yuval struct mstorm_iwarp_conn_st_ctx { 91177b6859fbSMintz, Yuval __le32 reserved[32]; 91187b6859fbSMintz, Yuval }; 91197b6859fbSMintz, Yuval 9120a2e7699eSTomer Tayar /* The iwarp storm context of Ustorm */ 91217b6859fbSMintz, Yuval struct ustorm_iwarp_conn_st_ctx { 91220500a70dSMichal Kalderon struct regpair reserved[14]; 91237b6859fbSMintz, Yuval }; 91247b6859fbSMintz, Yuval 9125a2e7699eSTomer Tayar /* iwarp connection context */ 9126fb09a1edSShai Malin struct iwarp_conn_context { 91277b6859fbSMintz, Yuval struct ystorm_iwarp_conn_st_ctx ystorm_st_context; 91287b6859fbSMintz, Yuval struct regpair ystorm_st_padding[2]; 91297b6859fbSMintz, Yuval struct pstorm_iwarp_conn_st_ctx pstorm_st_context; 91307b6859fbSMintz, Yuval struct regpair pstorm_st_padding[2]; 91317b6859fbSMintz, Yuval struct xstorm_iwarp_conn_st_ctx xstorm_st_context; 9132fb09a1edSShai Malin struct xstorm_iwarp_conn_ag_ctx xstorm_ag_context; 9133fb09a1edSShai Malin struct tstorm_iwarp_conn_ag_ctx tstorm_ag_context; 91347b6859fbSMintz, Yuval struct timers_context timer_context; 9135fb09a1edSShai Malin struct ustorm_rdma_conn_ag_ctx ustorm_ag_context; 91367b6859fbSMintz, Yuval struct tstorm_iwarp_conn_st_ctx tstorm_st_context; 91377b6859fbSMintz, Yuval struct regpair tstorm_st_padding[2]; 91387b6859fbSMintz, Yuval struct mstorm_iwarp_conn_st_ctx mstorm_st_context; 91397b6859fbSMintz, Yuval struct ustorm_iwarp_conn_st_ctx ustorm_st_context; 91400500a70dSMichal Kalderon struct regpair ustorm_st_padding[2]; 91417b6859fbSMintz, Yuval }; 91427b6859fbSMintz, Yuval 9143a2e7699eSTomer Tayar /* iWARP create QP params passed by driver to FW in CreateQP Request Ramrod */ 91447b6859fbSMintz, Yuval struct iwarp_create_qp_ramrod_data { 91457b6859fbSMintz, Yuval u8 flags; 91467b6859fbSMintz, Yuval #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1 91477b6859fbSMintz, Yuval #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 0 91487b6859fbSMintz, Yuval #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_MASK 0x1 91497b6859fbSMintz, Yuval #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_SHIFT 1 91507b6859fbSMintz, Yuval #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 91517b6859fbSMintz, Yuval #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2 91527b6859fbSMintz, Yuval #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 91537b6859fbSMintz, Yuval #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3 91547b6859fbSMintz, Yuval #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 91557b6859fbSMintz, Yuval #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 4 91567b6859fbSMintz, Yuval #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_MASK 0x1 91577b6859fbSMintz, Yuval #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_SHIFT 5 915850bc60cbSMichal Kalderon #define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_MASK 0x1 915950bc60cbSMichal Kalderon #define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_SHIFT 6 916050bc60cbSMichal Kalderon #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK 0x1 916150bc60cbSMichal Kalderon #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_SHIFT 7 91627b6859fbSMintz, Yuval u8 reserved1; 91637b6859fbSMintz, Yuval __le16 pd; 91647b6859fbSMintz, Yuval __le16 sq_num_pages; 91657b6859fbSMintz, Yuval __le16 rq_num_pages; 91667b6859fbSMintz, Yuval __le32 reserved3[2]; 91677b6859fbSMintz, Yuval struct regpair qp_handle_for_cqe; 91687b6859fbSMintz, Yuval struct rdma_srq_id srq_id; 91697b6859fbSMintz, Yuval __le32 cq_cid_for_sq; 91707b6859fbSMintz, Yuval __le32 cq_cid_for_rq; 91717b6859fbSMintz, Yuval __le16 dpi; 91727b6859fbSMintz, Yuval __le16 physical_q0; 91737b6859fbSMintz, Yuval __le16 physical_q1; 91747b6859fbSMintz, Yuval u8 reserved2[6]; 91757b6859fbSMintz, Yuval }; 91767b6859fbSMintz, Yuval 9177a2e7699eSTomer Tayar /* iWARP completion queue types */ 91787b6859fbSMintz, Yuval enum iwarp_eqe_async_opcode { 91797b6859fbSMintz, Yuval IWARP_EVENT_TYPE_ASYNC_CONNECT_COMPLETE, 91807b6859fbSMintz, Yuval IWARP_EVENT_TYPE_ASYNC_ENHANCED_MPA_REPLY_ARRIVED, 91817b6859fbSMintz, Yuval IWARP_EVENT_TYPE_ASYNC_MPA_HANDSHAKE_COMPLETE, 91827b6859fbSMintz, Yuval IWARP_EVENT_TYPE_ASYNC_CID_CLEANED, 91837b6859fbSMintz, Yuval IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED, 91847b6859fbSMintz, Yuval IWARP_EVENT_TYPE_ASYNC_QP_IN_ERROR_STATE, 91857b6859fbSMintz, Yuval IWARP_EVENT_TYPE_ASYNC_CQ_OVERFLOW, 918639dbc646SYuval Bason IWARP_EVENT_TYPE_ASYNC_SRQ_LIMIT, 9187fe40a830SPrabhakar Kushwaha IWARP_EVENT_TYPE_ASYNC_SRQ_EMPTY, 91887b6859fbSMintz, Yuval MAX_IWARP_EQE_ASYNC_OPCODE 91897b6859fbSMintz, Yuval }; 91907b6859fbSMintz, Yuval 91917b6859fbSMintz, Yuval struct iwarp_eqe_data_mpa_async_completion { 91927b6859fbSMintz, Yuval __le16 ulp_data_len; 91930500a70dSMichal Kalderon u8 rtr_type_sent; 91940500a70dSMichal Kalderon u8 reserved[5]; 91957b6859fbSMintz, Yuval }; 91967b6859fbSMintz, Yuval 91977b6859fbSMintz, Yuval struct iwarp_eqe_data_tcp_async_completion { 91987b6859fbSMintz, Yuval __le16 ulp_data_len; 91997b6859fbSMintz, Yuval u8 mpa_handshake_mode; 92007b6859fbSMintz, Yuval u8 reserved[5]; 92017b6859fbSMintz, Yuval }; 92027b6859fbSMintz, Yuval 9203a2e7699eSTomer Tayar /* iWARP completion queue types */ 92047b6859fbSMintz, Yuval enum iwarp_eqe_sync_opcode { 9205fe40a830SPrabhakar Kushwaha IWARP_EVENT_TYPE_TCP_OFFLOAD = 13, 92067b6859fbSMintz, Yuval IWARP_EVENT_TYPE_MPA_OFFLOAD, 92077b6859fbSMintz, Yuval IWARP_EVENT_TYPE_MPA_OFFLOAD_SEND_RTR, 92087b6859fbSMintz, Yuval IWARP_EVENT_TYPE_CREATE_QP, 92097b6859fbSMintz, Yuval IWARP_EVENT_TYPE_QUERY_QP, 92107b6859fbSMintz, Yuval IWARP_EVENT_TYPE_MODIFY_QP, 92117b6859fbSMintz, Yuval IWARP_EVENT_TYPE_DESTROY_QP, 921250bc60cbSMichal Kalderon IWARP_EVENT_TYPE_ABORT_TCP_OFFLOAD, 92137b6859fbSMintz, Yuval MAX_IWARP_EQE_SYNC_OPCODE 92147b6859fbSMintz, Yuval }; 92157b6859fbSMintz, Yuval 9216a2e7699eSTomer Tayar /* iWARP EQE completion status */ 92177b6859fbSMintz, Yuval enum iwarp_fw_return_code { 92180500a70dSMichal Kalderon IWARP_CONN_ERROR_TCP_CONNECT_INVALID_PACKET = 6, 92197b6859fbSMintz, Yuval IWARP_CONN_ERROR_TCP_CONNECTION_RST, 92207b6859fbSMintz, Yuval IWARP_CONN_ERROR_TCP_CONNECT_TIMEOUT, 92217b6859fbSMintz, Yuval IWARP_CONN_ERROR_MPA_ERROR_REJECT, 92227b6859fbSMintz, Yuval IWARP_CONN_ERROR_MPA_NOT_SUPPORTED_VER, 92237b6859fbSMintz, Yuval IWARP_CONN_ERROR_MPA_RST, 92247b6859fbSMintz, Yuval IWARP_CONN_ERROR_MPA_FIN, 92257b6859fbSMintz, Yuval IWARP_CONN_ERROR_MPA_RTR_MISMATCH, 92267b6859fbSMintz, Yuval IWARP_CONN_ERROR_MPA_INSUF_IRD, 92277b6859fbSMintz, Yuval IWARP_CONN_ERROR_MPA_INVALID_PACKET, 92287b6859fbSMintz, Yuval IWARP_CONN_ERROR_MPA_LOCAL_ERROR, 92297b6859fbSMintz, Yuval IWARP_CONN_ERROR_MPA_TIMEOUT, 92307b6859fbSMintz, Yuval IWARP_CONN_ERROR_MPA_TERMINATE, 92317b6859fbSMintz, Yuval IWARP_QP_IN_ERROR_GOOD_CLOSE, 92327b6859fbSMintz, Yuval IWARP_QP_IN_ERROR_BAD_CLOSE, 92337b6859fbSMintz, Yuval IWARP_EXCEPTION_DETECTED_LLP_CLOSED, 92347b6859fbSMintz, Yuval IWARP_EXCEPTION_DETECTED_LLP_RESET, 92357b6859fbSMintz, Yuval IWARP_EXCEPTION_DETECTED_IRQ_FULL, 92367b6859fbSMintz, Yuval IWARP_EXCEPTION_DETECTED_RQ_EMPTY, 92377b6859fbSMintz, Yuval IWARP_EXCEPTION_DETECTED_LLP_TIMEOUT, 92387b6859fbSMintz, Yuval IWARP_EXCEPTION_DETECTED_REMOTE_PROTECTION_ERROR, 92397b6859fbSMintz, Yuval IWARP_EXCEPTION_DETECTED_CQ_OVERFLOW, 92407b6859fbSMintz, Yuval IWARP_EXCEPTION_DETECTED_LOCAL_CATASTROPHIC, 92417b6859fbSMintz, Yuval IWARP_EXCEPTION_DETECTED_LOCAL_ACCESS_ERROR, 92427b6859fbSMintz, Yuval IWARP_EXCEPTION_DETECTED_REMOTE_OPERATION_ERROR, 92437b6859fbSMintz, Yuval IWARP_EXCEPTION_DETECTED_TERMINATE_RECEIVED, 92447b6859fbSMintz, Yuval MAX_IWARP_FW_RETURN_CODE 92457b6859fbSMintz, Yuval }; 92467b6859fbSMintz, Yuval 9247a2e7699eSTomer Tayar /* unaligned opaque data received from LL2 */ 92487b6859fbSMintz, Yuval struct iwarp_init_func_params { 92497b6859fbSMintz, Yuval u8 ll2_ooo_q_index; 92507b6859fbSMintz, Yuval u8 reserved1[7]; 92517b6859fbSMintz, Yuval }; 92527b6859fbSMintz, Yuval 9253a2e7699eSTomer Tayar /* iwarp func init ramrod data */ 92547b6859fbSMintz, Yuval struct iwarp_init_func_ramrod_data { 92557b6859fbSMintz, Yuval struct rdma_init_func_ramrod_data rdma; 92567b6859fbSMintz, Yuval struct tcp_init_params tcp; 92577b6859fbSMintz, Yuval struct iwarp_init_func_params iwarp; 92587b6859fbSMintz, Yuval }; 92597b6859fbSMintz, Yuval 9260a2e7699eSTomer Tayar /* iWARP QP - possible states to transition to */ 92617b6859fbSMintz, Yuval enum iwarp_modify_qp_new_state_type { 92627b6859fbSMintz, Yuval IWARP_MODIFY_QP_STATE_CLOSING = 1, 9263a2e7699eSTomer Tayar IWARP_MODIFY_QP_STATE_ERROR = 2, 92647b6859fbSMintz, Yuval MAX_IWARP_MODIFY_QP_NEW_STATE_TYPE 92657b6859fbSMintz, Yuval }; 92667b6859fbSMintz, Yuval 9267a2e7699eSTomer Tayar /* iwarp modify qp responder ramrod data */ 92687b6859fbSMintz, Yuval struct iwarp_modify_qp_ramrod_data { 92697b6859fbSMintz, Yuval __le16 transition_to_state; 92707b6859fbSMintz, Yuval __le16 flags; 92717b6859fbSMintz, Yuval #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 92727b6859fbSMintz, Yuval #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 0 92737b6859fbSMintz, Yuval #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 92747b6859fbSMintz, Yuval #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 1 92757b6859fbSMintz, Yuval #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 92767b6859fbSMintz, Yuval #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 2 92777b6859fbSMintz, Yuval #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_MASK 0x1 92787b6859fbSMintz, Yuval #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_SHIFT 3 92797b6859fbSMintz, Yuval #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1 92807b6859fbSMintz, Yuval #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 4 928150bc60cbSMichal Kalderon #define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1 928250bc60cbSMichal Kalderon #define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT 5 928350bc60cbSMichal Kalderon #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_MASK 0x3FF 928450bc60cbSMichal Kalderon #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_SHIFT 6 928550bc60cbSMichal Kalderon __le16 physical_q0; 928650bc60cbSMichal Kalderon __le16 physical_q1; 928750bc60cbSMichal Kalderon __le32 reserved1[10]; 92887b6859fbSMintz, Yuval }; 92897b6859fbSMintz, Yuval 9290a2e7699eSTomer Tayar /* MPA params for Enhanced mode */ 92917b6859fbSMintz, Yuval struct mpa_rq_params { 92927b6859fbSMintz, Yuval __le32 ird; 92937b6859fbSMintz, Yuval __le32 ord; 92947b6859fbSMintz, Yuval }; 92957b6859fbSMintz, Yuval 9296a2e7699eSTomer Tayar /* MPA host Address-Len for private data */ 92977b6859fbSMintz, Yuval struct mpa_ulp_buffer { 92987b6859fbSMintz, Yuval struct regpair addr; 92997b6859fbSMintz, Yuval __le16 len; 93007b6859fbSMintz, Yuval __le16 reserved[3]; 93017b6859fbSMintz, Yuval }; 93027b6859fbSMintz, Yuval 9303a2e7699eSTomer Tayar /* iWARP MPA offload params common to Basic and Enhanced modes */ 93047b6859fbSMintz, Yuval struct mpa_outgoing_params { 93057b6859fbSMintz, Yuval u8 crc_needed; 93067b6859fbSMintz, Yuval u8 reject; 93077b6859fbSMintz, Yuval u8 reserved[6]; 93087b6859fbSMintz, Yuval struct mpa_rq_params out_rq; 93097b6859fbSMintz, Yuval struct mpa_ulp_buffer outgoing_ulp_buffer; 93107b6859fbSMintz, Yuval }; 93117b6859fbSMintz, Yuval 9312a2e7699eSTomer Tayar /* iWARP MPA offload params passed by driver to FW in MPA Offload Request 9313a2e7699eSTomer Tayar * Ramrod. 9314a2e7699eSTomer Tayar */ 93157b6859fbSMintz, Yuval struct iwarp_mpa_offload_ramrod_data { 93167b6859fbSMintz, Yuval struct mpa_outgoing_params common; 93177b6859fbSMintz, Yuval __le32 tcp_cid; 93187b6859fbSMintz, Yuval u8 mode; 93197b6859fbSMintz, Yuval u8 tcp_connect_side; 93207b6859fbSMintz, Yuval u8 rtr_pref; 93217b6859fbSMintz, Yuval #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_MASK 0x7 93227b6859fbSMintz, Yuval #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_SHIFT 0 93237b6859fbSMintz, Yuval #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_MASK 0x1F 93247b6859fbSMintz, Yuval #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_SHIFT 3 93257b6859fbSMintz, Yuval u8 reserved2; 93267b6859fbSMintz, Yuval struct mpa_ulp_buffer incoming_ulp_buffer; 93277b6859fbSMintz, Yuval struct regpair async_eqe_output_buf; 93287b6859fbSMintz, Yuval struct regpair handle_for_async; 93297b6859fbSMintz, Yuval struct regpair shared_queue_addr; 9330fe40a830SPrabhakar Kushwaha __le32 additional_setup_time; 9331da090917STomer Tayar __le16 rcv_wnd; 93327b6859fbSMintz, Yuval u8 stats_counter_id; 9333fe40a830SPrabhakar Kushwaha u8 reserved3[9]; 93347b6859fbSMintz, Yuval }; 93357b6859fbSMintz, Yuval 9336a2e7699eSTomer Tayar /* iWARP TCP connection offload params passed by driver to FW */ 93377b6859fbSMintz, Yuval struct iwarp_offload_params { 93387b6859fbSMintz, Yuval struct mpa_ulp_buffer incoming_ulp_buffer; 93397b6859fbSMintz, Yuval struct regpair async_eqe_output_buf; 93407b6859fbSMintz, Yuval struct regpair handle_for_async; 9341fe40a830SPrabhakar Kushwaha __le32 additional_setup_time; 93427b6859fbSMintz, Yuval __le16 physical_q0; 93437b6859fbSMintz, Yuval __le16 physical_q1; 93447b6859fbSMintz, Yuval u8 stats_counter_id; 93457b6859fbSMintz, Yuval u8 mpa_mode; 9346fe40a830SPrabhakar Kushwaha u8 src_vport_id; 9347fe40a830SPrabhakar Kushwaha u8 reserved[5]; 93487b6859fbSMintz, Yuval }; 93497b6859fbSMintz, Yuval 9350a2e7699eSTomer Tayar /* iWARP query QP output params */ 93517b6859fbSMintz, Yuval struct iwarp_query_qp_output_params { 93527b6859fbSMintz, Yuval __le32 flags; 93537b6859fbSMintz, Yuval #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1 93547b6859fbSMintz, Yuval #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0 93557b6859fbSMintz, Yuval #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF 93567b6859fbSMintz, Yuval #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_SHIFT 1 93577b6859fbSMintz, Yuval u8 reserved1[4]; 93587b6859fbSMintz, Yuval }; 93597b6859fbSMintz, Yuval 9360a2e7699eSTomer Tayar /* iWARP query QP ramrod data */ 93617b6859fbSMintz, Yuval struct iwarp_query_qp_ramrod_data { 93627b6859fbSMintz, Yuval struct regpair output_params_addr; 93637b6859fbSMintz, Yuval }; 93647b6859fbSMintz, Yuval 9365a2e7699eSTomer Tayar /* iWARP Ramrod Command IDs */ 93667b6859fbSMintz, Yuval enum iwarp_ramrod_cmd_id { 9367fe40a830SPrabhakar Kushwaha IWARP_RAMROD_CMD_ID_TCP_OFFLOAD = 13, 93687b6859fbSMintz, Yuval IWARP_RAMROD_CMD_ID_MPA_OFFLOAD, 93697b6859fbSMintz, Yuval IWARP_RAMROD_CMD_ID_MPA_OFFLOAD_SEND_RTR, 93707b6859fbSMintz, Yuval IWARP_RAMROD_CMD_ID_CREATE_QP, 93717b6859fbSMintz, Yuval IWARP_RAMROD_CMD_ID_QUERY_QP, 93727b6859fbSMintz, Yuval IWARP_RAMROD_CMD_ID_MODIFY_QP, 93737b6859fbSMintz, Yuval IWARP_RAMROD_CMD_ID_DESTROY_QP, 937450bc60cbSMichal Kalderon IWARP_RAMROD_CMD_ID_ABORT_TCP_OFFLOAD, 93757b6859fbSMintz, Yuval MAX_IWARP_RAMROD_CMD_ID 93767b6859fbSMintz, Yuval }; 93777b6859fbSMintz, Yuval 9378a2e7699eSTomer Tayar /* Per PF iWARP retransmit path statistics */ 93797b6859fbSMintz, Yuval struct iwarp_rxmit_stats_drv { 93807b6859fbSMintz, Yuval struct regpair tx_go_to_slow_start_event_cnt; 93817b6859fbSMintz, Yuval struct regpair tx_fast_retransmit_event_cnt; 93827b6859fbSMintz, Yuval }; 93837b6859fbSMintz, Yuval 9384a2e7699eSTomer Tayar /* iWARP and TCP connection offload params passed by driver to FW in iWARP 9385a2e7699eSTomer Tayar * offload ramrod. 9386a2e7699eSTomer Tayar */ 93877b6859fbSMintz, Yuval struct iwarp_tcp_offload_ramrod_data { 93887b6859fbSMintz, Yuval struct tcp_offload_params_opt2 tcp; 93890500a70dSMichal Kalderon struct iwarp_offload_params iwarp; 93907b6859fbSMintz, Yuval }; 93917b6859fbSMintz, Yuval 9392a2e7699eSTomer Tayar /* iWARP MPA negotiation types */ 93937b6859fbSMintz, Yuval enum mpa_negotiation_mode { 93947b6859fbSMintz, Yuval MPA_NEGOTIATION_TYPE_BASIC = 1, 93957b6859fbSMintz, Yuval MPA_NEGOTIATION_TYPE_ENHANCED = 2, 93967b6859fbSMintz, Yuval MAX_MPA_NEGOTIATION_MODE 93977b6859fbSMintz, Yuval }; 93987b6859fbSMintz, Yuval 9399a2e7699eSTomer Tayar /* iWARP MPA Enhanced mode RTR types */ 94007b6859fbSMintz, Yuval enum mpa_rtr_type { 94017b6859fbSMintz, Yuval MPA_RTR_TYPE_NONE = 0, 94027b6859fbSMintz, Yuval MPA_RTR_TYPE_ZERO_SEND = 1, 94037b6859fbSMintz, Yuval MPA_RTR_TYPE_ZERO_WRITE = 2, 94047b6859fbSMintz, Yuval MPA_RTR_TYPE_ZERO_SEND_AND_WRITE = 3, 94057b6859fbSMintz, Yuval MPA_RTR_TYPE_ZERO_READ = 4, 94067b6859fbSMintz, Yuval MPA_RTR_TYPE_ZERO_SEND_AND_READ = 5, 94077b6859fbSMintz, Yuval MPA_RTR_TYPE_ZERO_WRITE_AND_READ = 6, 94087b6859fbSMintz, Yuval MPA_RTR_TYPE_ZERO_SEND_AND_WRITE_AND_READ = 7, 94097b6859fbSMintz, Yuval MAX_MPA_RTR_TYPE 94107b6859fbSMintz, Yuval }; 94117b6859fbSMintz, Yuval 9412a2e7699eSTomer Tayar /* unaligned opaque data received from LL2 */ 94137b6859fbSMintz, Yuval struct unaligned_opaque_data { 94147b6859fbSMintz, Yuval __le16 first_mpa_offset; 94157b6859fbSMintz, Yuval u8 tcp_payload_offset; 94167b6859fbSMintz, Yuval u8 flags; 94177b6859fbSMintz, Yuval #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_MASK 0x1 94187b6859fbSMintz, Yuval #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_SHIFT 0 94197b6859fbSMintz, Yuval #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_MASK 0x1 94207b6859fbSMintz, Yuval #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_SHIFT 1 94217b6859fbSMintz, Yuval #define UNALIGNED_OPAQUE_DATA_RESERVED_MASK 0x3F 94227b6859fbSMintz, Yuval #define UNALIGNED_OPAQUE_DATA_RESERVED_SHIFT 2 94237b6859fbSMintz, Yuval __le32 cid; 94247b6859fbSMintz, Yuval }; 94257b6859fbSMintz, Yuval 9426fb09a1edSShai Malin struct mstorm_iwarp_conn_ag_ctx { 94277b6859fbSMintz, Yuval u8 reserved; 94287b6859fbSMintz, Yuval u8 state; 94297b6859fbSMintz, Yuval u8 flags0; 9430fb09a1edSShai Malin #define MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 9431fb09a1edSShai Malin #define MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 9432fb09a1edSShai Malin #define MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 9433fb09a1edSShai Malin #define MSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 9434fb09a1edSShai Malin #define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3 9435fb09a1edSShai Malin #define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT 2 9436fb09a1edSShai Malin #define MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 9437fb09a1edSShai Malin #define MSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 9438fb09a1edSShai Malin #define MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 9439fb09a1edSShai Malin #define MSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 94407b6859fbSMintz, Yuval u8 flags1; 9441fb09a1edSShai Malin #define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK 0x1 9442fb09a1edSShai Malin #define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT 0 9443fb09a1edSShai Malin #define MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 9444fb09a1edSShai Malin #define MSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 9445fb09a1edSShai Malin #define MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 9446fb09a1edSShai Malin #define MSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 9447fb09a1edSShai Malin #define MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 9448fb09a1edSShai Malin #define MSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3 9449fb09a1edSShai Malin #define MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 9450fb09a1edSShai Malin #define MSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4 9451fb09a1edSShai Malin #define MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 9452fb09a1edSShai Malin #define MSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5 9453fb09a1edSShai Malin #define MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK 0x1 9454fb09a1edSShai Malin #define MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_SHIFT 6 9455fb09a1edSShai Malin #define MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 9456fb09a1edSShai Malin #define MSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7 94577b6859fbSMintz, Yuval __le16 rcq_cons; 94587b6859fbSMintz, Yuval __le16 rcq_cons_th; 94597b6859fbSMintz, Yuval __le32 reg0; 94607b6859fbSMintz, Yuval __le32 reg1; 94617b6859fbSMintz, Yuval }; 94627b6859fbSMintz, Yuval 9463fb09a1edSShai Malin struct ustorm_iwarp_conn_ag_ctx { 94647b6859fbSMintz, Yuval u8 reserved; 94657b6859fbSMintz, Yuval u8 byte1; 94667b6859fbSMintz, Yuval u8 flags0; 9467fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 9468fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 9469fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 9470fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 9471fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 9472fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2 9473fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 9474fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 9475fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 9476fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 94777b6859fbSMintz, Yuval u8 flags1; 9478fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3 9479fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT 0 9480fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 9481fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 9482fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 9483fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 9484fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 9485fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 6 94867b6859fbSMintz, Yuval u8 flags2; 9487fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 9488fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0 9489fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 9490fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 9491fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 9492fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 9493fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK 0x1 9494fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CF3EN_SHIFT 3 9495fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 9496fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 9497fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 9498fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 9499fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 9500fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 6 9501fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 9502fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 95037b6859fbSMintz, Yuval u8 flags3; 9504fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK 0x1 9505fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT 0 9506fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 9507fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1 9508fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 9509fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2 9510fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 9511fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3 9512fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 9513fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4 9514fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1 9515fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 5 9516fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 9517fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6 9518fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1 9519fb09a1edSShai Malin #define USTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7 95207b6859fbSMintz, Yuval u8 byte2; 95217b6859fbSMintz, Yuval u8 byte3; 95227b6859fbSMintz, Yuval __le16 word0; 95237b6859fbSMintz, Yuval __le16 word1; 95247b6859fbSMintz, Yuval __le32 cq_cons; 95257b6859fbSMintz, Yuval __le32 cq_se_prod; 95267b6859fbSMintz, Yuval __le32 cq_prod; 95277b6859fbSMintz, Yuval __le32 reg3; 95287b6859fbSMintz, Yuval __le16 word2; 95297b6859fbSMintz, Yuval __le16 word3; 95307b6859fbSMintz, Yuval }; 95317b6859fbSMintz, Yuval 9532fb09a1edSShai Malin struct ystorm_iwarp_conn_ag_ctx { 95337b6859fbSMintz, Yuval u8 byte0; 95347b6859fbSMintz, Yuval u8 byte1; 95357b6859fbSMintz, Yuval u8 flags0; 9536fb09a1edSShai Malin #define YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK 0x1 9537fb09a1edSShai Malin #define YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT 0 9538fb09a1edSShai Malin #define YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 9539fb09a1edSShai Malin #define YSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 9540fb09a1edSShai Malin #define YSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 9541fb09a1edSShai Malin #define YSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2 9542fb09a1edSShai Malin #define YSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 9543fb09a1edSShai Malin #define YSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 9544fb09a1edSShai Malin #define YSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 9545fb09a1edSShai Malin #define YSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 95467b6859fbSMintz, Yuval u8 flags1; 9547fb09a1edSShai Malin #define YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 9548fb09a1edSShai Malin #define YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0 9549fb09a1edSShai Malin #define YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 9550fb09a1edSShai Malin #define YSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 9551fb09a1edSShai Malin #define YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 9552fb09a1edSShai Malin #define YSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 9553fb09a1edSShai Malin #define YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 9554fb09a1edSShai Malin #define YSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3 9555fb09a1edSShai Malin #define YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 9556fb09a1edSShai Malin #define YSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4 9557fb09a1edSShai Malin #define YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 9558fb09a1edSShai Malin #define YSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5 9559fb09a1edSShai Malin #define YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 9560fb09a1edSShai Malin #define YSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 6 9561fb09a1edSShai Malin #define YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 9562fb09a1edSShai Malin #define YSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7 95637b6859fbSMintz, Yuval u8 byte2; 95647b6859fbSMintz, Yuval u8 byte3; 95657b6859fbSMintz, Yuval __le16 word0; 95667b6859fbSMintz, Yuval __le32 reg0; 95677b6859fbSMintz, Yuval __le32 reg1; 95687b6859fbSMintz, Yuval __le16 word1; 95697b6859fbSMintz, Yuval __le16 word2; 95707b6859fbSMintz, Yuval __le16 word3; 95717b6859fbSMintz, Yuval __le16 word4; 95727b6859fbSMintz, Yuval __le32 reg2; 95737b6859fbSMintz, Yuval __le32 reg3; 95747b6859fbSMintz, Yuval }; 95757b6859fbSMintz, Yuval 9576a2e7699eSTomer Tayar /* The fcoe storm context of Ystorm */ 95771e128c81SArun Easi struct ystorm_fcoe_conn_st_ctx { 95781e128c81SArun Easi u8 func_mode; 95791e128c81SArun Easi u8 cos; 95801e128c81SArun Easi u8 conf_version; 95811e128c81SArun Easi u8 eth_hdr_size; 95821e128c81SArun Easi __le16 stat_ram_addr; 95831e128c81SArun Easi __le16 mtu; 95841e128c81SArun Easi __le16 max_fc_payload_len; 95851e128c81SArun Easi __le16 tx_max_fc_pay_len; 95861e128c81SArun Easi u8 fcp_cmd_size; 95871e128c81SArun Easi u8 fcp_rsp_size; 95881e128c81SArun Easi __le16 mss; 95891e128c81SArun Easi struct regpair reserved; 9590be086e7cSMintz, Yuval __le16 min_frame_size; 95911e128c81SArun Easi u8 protection_info_flags; 95921e128c81SArun Easi #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1 95931e128c81SArun Easi #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 0 95941e128c81SArun Easi #define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1 95951e128c81SArun Easi #define YSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 1 95961e128c81SArun Easi #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK 0x3F 95971e128c81SArun Easi #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_SHIFT 2 95981e128c81SArun Easi u8 dst_protection_per_mss; 95991e128c81SArun Easi u8 src_protection_per_mss; 96001e128c81SArun Easi u8 ptu_log_page_size; 96011e128c81SArun Easi u8 flags; 96021e128c81SArun Easi #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 96031e128c81SArun Easi #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 0 96041e128c81SArun Easi #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1 96051e128c81SArun Easi #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 1 96061e128c81SArun Easi #define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x3F 96071e128c81SArun Easi #define YSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 2 96081e128c81SArun Easi u8 fcp_xfer_size; 96091e128c81SArun Easi }; 96101e128c81SArun Easi 9611a2e7699eSTomer Tayar /* FCoE 16-bits vlan structure */ 96121e128c81SArun Easi struct fcoe_vlan_fields { 96131e128c81SArun Easi __le16 fields; 96141e128c81SArun Easi #define FCOE_VLAN_FIELDS_VID_MASK 0xFFF 96151e128c81SArun Easi #define FCOE_VLAN_FIELDS_VID_SHIFT 0 96161e128c81SArun Easi #define FCOE_VLAN_FIELDS_CLI_MASK 0x1 96171e128c81SArun Easi #define FCOE_VLAN_FIELDS_CLI_SHIFT 12 96181e128c81SArun Easi #define FCOE_VLAN_FIELDS_PRI_MASK 0x7 96191e128c81SArun Easi #define FCOE_VLAN_FIELDS_PRI_SHIFT 13 96201e128c81SArun Easi }; 96211e128c81SArun Easi 9622a2e7699eSTomer Tayar /* FCoE 16-bits vlan union */ 96231e128c81SArun Easi union fcoe_vlan_field_union { 96241e128c81SArun Easi struct fcoe_vlan_fields fields; 96251e128c81SArun Easi __le16 val; 96261e128c81SArun Easi }; 96271e128c81SArun Easi 9628a2e7699eSTomer Tayar /* FCoE 16-bits vlan, vif union */ 96291e128c81SArun Easi union fcoe_vlan_vif_field_union { 96301e128c81SArun Easi union fcoe_vlan_field_union vlan; 96311e128c81SArun Easi __le16 vif; 96321e128c81SArun Easi }; 96331e128c81SArun Easi 9634a2e7699eSTomer Tayar /* Ethernet context section */ 96351e128c81SArun Easi struct pstorm_fcoe_eth_context_section { 96361e128c81SArun Easi u8 remote_addr_3; 96371e128c81SArun Easi u8 remote_addr_2; 96381e128c81SArun Easi u8 remote_addr_1; 96391e128c81SArun Easi u8 remote_addr_0; 96401e128c81SArun Easi u8 local_addr_1; 96411e128c81SArun Easi u8 local_addr_0; 96421e128c81SArun Easi u8 remote_addr_5; 96431e128c81SArun Easi u8 remote_addr_4; 96441e128c81SArun Easi u8 local_addr_5; 96451e128c81SArun Easi u8 local_addr_4; 96461e128c81SArun Easi u8 local_addr_3; 96471e128c81SArun Easi u8 local_addr_2; 96481e128c81SArun Easi union fcoe_vlan_vif_field_union vif_outer_vlan; 96491e128c81SArun Easi __le16 vif_outer_eth_type; 96501e128c81SArun Easi union fcoe_vlan_vif_field_union inner_vlan; 96511e128c81SArun Easi __le16 inner_eth_type; 96521e128c81SArun Easi }; 96531e128c81SArun Easi 9654a2e7699eSTomer Tayar /* The fcoe storm context of Pstorm */ 96551e128c81SArun Easi struct pstorm_fcoe_conn_st_ctx { 96561e128c81SArun Easi u8 func_mode; 96571e128c81SArun Easi u8 cos; 96581e128c81SArun Easi u8 conf_version; 96591e128c81SArun Easi u8 rsrv; 96601e128c81SArun Easi __le16 stat_ram_addr; 96611e128c81SArun Easi __le16 mss; 96621e128c81SArun Easi struct regpair abts_cleanup_addr; 96631e128c81SArun Easi struct pstorm_fcoe_eth_context_section eth; 96641e128c81SArun Easi u8 sid_2; 96651e128c81SArun Easi u8 sid_1; 96661e128c81SArun Easi u8 sid_0; 96671e128c81SArun Easi u8 flags; 96681e128c81SArun Easi #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK 0x1 96691e128c81SArun Easi #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT 0 96701e128c81SArun Easi #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK 0x1 96711e128c81SArun Easi #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_SHIFT 1 96721e128c81SArun Easi #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 96731e128c81SArun Easi #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 2 96741e128c81SArun Easi #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1 96751e128c81SArun Easi #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 3 9676da090917STomer Tayar #define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_MASK 0x1 9677da090917STomer Tayar #define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_SHIFT 4 9678da090917STomer Tayar #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x7 9679da090917STomer Tayar #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 5 96801e128c81SArun Easi u8 did_2; 96811e128c81SArun Easi u8 did_1; 96821e128c81SArun Easi u8 did_0; 96831e128c81SArun Easi u8 src_mac_index; 96841e128c81SArun Easi __le16 rec_rr_tov_val; 96851e128c81SArun Easi u8 q_relative_offset; 96861e128c81SArun Easi u8 reserved1; 96871e128c81SArun Easi }; 96881e128c81SArun Easi 9689a2e7699eSTomer Tayar /* The fcoe storm context of Xstorm */ 96901e128c81SArun Easi struct xstorm_fcoe_conn_st_ctx { 96911e128c81SArun Easi u8 func_mode; 96921e128c81SArun Easi u8 src_mac_index; 96931e128c81SArun Easi u8 conf_version; 96941e128c81SArun Easi u8 cached_wqes_avail; 96951e128c81SArun Easi __le16 stat_ram_addr; 96961e128c81SArun Easi u8 flags; 96971e128c81SArun Easi #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK 0x1 96981e128c81SArun Easi #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT 0 96991e128c81SArun Easi #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 97001e128c81SArun Easi #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 1 97011e128c81SArun Easi #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK 0x1 97021e128c81SArun Easi #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_SHIFT 2 97031e128c81SArun Easi #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK 0x3 97041e128c81SArun Easi #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_SHIFT 3 97051e128c81SArun Easi #define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x7 97061e128c81SArun Easi #define XSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 5 97071e128c81SArun Easi u8 cached_wqes_offset; 97081e128c81SArun Easi u8 reserved2; 97091e128c81SArun Easi u8 eth_hdr_size; 97101e128c81SArun Easi u8 seq_id; 97111e128c81SArun Easi u8 max_conc_seqs; 97121e128c81SArun Easi __le16 num_pages_in_pbl; 97131e128c81SArun Easi __le16 reserved; 97141e128c81SArun Easi struct regpair sq_pbl_addr; 97151e128c81SArun Easi struct regpair sq_curr_page_addr; 97161e128c81SArun Easi struct regpair sq_next_page_addr; 97171e128c81SArun Easi struct regpair xferq_pbl_addr; 97181e128c81SArun Easi struct regpair xferq_curr_page_addr; 97191e128c81SArun Easi struct regpair xferq_next_page_addr; 97201e128c81SArun Easi struct regpair respq_pbl_addr; 97211e128c81SArun Easi struct regpair respq_curr_page_addr; 97221e128c81SArun Easi struct regpair respq_next_page_addr; 97231e128c81SArun Easi __le16 mtu; 97241e128c81SArun Easi __le16 tx_max_fc_pay_len; 97251e128c81SArun Easi __le16 max_fc_payload_len; 97261e128c81SArun Easi __le16 min_frame_size; 97271e128c81SArun Easi __le16 sq_pbl_next_index; 97281e128c81SArun Easi __le16 respq_pbl_next_index; 97291e128c81SArun Easi u8 fcp_cmd_byte_credit; 97301e128c81SArun Easi u8 fcp_rsp_byte_credit; 97311e128c81SArun Easi __le16 protection_info; 97321e128c81SArun Easi #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK 0x1 97331e128c81SArun Easi #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT 0 97341e128c81SArun Easi #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1 97351e128c81SArun Easi #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 1 97361e128c81SArun Easi #define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1 97371e128c81SArun Easi #define XSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 2 97381e128c81SArun Easi #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK 0x1 97391e128c81SArun Easi #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_SHIFT 3 97401e128c81SArun Easi #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK 0xF 97411e128c81SArun Easi #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_SHIFT 4 97421e128c81SArun Easi #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK 0xFF 97431e128c81SArun Easi #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_SHIFT 8 97441e128c81SArun Easi __le16 xferq_pbl_next_index; 97451e128c81SArun Easi __le16 page_size; 97461e128c81SArun Easi u8 mid_seq; 97471e128c81SArun Easi u8 fcp_xfer_byte_credit; 97481e128c81SArun Easi u8 reserved1[2]; 97491e128c81SArun Easi struct fcoe_wqe cached_wqes[16]; 97501e128c81SArun Easi }; 97511e128c81SArun Easi 9752fb09a1edSShai Malin struct xstorm_fcoe_conn_ag_ctx { 97531e128c81SArun Easi u8 reserved0; 9754da090917STomer Tayar u8 state; 97551e128c81SArun Easi u8 flags0; 9756fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 9757fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 9758fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1 9759fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT 1 9760fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1 9761fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT 2 9762fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 9763fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 9764fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1 9765fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT 4 9766fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1 9767fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT 5 9768fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1 9769fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT 6 9770fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1 9771fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT 7 97721e128c81SArun Easi u8 flags1; 9773fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1 9774fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT 0 9775fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1 9776fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT 1 9777fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1 9778fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT 2 9779fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1 9780fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT 3 9781fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1 9782fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT 4 9783fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1 9784fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT 5 9785fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1 9786fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT 6 9787fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1 9788fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT 7 97891e128c81SArun Easi u8 flags2; 9790fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 9791fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 0 9792fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 9793fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 2 9794fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 9795fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 4 9796fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3 9797fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 6 97981e128c81SArun Easi u8 flags3; 9799fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 9800fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 0 9801fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 9802fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 2 9803fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 9804fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 4 9805fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3 9806fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 6 98071e128c81SArun Easi u8 flags4; 9808fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3 9809fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 0 9810fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3 9811fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 2 9812fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3 9813fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 4 9814fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF11_MASK 0x3 9815fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT 6 98161e128c81SArun Easi u8 flags5; 9817fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF12_MASK 0x3 9818fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT 0 9819fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF13_MASK 0x3 9820fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT 2 9821fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF14_MASK 0x3 9822fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT 4 9823fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF15_MASK 0x3 9824fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT 6 98251e128c81SArun Easi u8 flags6; 9826fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF16_MASK 0x3 9827fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT 0 9828fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF17_MASK 0x3 9829fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT 2 9830fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF18_MASK 0x3 9831fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT 4 9832fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK 0x3 9833fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT 6 98341e128c81SArun Easi u8 flags7; 9835fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 9836fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 9837fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK 0x3 9838fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT 2 9839fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 9840fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 9841fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 9842fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 6 9843fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 9844fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 7 98451e128c81SArun Easi u8 flags8; 9846fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 9847fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 0 9848fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1 9849fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 1 9850fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 9851fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 2 9852fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 9853fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 3 9854fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 9855fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 4 9856fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1 9857fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 5 9858fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1 9859fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 6 9860fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1 9861fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 7 98621e128c81SArun Easi u8 flags9; 9863fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1 9864fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 0 9865fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1 9866fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT 1 9867fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1 9868fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT 2 9869fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1 9870fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT 3 9871fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1 9872fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT 4 9873fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1 9874fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT 5 9875fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1 9876fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT 6 9877fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1 9878fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT 7 98791e128c81SArun Easi u8 flags10; 9880fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1 9881fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT 0 9882fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 9883fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT 1 9884fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 9885fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 9886fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1 9887fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT 3 9888fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 9889fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 9890fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1 9891fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT 5 9892fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1 9893fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT 6 9894fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1 9895fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT 7 98961e128c81SArun Easi u8 flags11; 9897fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1 9898fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT 0 9899fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1 9900fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT 1 9901fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1 9902fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT 2 9903fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 9904fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 3 9905fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 9906fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 4 9907fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 9908fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 5 9909fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 9910fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 9911fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1 9912fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT 7 99131e128c81SArun Easi u8 flags12; 9914fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1 9915fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT 0 9916fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1 9917fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT 1 9918fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 9919fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 9920fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 9921fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 9922fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1 9923fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT 4 9924fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1 9925fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT 5 9926fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1 9927fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT 6 9928fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1 9929fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT 7 99301e128c81SArun Easi u8 flags13; 9931fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1 9932fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0 9933fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1 9934fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT 1 9935fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 9936fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 9937fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 9938fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 9939fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 9940fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 9941fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 9942fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 9943fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 9944fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 9945fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 9946fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 99471e128c81SArun Easi u8 flags14; 9948fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1 9949fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT 0 9950fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1 9951fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT 1 9952fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1 9953fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT 2 9954fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1 9955fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT 3 9956fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1 9957fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT 4 9958fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1 9959fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT 5 9960fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF23_MASK 0x3 9961fb09a1edSShai Malin #define XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT 6 99621e128c81SArun Easi u8 byte2; 99631e128c81SArun Easi __le16 physical_q0; 99641e128c81SArun Easi __le16 word1; 99651e128c81SArun Easi __le16 word2; 99661e128c81SArun Easi __le16 sq_cons; 99671e128c81SArun Easi __le16 sq_prod; 99681e128c81SArun Easi __le16 xferq_prod; 99691e128c81SArun Easi __le16 xferq_cons; 99701e128c81SArun Easi u8 byte3; 99711e128c81SArun Easi u8 byte4; 99721e128c81SArun Easi u8 byte5; 99731e128c81SArun Easi u8 byte6; 99741e128c81SArun Easi __le32 remain_io; 99751e128c81SArun Easi __le32 reg1; 99761e128c81SArun Easi __le32 reg2; 99771e128c81SArun Easi __le32 reg3; 99781e128c81SArun Easi __le32 reg4; 99791e128c81SArun Easi __le32 reg5; 99801e128c81SArun Easi __le32 reg6; 99811e128c81SArun Easi __le16 respq_prod; 99821e128c81SArun Easi __le16 respq_cons; 99831e128c81SArun Easi __le16 word9; 99841e128c81SArun Easi __le16 word10; 99851e128c81SArun Easi __le32 reg7; 99861e128c81SArun Easi __le32 reg8; 99871e128c81SArun Easi }; 99881e128c81SArun Easi 9989a2e7699eSTomer Tayar /* The fcoe storm context of Ustorm */ 99901e128c81SArun Easi struct ustorm_fcoe_conn_st_ctx { 99911e128c81SArun Easi struct regpair respq_pbl_addr; 99921e128c81SArun Easi __le16 num_pages_in_pbl; 99931e128c81SArun Easi u8 ptu_log_page_size; 99941e128c81SArun Easi u8 log_page_size; 99951e128c81SArun Easi __le16 respq_prod; 99961e128c81SArun Easi u8 reserved[2]; 99971e128c81SArun Easi }; 99981e128c81SArun Easi 9999fb09a1edSShai Malin struct tstorm_fcoe_conn_ag_ctx { 100001e128c81SArun Easi u8 reserved0; 10001da090917STomer Tayar u8 state; 100021e128c81SArun Easi u8 flags0; 10003fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 10004fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 10005fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 10006fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 10007fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1 10008fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT 2 10009fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1 10010fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT 3 10011fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1 10012fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT 4 10013fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1 10014fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT 5 10015fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK 0x3 10016fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT 6 100171e128c81SArun Easi u8 flags1; 10018fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 10019fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 0 10020fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 10021fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 2 10022fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 10023fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 10024fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 10025fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 6 100261e128c81SArun Easi u8 flags2; 10027fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 10028fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 0 10029fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 10030fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 2 10031fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3 10032fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 4 10033fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3 10034fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 6 100351e128c81SArun Easi u8 flags3; 10036fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3 10037fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 0 10038fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3 10039fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 2 10040fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1 10041fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT 4 10042fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 10043fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 10044fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 10045fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 6 10046fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 10047fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 100481e128c81SArun Easi u8 flags4; 10049fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 10050fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 0 10051fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 10052fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 1 10053fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 10054fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 2 10055fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1 10056fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 3 10057fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1 10058fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 4 10059fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1 10060fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 5 10061fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1 10062fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 6 10063fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 10064fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7 100651e128c81SArun Easi u8 flags5; 10066fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 10067fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0 10068fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 10069fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1 10070fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 10071fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2 10072fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 10073fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3 10074fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 10075fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4 10076fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 10077fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5 10078fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 10079fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6 10080fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1 10081fb09a1edSShai Malin #define TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7 100821e128c81SArun Easi __le32 reg0; 100831e128c81SArun Easi __le32 reg1; 100841e128c81SArun Easi }; 100851e128c81SArun Easi 10086fb09a1edSShai Malin struct ustorm_fcoe_conn_ag_ctx { 100871e128c81SArun Easi u8 byte0; 100881e128c81SArun Easi u8 byte1; 100891e128c81SArun Easi u8 flags0; 10090fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 10091fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 10092fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 10093fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 10094fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 10095fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 10096fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 10097fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 10098fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 10099fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 101001e128c81SArun Easi u8 flags1; 10101fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3 10102fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 0 10103fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 10104fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 2 10105fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 10106fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 4 10107fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 10108fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 6 101091e128c81SArun Easi u8 flags2; 10110fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 10111fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 10112fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 10113fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 10114fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 10115fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 10116fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1 10117fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 3 10118fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 10119fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 4 10120fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 10121fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 5 10122fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 10123fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 6 10124fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 10125fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7 101261e128c81SArun Easi u8 flags3; 10127fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 10128fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0 10129fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 10130fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1 10131fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 10132fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2 10133fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 10134fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3 10135fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 10136fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4 10137fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 10138fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5 10139fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 10140fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6 10141fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1 10142fb09a1edSShai Malin #define USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7 101431e128c81SArun Easi u8 byte2; 101441e128c81SArun Easi u8 byte3; 101451e128c81SArun Easi __le16 word0; 101461e128c81SArun Easi __le16 word1; 101471e128c81SArun Easi __le32 reg0; 101481e128c81SArun Easi __le32 reg1; 101491e128c81SArun Easi __le32 reg2; 101501e128c81SArun Easi __le32 reg3; 101511e128c81SArun Easi __le16 word2; 101521e128c81SArun Easi __le16 word3; 101531e128c81SArun Easi }; 101541e128c81SArun Easi 10155a2e7699eSTomer Tayar /* The fcoe storm context of Tstorm */ 101561e128c81SArun Easi struct tstorm_fcoe_conn_st_ctx { 101571e128c81SArun Easi __le16 stat_ram_addr; 101581e128c81SArun Easi __le16 rx_max_fc_payload_len; 101591e128c81SArun Easi __le16 e_d_tov_val; 101601e128c81SArun Easi u8 flags; 101611e128c81SArun Easi #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK 0x1 101621e128c81SArun Easi #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT 0 101631e128c81SArun Easi #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK 0x1 101641e128c81SArun Easi #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_SHIFT 1 101651e128c81SArun Easi #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK 0x3F 101661e128c81SArun Easi #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_SHIFT 2 101671e128c81SArun Easi u8 timers_cleanup_invocation_cnt; 101681e128c81SArun Easi __le32 reserved1[2]; 10169a2e7699eSTomer Tayar __le32 dst_mac_address_bytes_0_to_3; 10170a2e7699eSTomer Tayar __le16 dst_mac_address_bytes_4_to_5; 101711e128c81SArun Easi __le16 ramrod_echo; 101721e128c81SArun Easi u8 flags1; 101731e128c81SArun Easi #define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK 0x3 101741e128c81SArun Easi #define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT 0 101751e128c81SArun Easi #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x3F 101761e128c81SArun Easi #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 2 10177a2e7699eSTomer Tayar u8 cq_relative_offset; 10178da090917STomer Tayar u8 cmdq_relative_offset; 101791e128c81SArun Easi u8 bdq_resource_id; 10180da090917STomer Tayar u8 reserved0[4]; 101811e128c81SArun Easi }; 101821e128c81SArun Easi 10183fb09a1edSShai Malin struct mstorm_fcoe_conn_ag_ctx { 101841e128c81SArun Easi u8 byte0; 101851e128c81SArun Easi u8 byte1; 101861e128c81SArun Easi u8 flags0; 10187fb09a1edSShai Malin #define MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 10188fb09a1edSShai Malin #define MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 10189fb09a1edSShai Malin #define MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 10190fb09a1edSShai Malin #define MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 10191fb09a1edSShai Malin #define MSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 10192fb09a1edSShai Malin #define MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 10193fb09a1edSShai Malin #define MSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 10194fb09a1edSShai Malin #define MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 10195fb09a1edSShai Malin #define MSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 10196fb09a1edSShai Malin #define MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 101971e128c81SArun Easi u8 flags1; 10198fb09a1edSShai Malin #define MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 10199fb09a1edSShai Malin #define MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 10200fb09a1edSShai Malin #define MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 10201fb09a1edSShai Malin #define MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 10202fb09a1edSShai Malin #define MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 10203fb09a1edSShai Malin #define MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 10204fb09a1edSShai Malin #define MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 10205fb09a1edSShai Malin #define MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3 10206fb09a1edSShai Malin #define MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 10207fb09a1edSShai Malin #define MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4 10208fb09a1edSShai Malin #define MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 10209fb09a1edSShai Malin #define MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5 10210fb09a1edSShai Malin #define MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 10211fb09a1edSShai Malin #define MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6 10212fb09a1edSShai Malin #define MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 10213fb09a1edSShai Malin #define MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7 102141e128c81SArun Easi __le16 word0; 102151e128c81SArun Easi __le16 word1; 102161e128c81SArun Easi __le32 reg0; 102171e128c81SArun Easi __le32 reg1; 102181e128c81SArun Easi }; 102191e128c81SArun Easi 10220a2e7699eSTomer Tayar /* Fast path part of the fcoe storm context of Mstorm */ 102211e128c81SArun Easi struct fcoe_mstorm_fcoe_conn_st_ctx_fp { 102221e128c81SArun Easi __le16 xfer_prod; 10223da090917STomer Tayar u8 num_cqs; 10224da090917STomer Tayar u8 reserved1; 102251e128c81SArun Easi u8 protection_info; 102261e128c81SArun Easi #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_MASK 0x1 102271e128c81SArun Easi #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_SHIFT 0 102281e128c81SArun Easi #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_MASK 0x1 102291e128c81SArun Easi #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_SHIFT 1 102301e128c81SArun Easi #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_MASK 0x3F 102311e128c81SArun Easi #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_SHIFT 2 102321e128c81SArun Easi u8 q_relative_offset; 102331e128c81SArun Easi u8 reserved2[2]; 102341e128c81SArun Easi }; 102351e128c81SArun Easi 10236a2e7699eSTomer Tayar /* Non fast path part of the fcoe storm context of Mstorm */ 102371e128c81SArun Easi struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp { 102381e128c81SArun Easi __le16 conn_id; 102391e128c81SArun Easi __le16 stat_ram_addr; 102401e128c81SArun Easi __le16 num_pages_in_pbl; 102411e128c81SArun Easi u8 ptu_log_page_size; 102421e128c81SArun Easi u8 log_page_size; 102431e128c81SArun Easi __le16 unsolicited_cq_count; 102441e128c81SArun Easi __le16 cmdq_count; 102451e128c81SArun Easi u8 bdq_resource_id; 102461e128c81SArun Easi u8 reserved0[3]; 102471e128c81SArun Easi struct regpair xferq_pbl_addr; 102481e128c81SArun Easi struct regpair reserved1; 102491e128c81SArun Easi struct regpair reserved2[3]; 102501e128c81SArun Easi }; 102511e128c81SArun Easi 10252a2e7699eSTomer Tayar /* The fcoe storm context of Mstorm */ 102531e128c81SArun Easi struct mstorm_fcoe_conn_st_ctx { 102541e128c81SArun Easi struct fcoe_mstorm_fcoe_conn_st_ctx_fp fp; 102551e128c81SArun Easi struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp non_fp; 102561e128c81SArun Easi }; 102571e128c81SArun Easi 10258a2e7699eSTomer Tayar /* fcoe connection context */ 10259fb09a1edSShai Malin struct fcoe_conn_context { 102601e128c81SArun Easi struct ystorm_fcoe_conn_st_ctx ystorm_st_context; 102611e128c81SArun Easi struct pstorm_fcoe_conn_st_ctx pstorm_st_context; 102621e128c81SArun Easi struct regpair pstorm_st_padding[2]; 102631e128c81SArun Easi struct xstorm_fcoe_conn_st_ctx xstorm_st_context; 10264fb09a1edSShai Malin struct xstorm_fcoe_conn_ag_ctx xstorm_ag_context; 102651e128c81SArun Easi struct regpair xstorm_ag_padding[6]; 102661e128c81SArun Easi struct ustorm_fcoe_conn_st_ctx ustorm_st_context; 102671e128c81SArun Easi struct regpair ustorm_st_padding[2]; 10268fb09a1edSShai Malin struct tstorm_fcoe_conn_ag_ctx tstorm_ag_context; 102691e128c81SArun Easi struct regpair tstorm_ag_padding[2]; 102701e128c81SArun Easi struct timers_context timer_context; 10271fb09a1edSShai Malin struct ustorm_fcoe_conn_ag_ctx ustorm_ag_context; 102721e128c81SArun Easi struct tstorm_fcoe_conn_st_ctx tstorm_st_context; 10273fb09a1edSShai Malin struct mstorm_fcoe_conn_ag_ctx mstorm_ag_context; 102741e128c81SArun Easi struct mstorm_fcoe_conn_st_ctx mstorm_st_context; 102751e128c81SArun Easi }; 102761e128c81SArun Easi 10277a2e7699eSTomer Tayar /* FCoE connection offload params passed by driver to FW in FCoE offload 10278a2e7699eSTomer Tayar * ramrod. 10279a2e7699eSTomer Tayar */ 102801e128c81SArun Easi struct fcoe_conn_offload_ramrod_params { 102811e128c81SArun Easi struct fcoe_conn_offload_ramrod_data offload_ramrod_data; 102821e128c81SArun Easi }; 102831e128c81SArun Easi 10284a2e7699eSTomer Tayar /* FCoE connection terminate params passed by driver to FW in FCoE terminate 10285a2e7699eSTomer Tayar * conn ramrod. 10286a2e7699eSTomer Tayar */ 102871e128c81SArun Easi struct fcoe_conn_terminate_ramrod_params { 102881e128c81SArun Easi struct fcoe_conn_terminate_ramrod_data terminate_ramrod_data; 102891e128c81SArun Easi }; 102901e128c81SArun Easi 10291a2e7699eSTomer Tayar /* FCoE event type */ 102921e128c81SArun Easi enum fcoe_event_type { 102931e128c81SArun Easi FCOE_EVENT_INIT_FUNC, 102941e128c81SArun Easi FCOE_EVENT_DESTROY_FUNC, 102951e128c81SArun Easi FCOE_EVENT_STAT_FUNC, 102961e128c81SArun Easi FCOE_EVENT_OFFLOAD_CONN, 102971e128c81SArun Easi FCOE_EVENT_TERMINATE_CONN, 102981e128c81SArun Easi FCOE_EVENT_ERROR, 102991e128c81SArun Easi MAX_FCOE_EVENT_TYPE 103001e128c81SArun Easi }; 103011e128c81SArun Easi 10302a2e7699eSTomer Tayar /* FCoE init params passed by driver to FW in FCoE init ramrod */ 103031e128c81SArun Easi struct fcoe_init_ramrod_params { 103041e128c81SArun Easi struct fcoe_init_func_ramrod_data init_ramrod_data; 103051e128c81SArun Easi }; 103061e128c81SArun Easi 10307a2e7699eSTomer Tayar /* FCoE ramrod Command IDs */ 103081e128c81SArun Easi enum fcoe_ramrod_cmd_id { 103091e128c81SArun Easi FCOE_RAMROD_CMD_ID_INIT_FUNC, 103101e128c81SArun Easi FCOE_RAMROD_CMD_ID_DESTROY_FUNC, 103111e128c81SArun Easi FCOE_RAMROD_CMD_ID_STAT_FUNC, 103121e128c81SArun Easi FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, 103131e128c81SArun Easi FCOE_RAMROD_CMD_ID_TERMINATE_CONN, 103141e128c81SArun Easi MAX_FCOE_RAMROD_CMD_ID 103151e128c81SArun Easi }; 103161e128c81SArun Easi 10317a2e7699eSTomer Tayar /* FCoE statistics params buffer passed by driver to FW in FCoE statistics 10318a2e7699eSTomer Tayar * ramrod. 10319a2e7699eSTomer Tayar */ 103201e128c81SArun Easi struct fcoe_stat_ramrod_params { 103211e128c81SArun Easi struct fcoe_stat_ramrod_data stat_ramrod_data; 103221e128c81SArun Easi }; 103231e128c81SArun Easi 10324fb09a1edSShai Malin struct ystorm_fcoe_conn_ag_ctx { 103251e128c81SArun Easi u8 byte0; 103261e128c81SArun Easi u8 byte1; 103271e128c81SArun Easi u8 flags0; 10328fb09a1edSShai Malin #define YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 10329fb09a1edSShai Malin #define YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 10330fb09a1edSShai Malin #define YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 10331fb09a1edSShai Malin #define YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 10332fb09a1edSShai Malin #define YSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 10333fb09a1edSShai Malin #define YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 10334fb09a1edSShai Malin #define YSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 10335fb09a1edSShai Malin #define YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 10336fb09a1edSShai Malin #define YSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 10337fb09a1edSShai Malin #define YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 103381e128c81SArun Easi u8 flags1; 10339fb09a1edSShai Malin #define YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 10340fb09a1edSShai Malin #define YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 10341fb09a1edSShai Malin #define YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 10342fb09a1edSShai Malin #define YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 10343fb09a1edSShai Malin #define YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 10344fb09a1edSShai Malin #define YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 10345fb09a1edSShai Malin #define YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 10346fb09a1edSShai Malin #define YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3 10347fb09a1edSShai Malin #define YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 10348fb09a1edSShai Malin #define YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4 10349fb09a1edSShai Malin #define YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 10350fb09a1edSShai Malin #define YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5 10351fb09a1edSShai Malin #define YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 10352fb09a1edSShai Malin #define YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6 10353fb09a1edSShai Malin #define YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 10354fb09a1edSShai Malin #define YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7 103551e128c81SArun Easi u8 byte2; 103561e128c81SArun Easi u8 byte3; 103571e128c81SArun Easi __le16 word0; 103581e128c81SArun Easi __le32 reg0; 103591e128c81SArun Easi __le32 reg1; 103601e128c81SArun Easi __le16 word1; 103611e128c81SArun Easi __le16 word2; 103621e128c81SArun Easi __le16 word3; 103631e128c81SArun Easi __le16 word4; 103641e128c81SArun Easi __le32 reg2; 103651e128c81SArun Easi __le32 reg3; 103661e128c81SArun Easi }; 103671e128c81SArun Easi 10368a2e7699eSTomer Tayar /* The iscsi storm connection context of Ystorm */ 103697a9b6b8fSYuval Mintz struct ystorm_iscsi_conn_st_ctx { 10370da090917STomer Tayar __le32 reserved[8]; 103717a9b6b8fSYuval Mintz }; 103727a9b6b8fSYuval Mintz 10373a2e7699eSTomer Tayar /* Combined iSCSI and TCP storm connection of Pstorm */ 103747a9b6b8fSYuval Mintz struct pstorm_iscsi_tcp_conn_st_ctx { 103757a9b6b8fSYuval Mintz __le32 tcp[32]; 103767a9b6b8fSYuval Mintz __le32 iscsi[4]; 103777a9b6b8fSYuval Mintz }; 103787a9b6b8fSYuval Mintz 10379a2e7699eSTomer Tayar /* The combined tcp and iscsi storm context of Xstorm */ 103807a9b6b8fSYuval Mintz struct xstorm_iscsi_tcp_conn_st_ctx { 103817a9b6b8fSYuval Mintz __le32 reserved_tcp[4]; 10382da090917STomer Tayar __le32 reserved_iscsi[44]; 103837a9b6b8fSYuval Mintz }; 103847a9b6b8fSYuval Mintz 10385fb09a1edSShai Malin struct xstorm_iscsi_conn_ag_ctx { 103867a9b6b8fSYuval Mintz u8 cdu_validation; 103877a9b6b8fSYuval Mintz u8 state; 103887a9b6b8fSYuval Mintz u8 flags0; 10389fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 10390fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 10391fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1 10392fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1 10393fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK 0x1 10394fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_SHIFT 2 10395fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 10396fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 10397fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1 10398fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4 10399fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK 0x1 10400fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_SHIFT 5 10401fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK 0x1 10402fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_BIT6_SHIFT 6 10403fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK 0x1 10404fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_BIT7_SHIFT 7 104057a9b6b8fSYuval Mintz u8 flags1; 10406fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK 0x1 10407fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_BIT8_SHIFT 0 10408fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK 0x1 10409fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_BIT9_SHIFT 1 10410fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK 0x1 10411fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_BIT10_SHIFT 2 10412fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK 0x1 10413fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_BIT11_SHIFT 3 10414fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK 0x1 10415fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_BIT12_SHIFT 4 10416fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK 0x1 10417fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_BIT13_SHIFT 5 10418fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK 0x1 10419fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_BIT14_SHIFT 6 10420fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK 0x1 10421fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_SHIFT 7 104227a9b6b8fSYuval Mintz u8 flags2; 10423fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 10424fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 0 10425fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 10426fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 2 10427fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 10428fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 4 10429fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 10430fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6 104317a9b6b8fSYuval Mintz u8 flags3; 10432fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3 10433fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 0 10434fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3 10435fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 2 10436fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3 10437fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 4 10438fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3 10439fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 6 104407a9b6b8fSYuval Mintz u8 flags4; 10441fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3 10442fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 0 10443fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK 0x3 10444fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF9_SHIFT 2 10445fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3 10446fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 4 10447fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK 0x3 10448fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF11_SHIFT 6 104497a9b6b8fSYuval Mintz u8 flags5; 10450fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK 0x3 10451fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF12_SHIFT 0 10452fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK 0x3 10453fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF13_SHIFT 2 10454fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK 0x3 10455fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF14_SHIFT 4 10456fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK 0x3 10457fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_SHIFT 6 104587a9b6b8fSYuval Mintz u8 flags6; 10459fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK 0x3 10460fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF16_SHIFT 0 10461fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK 0x3 10462fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF17_SHIFT 2 10463fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK 0x3 10464fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF18_SHIFT 4 10465fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK 0x3 10466fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_SHIFT 6 104677a9b6b8fSYuval Mintz u8 flags7; 10468fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_MASK 0x3 10469fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_SHIFT 0 10470fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_MASK 0x3 10471fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_SHIFT 2 10472fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK 0x3 10473fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_SHIFT 4 10474fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 10475fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 6 10476fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1 10477fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 7 104787a9b6b8fSYuval Mintz u8 flags8; 10479fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1 10480fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 0 10481fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 10482fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1 10483fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1 10484fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 2 10485fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1 10486fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 3 10487fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1 10488fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 4 10489fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1 10490fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 5 10491fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1 10492fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 6 10493fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK 0x1 10494fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_SHIFT 7 104957a9b6b8fSYuval Mintz u8 flags9; 10496fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1 10497fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 0 10498fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK 0x1 10499fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_SHIFT 1 10500fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK 0x1 10501fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_SHIFT 2 10502fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK 0x1 10503fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_SHIFT 3 10504fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK 0x1 10505fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_SHIFT 4 10506fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK 0x1 10507fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_SHIFT 5 10508fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK 0x1 10509fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_SHIFT 6 10510fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK 0x1 10511fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_SHIFT 7 105127a9b6b8fSYuval Mintz u8 flags10; 10513fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK 0x1 10514fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_SHIFT 0 10515fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1 10516fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1 10517fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_MASK 0x1 10518fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_SHIFT 2 10519fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_MASK 0x1 10520fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_SHIFT 3 10521fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 10522fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 10523fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK 0x1 10524fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_SHIFT 5 10525fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 10526fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 6 10527fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK 0x1 10528fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_SHIFT 7 105297a9b6b8fSYuval Mintz u8 flags11; 10530fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1 10531fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0 10532fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 10533fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 1 10534fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK 0x1 10535fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_SHIFT 2 10536fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1 10537fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 3 10538fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1 10539fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 4 10540fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1 10541fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 5 10542fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 10543fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 10544fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK 0x1 10545fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_SHIFT 7 105467a9b6b8fSYuval Mintz u8 flags12; 10547fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK 0x1 10548fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_SHIFT 0 10549fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK 0x1 10550fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_SHIFT 1 10551fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 10552fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 10553fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 10554fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 10555fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK 0x1 10556fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_SHIFT 4 10557fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK 0x1 10558fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_SHIFT 5 10559fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK 0x1 10560fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_SHIFT 6 10561fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK 0x1 10562fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_SHIFT 7 105637a9b6b8fSYuval Mintz u8 flags13; 10564fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK 0x1 10565fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_SHIFT 0 10566fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK 0x1 10567fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_SHIFT 1 10568fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 10569fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 10570fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 10571fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 10572fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 10573fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 10574fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 10575fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 10576fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 10577fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 10578fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 10579fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 105807a9b6b8fSYuval Mintz u8 flags14; 10581fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK 0x1 10582fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_BIT16_SHIFT 0 10583fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK 0x1 10584fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_BIT17_SHIFT 1 10585fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK 0x1 10586fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_BIT18_SHIFT 2 10587fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK 0x1 10588fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_BIT19_SHIFT 3 10589fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK 0x1 10590fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_BIT20_SHIFT 4 10591fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK 0x1 10592fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_SHIFT 5 10593fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK 0x3 10594fb09a1edSShai Malin #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_SHIFT 6 105957a9b6b8fSYuval Mintz u8 byte2; 105967a9b6b8fSYuval Mintz __le16 physical_q0; 105977a9b6b8fSYuval Mintz __le16 physical_q1; 105987a9b6b8fSYuval Mintz __le16 dummy_dorq_var; 105997a9b6b8fSYuval Mintz __le16 sq_cons; 106007a9b6b8fSYuval Mintz __le16 sq_prod; 106017a9b6b8fSYuval Mintz __le16 word5; 106027a9b6b8fSYuval Mintz __le16 slow_io_total_data_tx_update; 106037a9b6b8fSYuval Mintz u8 byte3; 106047a9b6b8fSYuval Mintz u8 byte4; 106057a9b6b8fSYuval Mintz u8 byte5; 106067a9b6b8fSYuval Mintz u8 byte6; 106077a9b6b8fSYuval Mintz __le32 reg0; 106087a9b6b8fSYuval Mintz __le32 reg1; 106097a9b6b8fSYuval Mintz __le32 reg2; 106107a9b6b8fSYuval Mintz __le32 more_to_send_seq; 106117a9b6b8fSYuval Mintz __le32 reg4; 106127a9b6b8fSYuval Mintz __le32 reg5; 106137a9b6b8fSYuval Mintz __le32 hq_scan_next_relevant_ack; 106147a9b6b8fSYuval Mintz __le16 r2tq_prod; 106157a9b6b8fSYuval Mintz __le16 r2tq_cons; 106167a9b6b8fSYuval Mintz __le16 hq_prod; 106177a9b6b8fSYuval Mintz __le16 hq_cons; 106187a9b6b8fSYuval Mintz __le32 remain_seq; 106197a9b6b8fSYuval Mintz __le32 bytes_to_next_pdu; 106207a9b6b8fSYuval Mintz __le32 hq_tcp_seq; 106217a9b6b8fSYuval Mintz u8 byte7; 106227a9b6b8fSYuval Mintz u8 byte8; 106237a9b6b8fSYuval Mintz u8 byte9; 106247a9b6b8fSYuval Mintz u8 byte10; 106257a9b6b8fSYuval Mintz u8 byte11; 106267a9b6b8fSYuval Mintz u8 byte12; 106277a9b6b8fSYuval Mintz u8 byte13; 106287a9b6b8fSYuval Mintz u8 byte14; 106297a9b6b8fSYuval Mintz u8 byte15; 1063021dd79e8STomer Tayar u8 e5_reserved; 106317a9b6b8fSYuval Mintz __le16 word11; 106327a9b6b8fSYuval Mintz __le32 reg10; 106337a9b6b8fSYuval Mintz __le32 reg11; 106347a9b6b8fSYuval Mintz __le32 exp_stat_sn; 10635be086e7cSMintz, Yuval __le32 ongoing_fast_rxmit_seq; 106367a9b6b8fSYuval Mintz __le32 reg14; 106377a9b6b8fSYuval Mintz __le32 reg15; 106387a9b6b8fSYuval Mintz __le32 reg16; 106397a9b6b8fSYuval Mintz __le32 reg17; 106407a9b6b8fSYuval Mintz }; 106417a9b6b8fSYuval Mintz 10642fb09a1edSShai Malin struct tstorm_iscsi_conn_ag_ctx { 106437a9b6b8fSYuval Mintz u8 reserved0; 106447a9b6b8fSYuval Mintz u8 state; 106457a9b6b8fSYuval Mintz u8 flags0; 10646fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 10647fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 10648fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1 10649fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1 10650fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK 0x1 10651fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_BIT2_SHIFT 2 10652fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK 0x1 10653fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_BIT3_SHIFT 3 10654fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1 10655fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4 10656fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK 0x1 10657fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_BIT5_SHIFT 5 10658fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 10659fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 6 106607a9b6b8fSYuval Mintz u8 flags1; 10661fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_MASK 0x3 10662fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_SHIFT 0 10663fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_MASK 0x3 10664fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_SHIFT 2 10665fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 10666fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4 10667fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3 10668fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 6 106697a9b6b8fSYuval Mintz u8 flags2; 10670fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3 10671fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 0 10672fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3 10673fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 2 10674fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3 10675fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 4 10676fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3 10677fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 6 106787a9b6b8fSYuval Mintz u8 flags3; 10679fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 10680fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 10681fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_MASK 0x3 10682fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_SHIFT 2 10683fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 10684fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 4 10685fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_MASK 0x1 10686fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_SHIFT 5 10687fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_MASK 0x1 10688fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_SHIFT 6 10689fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 10690fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7 106917a9b6b8fSYuval Mintz u8 flags4; 10692fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1 10693fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 0 10694fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1 10695fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 1 10696fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1 10697fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 2 10698fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1 10699fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 3 10700fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1 10701fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 4 10702fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 10703fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5 10704fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_EN_MASK 0x1 10705fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_EN_SHIFT 6 10706fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 10707fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7 107087a9b6b8fSYuval Mintz u8 flags5; 10709fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1 10710fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0 10711fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1 10712fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1 10713fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 10714fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2 10715fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1 10716fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3 10717fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1 10718fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4 10719fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1 10720fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5 10721fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1 10722fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6 10723fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1 10724fb09a1edSShai Malin #define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7 107257a9b6b8fSYuval Mintz __le32 reg0; 107267a9b6b8fSYuval Mintz __le32 reg1; 1072750bc60cbSMichal Kalderon __le32 rx_tcp_checksum_err_cnt; 107287a9b6b8fSYuval Mintz __le32 reg3; 107297a9b6b8fSYuval Mintz __le32 reg4; 107307a9b6b8fSYuval Mintz __le32 reg5; 107317a9b6b8fSYuval Mintz __le32 reg6; 107327a9b6b8fSYuval Mintz __le32 reg7; 107337a9b6b8fSYuval Mintz __le32 reg8; 10734be086e7cSMintz, Yuval u8 cid_offload_cnt; 107357a9b6b8fSYuval Mintz u8 byte3; 107367a9b6b8fSYuval Mintz __le16 word0; 107377a9b6b8fSYuval Mintz }; 107387a9b6b8fSYuval Mintz 10739fb09a1edSShai Malin struct ustorm_iscsi_conn_ag_ctx { 107407a9b6b8fSYuval Mintz u8 byte0; 107417a9b6b8fSYuval Mintz u8 byte1; 107427a9b6b8fSYuval Mintz u8 flags0; 10743fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1 10744fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0 10745fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1 10746fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1 10747fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 10748fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2 10749fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 10750fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4 10751fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 10752fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6 107537a9b6b8fSYuval Mintz u8 flags1; 10754fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_CF3_MASK 0x3 10755fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_CF3_SHIFT 0 10756fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3 10757fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 2 10758fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3 10759fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 4 10760fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3 10761fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 6 107627a9b6b8fSYuval Mintz u8 flags2; 10763fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 10764fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0 10765fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1 10766fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1 10767fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1 10768fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2 10769fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK 0x1 10770fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_CF3EN_SHIFT 3 10771fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1 10772fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 4 10773fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1 10774fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 5 10775fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1 10776fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 6 10777fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 10778fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7 107797a9b6b8fSYuval Mintz u8 flags3; 10780fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1 10781fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0 10782fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1 10783fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1 10784fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 10785fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2 10786fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1 10787fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3 10788fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1 10789fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4 10790fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1 10791fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5 10792fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1 10793fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6 10794fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1 10795fb09a1edSShai Malin #define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7 107967a9b6b8fSYuval Mintz u8 byte2; 107977a9b6b8fSYuval Mintz u8 byte3; 107987a9b6b8fSYuval Mintz __le16 word0; 107997a9b6b8fSYuval Mintz __le16 word1; 108007a9b6b8fSYuval Mintz __le32 reg0; 108017a9b6b8fSYuval Mintz __le32 reg1; 108027a9b6b8fSYuval Mintz __le32 reg2; 108037a9b6b8fSYuval Mintz __le32 reg3; 108047a9b6b8fSYuval Mintz __le16 word2; 108057a9b6b8fSYuval Mintz __le16 word3; 108067a9b6b8fSYuval Mintz }; 108077a9b6b8fSYuval Mintz 10808a2e7699eSTomer Tayar /* The iscsi storm connection context of Tstorm */ 108097a9b6b8fSYuval Mintz struct tstorm_iscsi_conn_st_ctx { 10810da090917STomer Tayar __le32 reserved[44]; 108117a9b6b8fSYuval Mintz }; 108127a9b6b8fSYuval Mintz 10813fb09a1edSShai Malin struct mstorm_iscsi_conn_ag_ctx { 108147a9b6b8fSYuval Mintz u8 reserved; 108157a9b6b8fSYuval Mintz u8 state; 108167a9b6b8fSYuval Mintz u8 flags0; 10817fb09a1edSShai Malin #define MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1 10818fb09a1edSShai Malin #define MSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0 10819fb09a1edSShai Malin #define MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1 10820fb09a1edSShai Malin #define MSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1 10821fb09a1edSShai Malin #define MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 10822fb09a1edSShai Malin #define MSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2 10823fb09a1edSShai Malin #define MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 10824fb09a1edSShai Malin #define MSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4 10825fb09a1edSShai Malin #define MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 10826fb09a1edSShai Malin #define MSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6 108277a9b6b8fSYuval Mintz u8 flags1; 10828fb09a1edSShai Malin #define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 10829fb09a1edSShai Malin #define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0 10830fb09a1edSShai Malin #define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1 10831fb09a1edSShai Malin #define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1 10832fb09a1edSShai Malin #define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1 10833fb09a1edSShai Malin #define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2 10834fb09a1edSShai Malin #define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 10835fb09a1edSShai Malin #define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3 10836fb09a1edSShai Malin #define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1 10837fb09a1edSShai Malin #define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4 10838fb09a1edSShai Malin #define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1 10839fb09a1edSShai Malin #define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5 10840fb09a1edSShai Malin #define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 10841fb09a1edSShai Malin #define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6 10842fb09a1edSShai Malin #define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1 10843fb09a1edSShai Malin #define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7 108447a9b6b8fSYuval Mintz __le16 word0; 108457a9b6b8fSYuval Mintz __le16 word1; 108467a9b6b8fSYuval Mintz __le32 reg0; 108477a9b6b8fSYuval Mintz __le32 reg1; 108487a9b6b8fSYuval Mintz }; 108497a9b6b8fSYuval Mintz 10850a2e7699eSTomer Tayar /* Combined iSCSI and TCP storm connection of Mstorm */ 108517a9b6b8fSYuval Mintz struct mstorm_iscsi_tcp_conn_st_ctx { 108527a9b6b8fSYuval Mintz __le32 reserved_tcp[20]; 10853da090917STomer Tayar __le32 reserved_iscsi[12]; 108547a9b6b8fSYuval Mintz }; 108557a9b6b8fSYuval Mintz 10856a2e7699eSTomer Tayar /* The iscsi storm context of Ustorm */ 108577a9b6b8fSYuval Mintz struct ustorm_iscsi_conn_st_ctx { 108587a9b6b8fSYuval Mintz __le32 reserved[52]; 108597a9b6b8fSYuval Mintz }; 108607a9b6b8fSYuval Mintz 10861a2e7699eSTomer Tayar /* iscsi connection context */ 10862fb09a1edSShai Malin struct iscsi_conn_context { 108637a9b6b8fSYuval Mintz struct ystorm_iscsi_conn_st_ctx ystorm_st_context; 108647a9b6b8fSYuval Mintz struct pstorm_iscsi_tcp_conn_st_ctx pstorm_st_context; 108657a9b6b8fSYuval Mintz struct regpair pstorm_st_padding[2]; 108667a9b6b8fSYuval Mintz struct pb_context xpb2_context; 108677a9b6b8fSYuval Mintz struct xstorm_iscsi_tcp_conn_st_ctx xstorm_st_context; 108687a9b6b8fSYuval Mintz struct regpair xstorm_st_padding[2]; 10869fb09a1edSShai Malin struct xstorm_iscsi_conn_ag_ctx xstorm_ag_context; 10870fb09a1edSShai Malin struct tstorm_iscsi_conn_ag_ctx tstorm_ag_context; 108717a9b6b8fSYuval Mintz struct regpair tstorm_ag_padding[2]; 108727a9b6b8fSYuval Mintz struct timers_context timer_context; 10873fb09a1edSShai Malin struct ustorm_iscsi_conn_ag_ctx ustorm_ag_context; 108747a9b6b8fSYuval Mintz struct pb_context upb_context; 108757a9b6b8fSYuval Mintz struct tstorm_iscsi_conn_st_ctx tstorm_st_context; 108767a9b6b8fSYuval Mintz struct regpair tstorm_st_padding[2]; 10877fb09a1edSShai Malin struct mstorm_iscsi_conn_ag_ctx mstorm_ag_context; 108787a9b6b8fSYuval Mintz struct mstorm_iscsi_tcp_conn_st_ctx mstorm_st_context; 108797a9b6b8fSYuval Mintz struct ustorm_iscsi_conn_st_ctx ustorm_st_context; 108807a9b6b8fSYuval Mintz }; 108817a9b6b8fSYuval Mintz 10882a2e7699eSTomer Tayar /* iSCSI init params passed by driver to FW in iSCSI init ramrod */ 108837a9b6b8fSYuval Mintz struct iscsi_init_ramrod_params { 108847a9b6b8fSYuval Mintz struct iscsi_spe_func_init iscsi_init_spe; 108857a9b6b8fSYuval Mintz struct tcp_init_params tcp_init; 108867a9b6b8fSYuval Mintz }; 108877a9b6b8fSYuval Mintz 10888fb09a1edSShai Malin struct ystorm_iscsi_conn_ag_ctx { 108897a9b6b8fSYuval Mintz u8 byte0; 108907a9b6b8fSYuval Mintz u8 byte1; 108917a9b6b8fSYuval Mintz u8 flags0; 10892fb09a1edSShai Malin #define YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1 10893fb09a1edSShai Malin #define YSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0 10894fb09a1edSShai Malin #define YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1 10895fb09a1edSShai Malin #define YSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1 10896fb09a1edSShai Malin #define YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 10897fb09a1edSShai Malin #define YSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2 10898fb09a1edSShai Malin #define YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 10899fb09a1edSShai Malin #define YSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4 10900fb09a1edSShai Malin #define YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 10901fb09a1edSShai Malin #define YSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6 109027a9b6b8fSYuval Mintz u8 flags1; 10903fb09a1edSShai Malin #define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 10904fb09a1edSShai Malin #define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0 10905fb09a1edSShai Malin #define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1 10906fb09a1edSShai Malin #define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1 10907fb09a1edSShai Malin #define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1 10908fb09a1edSShai Malin #define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2 10909fb09a1edSShai Malin #define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 10910fb09a1edSShai Malin #define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3 10911fb09a1edSShai Malin #define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1 10912fb09a1edSShai Malin #define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4 10913fb09a1edSShai Malin #define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1 10914fb09a1edSShai Malin #define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5 10915fb09a1edSShai Malin #define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 10916fb09a1edSShai Malin #define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6 10917fb09a1edSShai Malin #define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1 10918fb09a1edSShai Malin #define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7 109197a9b6b8fSYuval Mintz u8 byte2; 109207a9b6b8fSYuval Mintz u8 byte3; 109217a9b6b8fSYuval Mintz __le16 word0; 109227a9b6b8fSYuval Mintz __le32 reg0; 109237a9b6b8fSYuval Mintz __le32 reg1; 109247a9b6b8fSYuval Mintz __le16 word1; 109257a9b6b8fSYuval Mintz __le16 word2; 109267a9b6b8fSYuval Mintz __le16 word3; 109277a9b6b8fSYuval Mintz __le16 word4; 109287a9b6b8fSYuval Mintz __le32 reg2; 109297a9b6b8fSYuval Mintz __le32 reg3; 109307a9b6b8fSYuval Mintz }; 10931c965db44STomer Tayar 10932fe56b9e6SYuval Mintz #endif 10933