| /openbmc/linux/Documentation/devicetree/bindings/net/ |
| H A D | mdio-mux-gpio.yaml | 39 pair of GPIO lines. Child busses 2 and 3 populated with 4
44 gpios = <&gpio1 3 0>, <&gpio1 4 0>;
56 marvell,reg-init = <3 0x10 0 0x5777>,
57 <3 0x11 0 0x00aa>,
58 <3 0x12 0 0x4105>,
59 <3 0x13 0 0x0a60>;
65 marvell,reg-init = <3 0x10 0 0x5777>,
66 <3 0x11 0 0x00aa>,
67 <3 0x12 0 0x4105>,
68 <3 0x13 0 0x0a60>;
[all …]
|
| /openbmc/u-boot/arch/arm/cpu/armv8/ |
| H A D | cache.S | 26 lsl x12, x0, #1
27 msr csselr_el1, x12 /* select cache level */
33 and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */
37 /* x12 <- cache level << 1 */
47 orr x9, x12, x7 /* map way and level to cisw value */
86 lsl x12, x0, #1
87 add x12, x12, x0 /* x0 <- tripled cache level */
88 lsr x12, x10, x12
89 and x12, x12, #7 /* x12 <- cache type */
90 cmp x12, #2
[all …]
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| /openbmc/linux/tools/perf/arch/x86/tests/ |
| H A D | insn-x86-dat-32.c | 12 {{0x62, 0x81, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "",
14 {{0x62, 0x88, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "",
16 {{0x62, 0x90, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "",
18 {{0x62, 0x98, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "",
20 {{0x62, 0xa0, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "",
22 {{0x62, 0xa8, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "",
24 {{0x62, 0xb0, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "",
26 {{0x62, 0xb8, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "",
30 {{0x62, 0x05, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "",
32 {{0x62, 0x14, 0x01, }, 3, 0, "", "",
[all …]
|
| H A D | insn-x86-dat-src.c | 149 asm volatile("kshiftrw $0x12,%k6,%k5"); in main()
151 asm volatile("kshiftlw $0x12,%k6,%k5"); in main()
443 /* AVX-512: Op code 0f 38 3a */ in main()
448 /* AVX-512: Op code 0f 38 3b */ in main()
454 /* AVX-512: Op code 0f 38 3d */ in main()
460 /* AVX-512: Op code 0f 38 3f */ in main()
982 /* AVX-512: Op code 0f 3a 03 */ in main()
984 asm volatile("valignd $0x12,%zmm28,%zmm29,%zmm30"); in main()
985 asm volatile("valignq $0x12,%zmm25,%zmm26,%zmm27"); in main()
987 /* AVX-512: Op code 0f 3a 08 */ in main()
[all …]
|
| H A D | insn-x86-dat-64.c | 14 {{0x48, 0x0f, 0x41, 0x88, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
16 {{0x66, 0x0f, 0x41, 0x88, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
20 {{0x48, 0x0f, 0x44, 0x88, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
22 {{0x66, 0x0f, 0x44, 0x88, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
24 {{0x0f, 0x90, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
26 {{0x0f, 0x91, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
28 {{0x0f, 0x92, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
30 {{0x0f, 0x92, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
32 {{0x0f, 0x92, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
34 {{0x0f, 0x93, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
[all …]
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| /openbmc/linux/drivers/gpu/drm/vc4/ |
| H A D | vc4_hdmi_phy.c | 15 #define VC4_HDMI_TX_PHY_RESET_CTL_TX_CK_RESET BIT(3)
57 #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELCK_MASK VC4_MASK(3, 0)
95 #define VC4_HDMI_TX_PHY_PLL_CFG_PDIV_MASK VC4_MASK(3, 0)
254 struct phy_lane_settings channel[3];
262 {{0x0, 0x0A}, 0x12, 0x0},
263 {{0x0, 0x0A}, 0x12, 0x0},
264 {{0x0, 0x0A}, 0x12, 0x0}
271 {{0x0, 0x09}, 0x12, 0x0},
272 {{0x0, 0x09}, 0x12, 0x0},
273 {{0x0, 0x09}, 0x12, 0x0}
[all …]
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| /openbmc/linux/arch/arm64/crypto/ |
| H A D | poly1305-armv8.pl | 2 # SPDX-License-Identifier: GPL-1.0+ OR BSD-3-Clause
44 my ($ctx,$inp,$len,$padbit) = map("x$_",(0..3));
187 and $h2,$d2,#3
301 and $h2,$d2,#3
313 and x12,$h0,#0x03ffffff // base 2^64 -> base 2^26
325 str w14,[$ctx,#16*3] // r2
369 lsr $h1,x12,#12
370 adds $h0,$h0,x12,lsl#52
393 extr x12,$h1,$h0,#52
394 and x12,x12,#0x03ffffff
[all …]
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| /openbmc/linux/arch/mips/boot/dts/cavium-octeon/ |
| H A D | octeon_3xxx.dts | 3 * OCTEON 3XXX, 5XXX, 63XX device tree skeleton.
21 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
23 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
33 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
35 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
42 marvell,reg-init = <3 0x10 0 0x5777>,
43 <3 0x11 0 0x00aa>,
44 <3 0x12 0 0x4105>,
45 <3 0x13 0 0x0a60>;
47 phy3: ethernet-phy@3 {
[all …]
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| H A D | octeon_68xx.dts | 49 interrupts = <7 0>, <7 1>, <7 2>, <7 3>,
67 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
69 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
77 marvell,reg-init = <3 0x10 0 0x5777>,
78 <3 0x11 0 0x00aa>,
79 <3 0x12 0 0x4105>,
80 <3 0x13 0 0x0a60>;
86 marvell,reg-init = <3 0x10 0 0x5777>,
87 <3 0x11 0 0x00aa>,
88 <3 0x12 0 0x4105>,
[all …]
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| /openbmc/u-boot/drivers/net/phy/ |
| H A D | mscc.c | 30 #define MSCC_PHY_PAGE_EXT3 0x0003 /* Extended registers - page 3 */
38 #define PARALLEL_DET_IGNORE_ADVERTISED BIT(3)
52 #define MIIM_AUX_CNTRL_STAT_SPEED_POS (3)
73 #define MEDIA_OP_MODE_100BASEFX 3
106 #define RGMII_RX_CLK_DELAY_WIDTH (3)
109 #define RGMII_TX_CLK_DELAY_WIDTH (3)
115 #define EDGE_RATE_CNTL_WIDTH (3)
121 /* Extended Page 3 Register 22E3 */
132 #define MICRO_CLK_EN BIT(3)
177 #define PROC_CMD_NOP GENMASK(3, 0)
[all …]
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| /openbmc/linux/arch/arm/crypto/ |
| H A D | chacha-neon-core.S | 96 // x1 = shuffle32(x1, MASK(0, 3, 2, 1))
98 // x2 = shuffle32(x2, MASK(1, 0, 3, 2))
100 // x3 = shuffle32(x3, MASK(2, 1, 0, 3))
126 // x1 = shuffle32(x1, MASK(2, 1, 0, 3))
128 // x2 = shuffle32(x2, MASK(1, 0, 3, 2))
130 // x3 = shuffle32(x3, MASK(0, 3, 2, 1))
146 // x0..3 = s0..3
204 .Lctrinc: .word 0, 1, 2, 3
205 .Lrol8_table: .byte 3, 0, 1, 2, 7, 4, 5, 6
228 // x0..15[0-3] = s0..15[0-3]
[all …]
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| H A D | chacha-scalar-core.S | 39 X12 .req r10
106 // quarterrounds: (x0, x4, x8, x12) and (x1, x5, x9, x13)
107 _halfround X0, X4, X8_X10, X12, X1, X5, X9_X11, X13
121 // quarterrounds: (x0, x5, x10, x15) and (x1, x6, x11, x12)
122 _halfround X0, X5, X8_X10, X15, X1, X6, X9_X11, X12
144 // Registers contain x0-x9,x12-x15.
151 // Registers contain x0-x9,x12-x15.
152 // x4-x7 are rotated by 'brot'; x12-x15 are rotated by 'drot'.
154 // Free up some registers (r8-r12,r14) by pushing (x8-x9,x12-x15).
155 push {X8_X10, X9_X11, X12, X13, X14, X15}
[all …]
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| /openbmc/linux/drivers/memory/ |
| H A D | mtk-smi.c | 59 #define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2)
64 * every port have 4 bit to control, bit[port + 3] control virtual or physical,
69 #define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3)
70 /* mt2701 domain should be set to 3 */
94 #define MTK_SMI_FLAG_CFG_PORT_SEC_CTL BIT(3)
121 #define MTK_SMI_SUB_COM_GALS_REQ_CLK_NR 3
205 /* bit[port + 3] controls the virtual or physical */ in mtk_smi_larb_config_port_gen1()
288 [1] = {0x12, 0x02, 0x14, 0x14, 0x01, 0x18, 0x0a,},
289 [2] = {0x12, 0x12, 0x12, 0x12, 0x0a,},
290 [3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,},
[all …]
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| /openbmc/linux/drivers/gpu/drm/radeon/ |
| H A D | rv770_smc.c | 202 0x0C, 0x14, 0x12, 0xAA,
221 0x0C, 0x14, 0x12, 0xAA,
240 0x0C, 0x14, 0x12, 0xAA,
247 0x12, 0x05, 0x12, 0x05,
248 0x12, 0x05, 0x12, 0x05,
249 0x12, 0x05, 0x12, 0x05,
250 0x12, 0x05, 0x12, 0x05,
251 0x12, 0x05, 0x12, 0x05,
252 0x12, 0x05, 0x12, 0x05,
253 0x12, 0x05, 0x12, 0x05,
[all …]
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| /openbmc/linux/drivers/clk/mmp/ |
| H A D | clk-of-pxa168.c | 86 {PXA168_CLK_PLL1_6, "pll1_6", "pll1_2", 1, 3, 0},
95 {PXA168_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0},
97 {PXA168_CLK_PLL1_2_3_16, "pll1_2_3_16", "pll1_2", 3, 16, 0},
163 …arent_names, ARRAY_SIZE(twsi_parent_names), CLK_SET_RATE_PARENT, APBC_TWSI0, 4, 3, 0, &twsi0_lock},
164 …arent_names, ARRAY_SIZE(twsi_parent_names), CLK_SET_RATE_PARENT, APBC_TWSI1, 4, 3, 0, &twsi1_lock},
165 …{0, "kpc_mux", kpc_parent_names, ARRAY_SIZE(kpc_parent_names), CLK_SET_RATE_PARENT, APBC_KPC, 4, 3…
166 …m_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM0, 4, 3, 0, &pwm0_lock},
167 …m_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM1, 4, 3, 0, &pwm1_lock},
168 …m_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM2, 4, 3, 0, &pwm2_lock},
169 …m_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM3, 4, 3, 0, &pwm3_lock},
[all …]
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| /openbmc/qemu/target/ppc/translate/ |
| H A D | vsx-ops.c.inc | 32 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
38 GEN_HANDLER2_E(name, opcname, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
44 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2)
85 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
86 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
87 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
104 GEN_VSX_XFORM_300_EO(xsxsigqp, 0x04, 0x19, 0x12, 0x00000001),
129 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
133 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
141 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
[all …]
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| /openbmc/qemu/tests/unit/ |
| H A D | test-crypto-der.c | 30 "\x00\xb9\xe1\x22\xdb\x56\x2f\xb6\xf7\xf0\x0a\x87\x43\x07\x12\xdb"
32 "\xc8\x34\x0c\x12\x4f\x11\x90\xc6\xc2\xa5\xd0\xcd\xfb\xfc\x2c\x95"
35 "\x02\x03\x01\x00\x01" /* INTEGER, offset: 74, length: 3 */
54 "\xb8\x9d\x58\xf5\x12\x38\x03\x22\x94\x9d\x99\xf4\x42\x5e\x68\x81"
80 "\x02\x03\x01\x00\x01" /* INTEGER, offset 268, length 3 */
100 "\x00\xe8\x26\xd1\xf9\xa0\xd3\x0e\x3f\x2f\x89\x9b\x94\x16\x12\xd1"
106 "\xae\x3f\x49\x54\xd2\x2b\xac\x28\x39\x88\x31\x42\x12\x08\xea\x0b"
112 "\xdd\xa8\x41\xa1\x12\x84\x3c\xf8\xc2\x13\x3e\xb8\x4b\x22\x01\xac"
115 "\x6d\x0b\x12\x0b\xc9\x6d\x59\xfc\x33\x03\x36\x01\x12\x09\x72\x74"
116 "\x5e\x98\x65\x66\x2f\x3a\xde\xd8\xd4\xee\x6f\x82\xe6\x36\x49\x12"
[all …]
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| /openbmc/linux/arch/x86/crypto/ |
| H A D | chacha-ssse3-x86_64.S | 68 # x1 = shuffle32(x1, MASK(0, 3, 2, 1))
70 # x2 = shuffle32(x2, MASK(1, 0, 3, 2))
72 # x3 = shuffle32(x3, MASK(2, 1, 0, 3))
101 # x1 = shuffle32(x1, MASK(2, 1, 0, 3))
103 # x2 = shuffle32(x2, MASK(1, 0, 3, 2))
105 # x3 = shuffle32(x3, MASK(0, 3, 2, 1))
122 # x0..3 = s0..3
245 # x0..15[0-3] = s0..3[0..3]
270 # x0..3 on stack
280 # x12 += counter values 0-3
[all …]
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| /openbmc/linux/tools/include/uapi/linux/ |
| H A D | fs.h | 46 #define SEEK_DATA 3 /* seek to the next data */
148 #define BLKROSET _IO(0x12,93) /* set device read-only (0 = read-write) */
149 #define BLKROGET _IO(0x12,94) /* get read-only status (0 = read_write) */
150 #define BLKRRPART _IO(0x12,95) /* re-read partition table */
151 #define BLKGETSIZE _IO(0x12,96) /* return device size /512 (long *arg) */
152 #define BLKFLSBUF _IO(0x12,97) /* flush buffer cache */
153 #define BLKRASET _IO(0x12,98) /* set read ahead for block device */
154 #define BLKRAGET _IO(0x12,99) /* get current read ahead setting */
155 #define BLKFRASET _IO(0x12,100)/* set filesystem (mm/filemap.c) read-ahead */
156 #define BLKFRAGET _IO(0x12,101)/* get filesystem (mm/filemap.c) read-ahead */
[all …]
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| /openbmc/linux/include/uapi/linux/ |
| H A D | fs.h | 46 #define SEEK_DATA 3 /* seek to the next data */
148 #define BLKROSET _IO(0x12,93) /* set device read-only (0 = read-write) */
149 #define BLKROGET _IO(0x12,94) /* get read-only status (0 = read_write) */
150 #define BLKRRPART _IO(0x12,95) /* re-read partition table */
151 #define BLKGETSIZE _IO(0x12,96) /* return device size /512 (long *arg) */
152 #define BLKFLSBUF _IO(0x12,97) /* flush buffer cache */
153 #define BLKRASET _IO(0x12,98) /* set read ahead for block device */
154 #define BLKRAGET _IO(0x12,99) /* get current read ahead setting */
155 #define BLKFRASET _IO(0x12,100)/* set filesystem (mm/filemap.c) read-ahead */
156 #define BLKFRAGET _IO(0x12,101)/* get filesystem (mm/filemap.c) read-ahead */
[all …]
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| /openbmc/linux/drivers/mfd/ |
| H A D | stmpe.h | 124 #define STMPE801_REG_GPIO_DIR 0x12
134 #define STMPE811_IRQ_FIFO_FULL 3
152 #define STMPE811_REG_GPIO_MP_STA 0x12
164 #define STMPE811_SYS_CTRL2_TS_OFF (1 << 3)
180 #define STMPE1600_REG_GPSR_LSB 0x12
205 #define STMPE1601_REG_IER_MSB 0x12
232 #define STMPE1601_SYS_CTRL_ENABLE_GPIO (1 << 3)
238 #define STPME1601_AUTOSLEEP_ENABLE (1 << 3)
246 #define STMPE1801_IRQ_GPIOC 3
264 #define STMPE1801_REG_GPIO_SET_HIGH 0x12
[all …]
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| /openbmc/u-boot/arch/arm/mach-imx/mx5/ |
| H A D | soc.c | 103 {"sata", MAKE_CFGVAL(0x28, 0x00, 0x00, 0x12)},
104 {"escpi1:0", MAKE_CFGVAL(0x38, 0x20, 0x00, 0x12)},
105 {"escpi1:1", MAKE_CFGVAL(0x38, 0x20, 0x04, 0x12)},
106 {"escpi1:2", MAKE_CFGVAL(0x38, 0x20, 0x08, 0x12)},
107 {"escpi1:3", MAKE_CFGVAL(0x38, 0x20, 0x0c, 0x12)},
109 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
110 {"esdhc2", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
111 {"esdhc3", MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)},
112 {"esdhc4", MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)},
|
| /openbmc/linux/tools/testing/selftests/arm64/abi/ |
| H A D | syscall-abi-asm.S | 35 | (((\nw) & 3) << 13) \
46 | (((\nw) & 3) << 13) \
89 // Load ZA and ZT0 if enabled - uses x12 as scratch due to SME LDR
95 add x12, x12, #1
96 cmp x1, x12
114 ldp x12, x13, [x2], #16
158 ldr z3, [x2, #3, MUL VL]
201 ldr p3, [x2, #3, MUL VL]
224 stp x12, x13, [x2], #16
263 // Save ZA if it's enabled - uses x12 as scratch due to SME STR
[all …]
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| /openbmc/linux/drivers/net/phy/ |
| H A D | mediatek-ge-soc.c | 35 #define MTK_PHY_TXVLD_DA_RG 0x12
222 #define MTK_PHY_LED_ON_LINKDOWN BIT(3)
234 #define MTK_PHY_LED_BLINK_100RX BIT(3)
329 * 3.Fetch AD_CAL_COMP_OUT.
374 rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]); in rext_cal_efuse()
375 rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]); in rext_cal_efuse()
390 MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]); in tx_offset_fill_result()
402 tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]); in tx_offset_cal_efuse()
449 MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]); in tx_amp_fill_result()
470 MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8); in tx_amp_fill_result()
[all …]
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| /openbmc/linux/drivers/iio/imu/st_lsm6dsx/ |
| H A D | st_lsm6dsx_core.c | 5 * The ST LSM6DSx IMU MEMS series consists of 3D digital accelerometer
6 * and 3D digital gyroscope system-in-package with a digital I2C/SPI serial
35 * - FIFO size: 3KB
42 * - FIFO size: 3KB
86 IIO_CHAN_SOFT_TIMESTAMP(3),
93 IIO_CHAN_SOFT_TIMESTAMP(3),
100 IIO_CHAN_SOFT_TIMESTAMP(3),
147 .odr_avl[3] = { 238000, 0x04 },
160 .odr_avl[3] = { 238000, 0x04 },
170 .mask = GENMASK(4, 3),
[all …]
|