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/openbmc/linux/drivers/media/dvb-frontends/
H A Dmb86a16.c730 int v, int R, in swp_info_get() argument
740 crnt_swp_freq = fOSC_start * 1000 + v * swp_ofs; in swp_info_get()
758 static int swp_freq_calcuation(struct mb86a16_state *state, int i, int v, int *V, int vmax, int vm… in swp_freq_calcuation() argument
763 if ((i % 2 == 1) && (v <= vmax)) { in swp_freq_calcuation()
764 /* positive v (case 1) */ in swp_freq_calcuation()
765 if ((v - 1 == vmin) && in swp_freq_calcuation()
766 (*(V + 30 + v) >= 0) && in swp_freq_calcuation()
767 (*(V + 30 + v - 1) >= 0) && in swp_freq_calcuation()
768 (*(V + 30 + v - 1) > *(V + 30 + v)) && in swp_freq_calcuation()
769 (*(V + 30 + v - 1) > SIGMIN)) { in swp_freq_calcuation()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx5/
H A Dcrm_regs.h80 #define MXC_CCM_CCR_OSCNT(v) ((v) & 0xFF) argument
92 #define MXC_CCM_CCSR_STEP_SEL(v) (((v) & 0x3) << 7) argument
96 #define MXC_CCM_CCSR_PLL2_DIV_PODF(v) (((v) & 0x3) << 5) argument
100 #define MXC_CCM_CCSR_PLL3_DIV_PODF(v) (((v) & 0x3) << 3) argument
109 #define MXC_CCM_CACRR_ARM_PODF(v) ((v) & 0x7) argument
113 #define MXC_CCM_CBCDR_DDR_HIFREQ_SEL (0x1 << 30)
116 #define MXC_CCM_CBCDR_DDR_PODF(v) (((v) & 0x7) << 27) argument
122 #define MXC_CCM_CBCDR_EMI_PODF(v) (((v) & 0x7) << 22) argument
126 #define MXC_CCM_CBCDR_AXI_B_PODF(v) (((v) & 0x7) << 19) argument
130 #define MXC_CCM_CBCDR_AXI_A_PODF(v) (((v) & 0x7) << 16) argument
[all …]
/openbmc/linux/include/linux/
H A Dinet.h12 * $Id: Space.c,v 0.8.4.5 1992/12/12 19:25:04 bir7 Exp $
13 * $Id: arp.c,v 0.8.4.6 1993/01/28 22:30:00 bir7 Exp $
14 * $Id: arp.h,v 0.8.4.6 1993/01/28 22:30:00 bir7 Exp $
15 * $Id: dev.c,v 0.8.4.13 1993/01/23 18:00:11 bir7 Exp $
16 * $Id: dev.h,v 0.8.4.7 1993/01/23 18:00:11 bir7 Exp $
17 * $Id: eth.c,v 0.8.4.4 1993/01/22 23:21:38 bir7 Exp $
18 * $Id: eth.h,v 0.8.4.1 1992/11/10 00:17:18 bir7 Exp $
19 * $Id: icmp.c,v 0.8.4.9 1993/01/23 18:00:11 bir7 Exp $
20 * $Id: icmp.h,v 0.8.4.2 1992/11/15 14:55:30 bir7 Exp $
21 * $Id: ip.c,v 0.8.4.8 1992/12/12 19:25:04 bir7 Exp $
[all …]
/openbmc/linux/drivers/hwmon/
H A Dabituguru3.c191 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
192 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
193 { "MCH 2.5V", 5, 0, 20, 1, 0 },
194 { "ICH 1.05V", 6, 0, 10, 1, 0 },
195 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
196 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
197 { "ATX +5V", 9, 0, 30, 1, 0 },
198 { "+3.3V", 10, 0, 20, 1, 0 },
199 { "5VSB", 11, 0, 30, 1, 0 },
213 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx6/
H A Dcrm_regs.h411 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21) argument
414 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << 18) argument
417 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15) argument
421 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21) argument
424 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18) argument
428 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) (((v) & 0x7) << 15) argument
431 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16) argument
441 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \ argument
443 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) : \
444 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v))
[all …]
/openbmc/linux/drivers/staging/media/sunxi/cedrus/
H A Dcedrus_regs.h13 #define SHIFT_AND_MASK_BITS(v, h, l) \ argument
14 (((unsigned long)(v) << (l)) & GENMASK(h, l))
68 #define VE_SECONDARY_OUT_FMT_TILED_32_NV12 (0x00 << 30)
69 #define VE_SECONDARY_OUT_FMT_EXT (0x01 << 30)
70 #define VE_SECONDARY_OUT_FMT_YU12 (0x02 << 30)
71 #define VE_SECONDARY_OUT_FMT_YV12 (0x03 << 30)
95 #define VE_DEC_MPEG_MP12HDR_SLICE_TYPE(t) SHIFT_AND_MASK_BITS(t, 30, 28)
104 #define VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST(v) \ argument
105 ((v) ? BIT(7) : 0)
106 #define VE_DEC_MPEG_MP12HDR_FRAME_PRED_FRAME_DCT(v) \ argument
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dsiul.h50 #define SIUL2_MSCR_DDR_DO_TRIM(v) ((v) & 0xC0000000) argument
51 #define SIUL2_MSCR_DDR_DO_TRIM_MIN (0 << 30)
52 #define SIUL2_MSCR_DDR_DO_TRIM_50PS (1 << 30)
53 #define SIUL2_MSCR_DDR_DO_TRIM_100PS (2 << 30)
54 #define SIUL2_MSCR_DDR_DO_TRIM_150PS (3 << 30)
56 #define SIUL2_MSCR_DDR_INPUT(v) ((v) & 0x20000000) argument
60 #define SIUL2_MSCR_DDR_SEL(v) ((v) & 0x18000000) argument
64 #define SIUL2_MSCR_DDR_ODT(v) ((v) & 0x07000000) argument
73 #define SIUL2_MSCR_DCYCLE_TRIM(v) ((v) & 0x00C00000) argument
78 #define SIUL2_MSCR_OBE(v) ((v) & 0x00200000) argument
[all …]
/openbmc/linux/arch/arm64/crypto/
H A Dsha512-ce-core.S85 ld1 {v\rc1\().2d}, [x4], #16
87 add v5.2d, v\rc0\().2d, v\in0\().2d
88 ext v6.16b, v\i2\().16b, v\i3\().16b, #8
90 ext v7.16b, v\i1\().16b, v\i2\().16b, #8
91 add v\i3\().2d, v\i3\().2d, v5.2d
93 ext v5.16b, v\in3\().16b, v\in4\().16b, #8
94 sha512su0 v\in0\().2d, v\in1\().2d
98 sha512su1 v\in0\().2d, v\in2\().2d, v5.2d
100 add v\i4\().2d, v\i1\().2d, v\i3\().2d
101 sha512h2 q\i3, q\i1, v\i0\().2d
[all …]
/openbmc/linux/sound/isa/sb/
H A Demu8000_patch.c28 /* reserve all 30 voices for loading */ in snd_emu8000_open_dma()
35 EMU8000_VTFT_WRITE(emu, 30, 0); in snd_emu8000_open_dma()
36 EMU8000_PSST_WRITE(emu, 30, 0x1d8); in snd_emu8000_open_dma()
37 EMU8000_CSL_WRITE(emu, 30, 0x1e0); in snd_emu8000_open_dma()
38 EMU8000_CCCA_WRITE(emu, 30, 0x1d8); in snd_emu8000_open_dma()
151 if (sp->v.size == 0) in snd_emu8000_sample_new()
155 if (sp->v.loopstart > sp->v.loopend) in snd_emu8000_sample_new()
156 swap(sp->v.loopstart, sp->v.loopend); in snd_emu8000_sample_new()
159 truesize = sp->v.size; in snd_emu8000_sample_new()
160 if (sp->v.mode_flags & (SNDRV_SFNT_SAMPLE_BIDIR_LOOP|SNDRV_SFNT_SAMPLE_REVERSE_LOOP)) in snd_emu8000_sample_new()
[all …]
/openbmc/linux/drivers/gpu/drm/exynos/
H A Dregs-scaler.h206 #define SCALER_SRC_CFG_SET_BYTE_SWAP(v) SCALER_SET(v, 6, 5) argument
208 #define SCALER_SRC_CFG_SET_COLOR_FORMAT(v) SCALER_SET(v, 4, 0) argument
232 #define SCALER_SRC_SPAN_SET_C_SPAN(v) SCALER_SET(v, 29, 16) argument
234 #define SCALER_SRC_SPAN_SET_Y_SPAN(v) SCALER_SET(v, 13, 0) argument
238 #define SCALER_SRC_Y_POS_SET_YH_POS(v) SCALER_SET(v, 31, 16) argument
240 #define SCALER_SRC_Y_POS_SET_YV_POS(v) SCALER_SET(v, 15, 0) argument
244 #define SCALER_SRC_WH_SET_WIDTH(v) SCALER_SET(v, 29, 16) argument
246 #define SCALER_SRC_WH_SET_HEIGHT(v) SCALER_SET(v, 13, 0) argument
250 #define SCALER_SRC_C_POS_SET_CH_POS(v) SCALER_SET(v, 31, 16) argument
252 #define SCALER_SRC_C_POS_SET_CV_POS(v) SCALER_SET(v, 15, 0) argument
[all …]
/openbmc/openbmc/poky/bitbake/lib/toaster/toastergui/static/fonts/
H A Dfontawesome-webfont.svg34 <glyph unicode="&#xf000;" horiz-adv-x="1792" d="M1699 1350q0 -35 -43 -78l-632 -632v-768h320q26 0 45…
35 …v-1120q0 -50 -34 -89t-86 -60.5t-103.5 -32t-96.5 -10.5t-96.5 10.5t-103.5 32t-86 60.5t-34 89t34 89t8…
37 …30 -69 66v-768q0 -13 9.5 -22.5t22.5 -9.5h1472q13 0 22.5 9.5t9.5 22.5zM1664 1083v11v13.5t-0.5 13 t-…
42 …v-128q0 -26 19 -45t45 -19h128q26 0 45 19t19 45zM384 320v128q0 26 -19 45t-45 19h-128q-26 0 -45 -19t…
43 …v-384q0 -52 -38 -90t-90 -38h-512q-52 0 -90 38t-38 90v384q0 52 38 90t90 38h512q52 0 90 -38t38 -90zM…
44 …v-192q0 -40 -28 -68t-68 -28h-320q-40 0 -68 28t-28 68v192q0 40 28 68t68 28h320q40 0 68 -28t28 -68zM…
45 …v-192q0 -40 -28 -68t-68 -28h-320q-40 0 -68 28t-28 68v192q0 40 28 68t68 28h320q40 0 68 -28t28 -68zM…
48 …v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-224v-224q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22…
49 <glyph unicode="&#xf010;" horiz-adv-x="1664" d="M1024 736v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-576q-13 …
50 ….5 84.5t24.5 94.5q31 43 84 50t95 -25q146 -109 226.5 -270t80.5 -343zM896 1408v-640q0 -52 -38 -90t-9…
[all …]
H A Dglyphicons-halflings-regular.svg12 …v-224l158 158q7 7 18 8t19 -6l106 -106q7 -8 6 -19t-8 -18l-158 -158h224q10 0 18.5 -7.5t10.5 -17.5q6 …
13 …50 1100h200q21 0 35.5 -14.5t14.5 -35.5v-350h350q21 0 35.5 -14.5t14.5 -35.5v-200q0 -21 -14.5 -35.5t…
15 …6t-3 -14l-120 -160q-6 -8 -18 -14t-22 -6h-125v-100h275q10 0 13 -6t-3 -14l-120 -160q-6 -8 -18 -14t-2…
29 …5 -54.5t59 -29 t47 -7.5q22 0 50.5 7.5t60.5 24.5t58 41t43.5 61t17.5 80h174q-30 -171 -128 -278q-107 …
30 …v-16.5v-16.5q0 -36 -0.5 -57t-6.5 -61t-17 -65t-35 -57t-57 -50.5t-86 -31.5t-120 -13h-178l-2 -100h288…
31 <glyph unicode="&#x2212;" d="M250 700h800q21 0 35.5 -14.5t14.5 -35.5v-200q0 -21 -14.5 -35.5t-35.5 -…
32 …v-150q0 -21 -14.5 -35.5t-35.5 -14.5h-50v-100q0 -91 -49.5 -165.5t-130.5 -109.5q81 -35 130.5 -109.5t…
35 …v-42h-1200v42q0 21 15 39.5t35 18.5h30l468 746l-135 183q-10 16 -5.5 34t20.5 28t34 5.5t28 -20.5l111 …
36 …-13 -5.5t-5 12.5v550q0 10 5 12.5t13 -5.5zM918 618l264 264q8 8 13 5.5t5 -12.5v-550q0 -10 -5 -12.5t-…
38 <glyph unicode="&#xe001;" d="M700 650v-550h250q21 0 35.5 -14.5t14.5 -35.5v-50h-800v50q0 21 14.5 35.…
[all …]
/openbmc/linux/sound/soc/qcom/
H A Dlpass-sc7280.c113 struct lpass_variant *v = drvdata->variant; in sc7280_lpass_alloc_dma_channel() local
120 v->rdma_channels); in sc7280_lpass_alloc_dma_channel()
122 if (chan >= v->rdma_channels) in sc7280_lpass_alloc_dma_channel()
126 v->wrdma_channel_start + in sc7280_lpass_alloc_dma_channel()
127 v->wrdma_channels, in sc7280_lpass_alloc_dma_channel()
128 v->wrdma_channel_start); in sc7280_lpass_alloc_dma_channel()
130 if (chan >= v->wrdma_channel_start + v->wrdma_channels) in sc7280_lpass_alloc_dma_channel()
137 v->hdmi_rdma_channels); in sc7280_lpass_alloc_dma_channel()
138 if (chan >= v->hdmi_rdma_channels) in sc7280_lpass_alloc_dma_channel()
144 v->rxtx_rdma_channels); in sc7280_lpass_alloc_dma_channel()
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/fftw/fftw/
H A Drun-ptest4 /usr/bin/perl -w ./check.pl -r -c=30 -v `pwd`/bench
7 /usr/bin/perl -w ./check.pl -r -c=30 -v `pwd`/benchf
10 /usr/bin/perl -w ./check.pl -r -c=30 -v `pwd`/benchl
/openbmc/openbmc/poky/meta/conf/machine/include/microblaze/
H A Dfeature-microblaze-versions.inc19 m = re.search(r"^v(\d+)\.(\d+)", t)
27 return ("v%d.%02d" % version[0:2]) + (".a" if gcc else "")
29 return "v%d.%d" % version[0:2]
36 TUNEVALID[v8.30] = "MicroBlaze version 8.30"
53 TUNECONFLICTS[v8.30] = "v8.00 v8.10 v8.20"
54 TUNECONFLICTS[v8.40] = "v8.00 v8.10 v8.20 v8.30"
55 TUNECONFLICTS[v8.50] = "v8.00 v8.10 v8.20 v8.30 v8.40"
56 TUNECONFLICTS[v9.0] = "v8.00 v8.10 v8.20 v8.30 v8.40 v8.50"
57 TUNECONFLICTS[v9.1] = "v8.00 v8.10 v8.20 v8.30 v8.40 v8.50 v9.0"
58 TUNECONFLICTS[v9.2] = "v8.00 v8.10 v8.20 v8.30 v8.40 v8.50 v9.0 v9.1"
[all …]
/openbmc/linux/drivers/media/platform/nxp/
H A Dimx-pxp.h19 #define BF_PXP_CTRL_SFTRST(v) \ argument
20 (((v) << 31) & BM_PXP_CTRL_SFTRST)
22 #define BF_PXP_CTRL_CLKGATE(v) \ argument
23 (((v) << 30) & BM_PXP_CTRL_CLKGATE)
25 #define BF_PXP_CTRL_RSVD4(v) \ argument
26 (((v) << 29) & BM_PXP_CTRL_RSVD4)
28 #define BF_PXP_CTRL_EN_REPEAT(v) \ argument
29 (((v) << 28) & BM_PXP_CTRL_EN_REPEAT)
31 #define BF_PXP_CTRL_ENABLE_ROTATE1(v) \ argument
32 (((v) << 27) & BM_PXP_CTRL_ENABLE_ROTATE1)
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-imx8/sci/svc/pad/
H A Dapi.h22 #define SC_PAD_28FDSOI_DSE_18V_1MA 0U /* Drive strength of 1mA for 1.8v */
23 #define SC_PAD_28FDSOI_DSE_18V_2MA 1U /* Drive strength of 2mA for 1.8v */
24 #define SC_PAD_28FDSOI_DSE_18V_4MA 2U /* Drive strength of 4mA for 1.8v */
25 #define SC_PAD_28FDSOI_DSE_18V_6MA 3U /* Drive strength of 6mA for 1.8v */
26 #define SC_PAD_28FDSOI_DSE_18V_8MA 4U /* Drive strength of 8mA for 1.8v */
27 #define SC_PAD_28FDSOI_DSE_18V_10MA 5U /* Drive strength of 10mA for 1.8v */
28 #define SC_PAD_28FDSOI_DSE_18V_12MA 6U /* Drive strength of 12mA for 1.8v */
29 #define SC_PAD_28FDSOI_DSE_18V_HS 7U /* High-speed for 1.8v */
30 #define SC_PAD_28FDSOI_DSE_33V_2MA 0U /* Drive strength of 2mA for 3.3v */
31 #define SC_PAD_28FDSOI_DSE_33V_4MA 1U /* Drive strength of 4mA for 3.3v */
[all …]
/openbmc/linux/drivers/i3c/master/mipi-i3c-hci/
H A Dcmd_v1.c26 #define CMD_A0_ROC W0_BIT_(30)
27 #define CMD_A0_DEV_COUNT(v) FIELD_PREP(W0_MASK(29, 26), v) argument
28 #define CMD_A0_DEV_INDEX(v) FIELD_PREP(W0_MASK(20, 16), v) argument
29 #define CMD_A0_CMD(v) FIELD_PREP(W0_MASK(14, 7), v) argument
30 #define CMD_A0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v) argument
38 #define CMD_I1_DATA_BYTE_4(v) FIELD_PREP(W1_MASK(63, 56), v) argument
39 #define CMD_I1_DATA_BYTE_3(v) FIELD_PREP(W1_MASK(55, 48), v) argument
40 #define CMD_I1_DATA_BYTE_2(v) FIELD_PREP(W1_MASK(47, 40), v) argument
41 #define CMD_I1_DATA_BYTE_1(v) FIELD_PREP(W1_MASK(39, 32), v) argument
42 #define CMD_I1_DEF_BYTE(v) FIELD_PREP(W1_MASK(39, 32), v) argument
[all …]
/openbmc/qemu/tests/fp/
H A Dmeson.build10 # By default tests run with the usual 30s timeout; particularly
119 foreach k, v : softfloat_conv_tests
121 args: fptest_args + fptest_rounding_args + v.split(),
122 timeout: slow_fp_tests.get(k, 30),
126 foreach k, v : softfloat_tests
130 timeout: slow_fp_tests.get(k, 30),
131 suite: ['softfloat', 'softfloat-' + v])
139 timeout: slow_fp_tests.get('mulAdd', 30),
156 timeout: slow_fp_tests.get('log2', 30),
/openbmc/linux/drivers/media/pci/cx23885/
H A Dcx23885-f300.c47 udelay(30); in f300_send_byte()
49 udelay(30); in f300_send_byte()
52 udelay(30); in f300_send_byte()
62 udelay(30); in f300_get_byte()
65 udelay(30); in f300_get_byte()
87 udelay(30); in f300_xfer()
148 buf[4] = 0x02;/* B port, H/V */ in f300_set_voltage()
149 buf[5] = 0x00;/*13V v*/ in f300_set_voltage()
154 buf[5] = 0x01;/* 18V h*/ in f300_set_voltage()
/openbmc/linux/arch/mips/pic32/pic32mzda/
H A Dconfig.c28 u32 v; in pic32_conf_get_reg_field() local
30 v = readl(pic32_conf_base + offset); in pic32_conf_get_reg_field()
31 v >>= rshift; in pic32_conf_get_reg_field()
32 v &= mask; in pic32_conf_get_reg_field()
34 return v; in pic32_conf_get_reg_field()
39 u32 v; in pic32_conf_modify_atomic() local
43 v = readl(pic32_conf_base + offset); in pic32_conf_modify_atomic()
44 v &= ~mask; in pic32_conf_modify_atomic()
45 v |= (set & mask); in pic32_conf_modify_atomic()
46 writel(v, pic32_conf_base + offset); in pic32_conf_modify_atomic()
[all …]
/openbmc/bmcweb/redfish-core/schema/dmtf/csdl/
H A DCircuit_v1.xml186 <Annotation Term="OData.Description" String="AC 100-127V nominal."/>
198 <Annotation Term="OData.Description" String="AC 100-240V nominal."/>
202 <Annotation Term="OData.Description" String="AC 100-277V nominal."/>
206 <Annotation Term="OData.Description" String="AC 120V nominal."/>
210 <Annotation Term="OData.Description" String="AC 200-240V nominal."/>
214 <Annotation Term="OData.Description" String="AC 200-277V nominal."/>
218 <Annotation Term="OData.Description" String="AC 208V nominal."/>
222 <Annotation Term="OData.Description" String="AC 230V nominal."/>
226 <Annotation Term="OData.Description" String="AC 240V nominal."/>
230 <Annotation Term="OData.Description" String="AC 200-240V and DC 380V."/>
[all …]
/openbmc/u-boot/drivers/net/
H A Dpic32_mdio.c20 u32 v; in pic32_mdio_write() local
28 v = (addr << MIIMADD_PHYADDR_SHIFT) | (reg & MIIMADD_REGADDR); in pic32_mdio_write()
29 writel(v, &mii_regs->madr.raw); in pic32_mdio_write()
34 /* Wait 30 clock cycles for busy flag to be set */ in pic32_mdio_write()
46 u32 v; in pic32_mdio_read() local
54 v = (addr << MIIMADD_PHYADDR_SHIFT) | (reg & MIIMADD_REGADDR); in pic32_mdio_read()
55 writel(v, &mii_regs->madr.raw); in pic32_mdio_read()
60 /* Wait 30 clock cycles for busy flag to be set */ in pic32_mdio_read()
72 v = readl(&mii_regs->mrdd.raw); in pic32_mdio_read()
73 return v; in pic32_mdio_read()
/openbmc/linux/tools/testing/selftests/drivers/net/mlxsw/
H A Dblackhole_routes.sh56 ip -4 route add default vrf v$h1 nexthop via 192.0.2.2
57 ip -6 route add default vrf v$h1 nexthop via 2001:db8:1::2
62 ip -6 route del default vrf v$h1 nexthop via 2001:db8:1::2
63 ip -4 route del default vrf v$h1 nexthop via 192.0.2.2
72 ip -4 route add default vrf v$h2 nexthop via 198.51.100.2
73 ip -6 route add default vrf v$h2 nexthop via 2001:db8:2::2
78 ip -6 route del default vrf v$h2 nexthop via 2001:db8:2::2
79 ip -4 route del default vrf v$h2 nexthop via 198.51.100.2
122 ip -4 route add blackhole 198.51.100.0/30
127 busywait "$TIMEOUT" wait_for_offload ip -4 route show 198.51.100.0/30
[all …]
/openbmc/linux/arch/x86/include/asm/
H A Dsev-common.h15 #define GHCB_DATA(v) \ argument
16 (((unsigned long)(v) & ~GHCB_MSR_INFO_MASK) >> GHCB_DATA_LOW)
31 #define GHCB_MSR_INFO(v) ((v) & 0xfffUL) argument
32 #define GHCB_MSR_PROTO_MAX(v) (((v) >> 48) & 0xffff) argument
33 #define GHCB_MSR_PROTO_MIN(v) (((v) >> 32) & 0xffff) argument
42 #define GHCB_MSR_CPUID_REG_POS 30
52 (((unsigned long)(reg) & 0x3) << 30) | \
62 #define GHCB_MSR_REG_GPA_REQ_VAL(v) \ argument
64 (((u64)((v) & GENMASK_ULL(51, 0)) << 12) | \
69 #define GHCB_MSR_REG_GPA_RESP_VAL(v) \ argument
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