xref: /openbmc/linux/arch/x86/include/asm/sev-common.h (revision 69dcb1e3)
1b81fc74dSBrijesh Singh /* SPDX-License-Identifier: GPL-2.0 */
2b81fc74dSBrijesh Singh /*
3b81fc74dSBrijesh Singh  * AMD SEV header common between the guest and the hypervisor.
4b81fc74dSBrijesh Singh  *
5b81fc74dSBrijesh Singh  * Author: Brijesh Singh <brijesh.singh@amd.com>
6b81fc74dSBrijesh Singh  */
7b81fc74dSBrijesh Singh 
8b81fc74dSBrijesh Singh #ifndef __ASM_X86_SEV_COMMON_H
9b81fc74dSBrijesh Singh #define __ASM_X86_SEV_COMMON_H
10b81fc74dSBrijesh Singh 
11b81fc74dSBrijesh Singh #define GHCB_MSR_INFO_POS		0
12310f134eSBrijesh Singh #define GHCB_DATA_LOW			12
13310f134eSBrijesh Singh #define GHCB_MSR_INFO_MASK		(BIT_ULL(GHCB_DATA_LOW) - 1)
14b81fc74dSBrijesh Singh 
15310f134eSBrijesh Singh #define GHCB_DATA(v)			\
16310f134eSBrijesh Singh 	(((unsigned long)(v) & ~GHCB_MSR_INFO_MASK) >> GHCB_DATA_LOW)
17310f134eSBrijesh Singh 
18310f134eSBrijesh Singh /* SEV Information Request/Response */
19b81fc74dSBrijesh Singh #define GHCB_MSR_SEV_INFO_RESP		0x001
20b81fc74dSBrijesh Singh #define GHCB_MSR_SEV_INFO_REQ		0x002
21dbc4c70eSBorislav Petkov 
22b81fc74dSBrijesh Singh #define GHCB_MSR_SEV_INFO(_max, _min, _cbit)	\
23dbc4c70eSBorislav Petkov 	/* GHCBData[63:48] */			\
24dbc4c70eSBorislav Petkov 	((((_max) & 0xffff) << 48) |		\
25dbc4c70eSBorislav Petkov 	 /* GHCBData[47:32] */			\
26dbc4c70eSBorislav Petkov 	 (((_min) & 0xffff) << 32) |		\
27dbc4c70eSBorislav Petkov 	 /* GHCBData[31:24] */			\
28dbc4c70eSBorislav Petkov 	 (((_cbit) & 0xff)  << 24) |		\
29b81fc74dSBrijesh Singh 	 GHCB_MSR_SEV_INFO_RESP)
30dbc4c70eSBorislav Petkov 
31b81fc74dSBrijesh Singh #define GHCB_MSR_INFO(v)		((v) & 0xfffUL)
32dbc4c70eSBorislav Petkov #define GHCB_MSR_PROTO_MAX(v)		(((v) >> 48) & 0xffff)
33dbc4c70eSBorislav Petkov #define GHCB_MSR_PROTO_MIN(v)		(((v) >> 32) & 0xffff)
34b81fc74dSBrijesh Singh 
35310f134eSBrijesh Singh /* CPUID Request/Response */
36b81fc74dSBrijesh Singh #define GHCB_MSR_CPUID_REQ		0x004
37b81fc74dSBrijesh Singh #define GHCB_MSR_CPUID_RESP		0x005
38b81fc74dSBrijesh Singh #define GHCB_MSR_CPUID_FUNC_POS		32
39b81fc74dSBrijesh Singh #define GHCB_MSR_CPUID_FUNC_MASK	0xffffffff
40b81fc74dSBrijesh Singh #define GHCB_MSR_CPUID_VALUE_POS	32
41b81fc74dSBrijesh Singh #define GHCB_MSR_CPUID_VALUE_MASK	0xffffffff
42b81fc74dSBrijesh Singh #define GHCB_MSR_CPUID_REG_POS		30
43b81fc74dSBrijesh Singh #define GHCB_MSR_CPUID_REG_MASK		0x3
44b81fc74dSBrijesh Singh #define GHCB_CPUID_REQ_EAX		0
45b81fc74dSBrijesh Singh #define GHCB_CPUID_REQ_EBX		1
46b81fc74dSBrijesh Singh #define GHCB_CPUID_REQ_ECX		2
47b81fc74dSBrijesh Singh #define GHCB_CPUID_REQ_EDX		3
48b81fc74dSBrijesh Singh #define GHCB_CPUID_REQ(fn, reg)				\
49dbc4c70eSBorislav Petkov 	/* GHCBData[11:0] */				\
50b81fc74dSBrijesh Singh 	(GHCB_MSR_CPUID_REQ |				\
51dbc4c70eSBorislav Petkov 	/* GHCBData[31:12] */				\
52dbc4c70eSBorislav Petkov 	(((unsigned long)(reg) & 0x3) << 30) |		\
53dbc4c70eSBorislav Petkov 	/* GHCBData[63:32] */				\
54dbc4c70eSBorislav Petkov 	(((unsigned long)fn) << 32))
55b81fc74dSBrijesh Singh 
56310f134eSBrijesh Singh /* AP Reset Hold */
57310f134eSBrijesh Singh #define GHCB_MSR_AP_RESET_HOLD_REQ	0x006
58310f134eSBrijesh Singh #define GHCB_MSR_AP_RESET_HOLD_RESP	0x007
59310f134eSBrijesh Singh 
6087294bdbSBrijesh Singh /* GHCB GPA Register */
6187294bdbSBrijesh Singh #define GHCB_MSR_REG_GPA_REQ		0x012
6287294bdbSBrijesh Singh #define GHCB_MSR_REG_GPA_REQ_VAL(v)			\
6387294bdbSBrijesh Singh 	/* GHCBData[63:12] */				\
6487294bdbSBrijesh Singh 	(((u64)((v) & GENMASK_ULL(51, 0)) << 12) |	\
6587294bdbSBrijesh Singh 	/* GHCBData[11:0] */				\
6687294bdbSBrijesh Singh 	GHCB_MSR_REG_GPA_REQ)
6787294bdbSBrijesh Singh 
6887294bdbSBrijesh Singh #define GHCB_MSR_REG_GPA_RESP		0x013
6987294bdbSBrijesh Singh #define GHCB_MSR_REG_GPA_RESP_VAL(v)			\
7087294bdbSBrijesh Singh 	/* GHCBData[63:12] */				\
7187294bdbSBrijesh Singh 	(((u64)(v) & GENMASK_ULL(63, 12)) >> 12)
7287294bdbSBrijesh Singh 
734f9c403eSBrijesh Singh /*
744f9c403eSBrijesh Singh  * SNP Page State Change Operation
754f9c403eSBrijesh Singh  *
764f9c403eSBrijesh Singh  * GHCBData[55:52] - Page operation:
774f9c403eSBrijesh Singh  *   0x0001	Page assignment, Private
784f9c403eSBrijesh Singh  *   0x0002	Page assignment, Shared
794f9c403eSBrijesh Singh  */
804f9c403eSBrijesh Singh enum psc_op {
814f9c403eSBrijesh Singh 	SNP_PAGE_STATE_PRIVATE = 1,
824f9c403eSBrijesh Singh 	SNP_PAGE_STATE_SHARED,
834f9c403eSBrijesh Singh };
844f9c403eSBrijesh Singh 
854f9c403eSBrijesh Singh #define GHCB_MSR_PSC_REQ		0x014
864f9c403eSBrijesh Singh #define GHCB_MSR_PSC_REQ_GFN(gfn, op)			\
874f9c403eSBrijesh Singh 	/* GHCBData[55:52] */				\
884f9c403eSBrijesh Singh 	(((u64)((op) & 0xf) << 52) |			\
894f9c403eSBrijesh Singh 	/* GHCBData[51:12] */				\
904f9c403eSBrijesh Singh 	((u64)((gfn) & GENMASK_ULL(39, 0)) << 12) |	\
914f9c403eSBrijesh Singh 	/* GHCBData[11:0] */				\
924f9c403eSBrijesh Singh 	GHCB_MSR_PSC_REQ)
934f9c403eSBrijesh Singh 
944f9c403eSBrijesh Singh #define GHCB_MSR_PSC_RESP		0x015
954f9c403eSBrijesh Singh #define GHCB_MSR_PSC_RESP_VAL(val)			\
964f9c403eSBrijesh Singh 	/* GHCBData[63:32] */				\
974f9c403eSBrijesh Singh 	(((u64)(val) & GENMASK_ULL(63, 32)) >> 32)
984f9c403eSBrijesh Singh 
99310f134eSBrijesh Singh /* GHCB Hypervisor Feature Request/Response */
100310f134eSBrijesh Singh #define GHCB_MSR_HV_FT_REQ		0x080
101310f134eSBrijesh Singh #define GHCB_MSR_HV_FT_RESP		0x081
102cbd3d4f7SBrijesh Singh #define GHCB_MSR_HV_FT_RESP_VAL(v)			\
103cbd3d4f7SBrijesh Singh 	/* GHCBData[63:12] */				\
104cbd3d4f7SBrijesh Singh 	(((u64)(v) & GENMASK_ULL(63, 12)) >> 12)
105cbd3d4f7SBrijesh Singh 
106cbd3d4f7SBrijesh Singh #define GHCB_HV_FT_SNP			BIT_ULL(0)
1070afb6b66STom Lendacky #define GHCB_HV_FT_SNP_AP_CREATION	BIT_ULL(1)
108310f134eSBrijesh Singh 
109*69dcb1e3STom Lendacky /*
110*69dcb1e3STom Lendacky  * SNP Page State Change NAE event
111*69dcb1e3STom Lendacky  *   The VMGEXIT_PSC_MAX_ENTRY determines the size of the PSC structure, which
112*69dcb1e3STom Lendacky  *   is a local stack variable in set_pages_state(). Do not increase this value
113*69dcb1e3STom Lendacky  *   without evaluating the impact to stack usage.
114*69dcb1e3STom Lendacky  */
115*69dcb1e3STom Lendacky #define VMGEXIT_PSC_MAX_ENTRY		64
116dc3f3d24SBrijesh Singh 
117dc3f3d24SBrijesh Singh struct psc_hdr {
118dc3f3d24SBrijesh Singh 	u16 cur_entry;
119dc3f3d24SBrijesh Singh 	u16 end_entry;
120dc3f3d24SBrijesh Singh 	u32 reserved;
121dc3f3d24SBrijesh Singh } __packed;
122dc3f3d24SBrijesh Singh 
123dc3f3d24SBrijesh Singh struct psc_entry {
124dc3f3d24SBrijesh Singh 	u64	cur_page	: 12,
125dc3f3d24SBrijesh Singh 		gfn		: 40,
126dc3f3d24SBrijesh Singh 		operation	: 4,
127dc3f3d24SBrijesh Singh 		pagesize	: 1,
128dc3f3d24SBrijesh Singh 		reserved	: 7;
129dc3f3d24SBrijesh Singh } __packed;
130dc3f3d24SBrijesh Singh 
131dc3f3d24SBrijesh Singh struct snp_psc_desc {
132dc3f3d24SBrijesh Singh 	struct psc_hdr hdr;
133dc3f3d24SBrijesh Singh 	struct psc_entry entries[VMGEXIT_PSC_MAX_ENTRY];
134dc3f3d24SBrijesh Singh } __packed;
135dc3f3d24SBrijesh Singh 
136b81fc74dSBrijesh Singh #define GHCB_MSR_TERM_REQ		0x100
137b81fc74dSBrijesh Singh #define GHCB_MSR_TERM_REASON_SET_POS	12
138b81fc74dSBrijesh Singh #define GHCB_MSR_TERM_REASON_SET_MASK	0xf
139b81fc74dSBrijesh Singh #define GHCB_MSR_TERM_REASON_POS	16
140b81fc74dSBrijesh Singh #define GHCB_MSR_TERM_REASON_MASK	0xff
141b81fc74dSBrijesh Singh 
142b81fc74dSBrijesh Singh #define GHCB_SEV_TERM_REASON(reason_set, reason_val)	\
143dbc4c70eSBorislav Petkov 	/* GHCBData[15:12] */				\
144dbc4c70eSBorislav Petkov 	(((((u64)reason_set) &  0xf) << 12) |		\
145dbc4c70eSBorislav Petkov 	 /* GHCBData[23:16] */				\
146dbc4c70eSBorislav Petkov 	((((u64)reason_val) & 0xff) << 16))
147b81fc74dSBrijesh Singh 
1486c0f74d6SBrijesh Singh /* Error codes from reason set 0 */
1496c0f74d6SBrijesh Singh #define SEV_TERM_SET_GEN		0
15018c3933cSBrijesh Singh #define GHCB_SEV_ES_GEN_REQ		0
15118c3933cSBrijesh Singh #define GHCB_SEV_ES_PROT_UNSUPPORTED	1
152cbd3d4f7SBrijesh Singh #define GHCB_SNP_UNSUPPORTED		2
153b81fc74dSBrijesh Singh 
1546c0f74d6SBrijesh Singh /* Linux-specific reason codes (used with reason set 1) */
1556c0f74d6SBrijesh Singh #define SEV_TERM_SET_LINUX		1
1566c0f74d6SBrijesh Singh #define GHCB_TERM_REGISTER		0	/* GHCB GPA registration failure */
1576c0f74d6SBrijesh Singh #define GHCB_TERM_PSC			1	/* Page State Change failure */
1586c0f74d6SBrijesh Singh #define GHCB_TERM_PVALIDATE		2	/* Pvalidate failure */
15981cc3df9SBrijesh Singh #define GHCB_TERM_NOT_VMPL0		3	/* SNP guest is not running at VMPL-0 */
160ee0bfa08SMichael Roth #define GHCB_TERM_CPUID			4	/* CPUID-validation failure */
161ee0bfa08SMichael Roth #define GHCB_TERM_CPUID_HV		5	/* CPUID failure during hypervisor fallback */
1626c0f74d6SBrijesh Singh 
163b81fc74dSBrijesh Singh #define GHCB_RESP_CODE(v)		((v) & GHCB_MSR_INFO_MASK)
164b81fc74dSBrijesh Singh 
165ad5b3532STom Lendacky /*
166ad5b3532STom Lendacky  * Error codes related to GHCB input that can be communicated back to the guest
167ad5b3532STom Lendacky  * by setting the lower 32-bits of the GHCB SW_EXITINFO1 field to 2.
168ad5b3532STom Lendacky  */
169ad5b3532STom Lendacky #define GHCB_ERR_NOT_REGISTERED		1
170ad5b3532STom Lendacky #define GHCB_ERR_INVALID_USAGE		2
171ad5b3532STom Lendacky #define GHCB_ERR_INVALID_SCRATCH_AREA	3
172ad5b3532STom Lendacky #define GHCB_ERR_MISSING_INPUT		4
173ad5b3532STom Lendacky #define GHCB_ERR_INVALID_INPUT		5
174ad5b3532STom Lendacky #define GHCB_ERR_INVALID_EVENT		6
175ad5b3532STom Lendacky 
176b81fc74dSBrijesh Singh #endif
177