| /openbmc/linux/include/sound/ |
| H A D | asoundef.h | 19 #define IEC958_AES0_PRO_EMPHASIS (7<<2) /* mask - emphasis */
20 #define IEC958_AES0_PRO_EMPHASIS_NOTID (0<<2) /* emphasis not indicated */
21 #define IEC958_AES0_PRO_EMPHASIS_NONE (1<<2) /* none emphasis */
22 #define IEC958_AES0_PRO_EMPHASIS_5015 (3<<2) /* 50/15us emphasis */
23 #define IEC958_AES0_PRO_EMPHASIS_CCITT (7<<2) /* CCITT J.17 emphasis */
27 #define IEC958_AES0_PRO_FS_44100 (1<<6) /* 44.1kHz */
28 #define IEC958_AES0_PRO_FS_48000 (2<<6) /* 48kHz */
29 #define IEC958_AES0_PRO_FS_32000 (3<<6) /* 32kHz */
30 #define IEC958_AES0_CON_NOT_COPYRIGHT (1<<2) /* 0 = copyright, 1 = not copyright */
37 #define IEC958_AES1_PRO_MODE_STEREOPHONIC (2<<0) /* stereophonic - ch A is left */
[all …]
|
| H A D | emu10k1.h | 209 #define HCFG_BAUD_RATE 0x00080000 /* 0 = 48kHz, 1 = 44.1kHz */
210 #define HCFG_EXPANDED_MEM 0x00040000 /* 1 = any 16M of 4G addr, 0 = 32M of 2G addr */
285 #define A_GPINPUT_MASK 0xff00 /* Alice/2 has 8 input pins */
286 #define A3_GPINPUT_MASK 0x3f00 /* ... while Tina/2 has only 6 */
323 /* Available on the Audigy 2 and Audigy 4 only. This is the P16V chip. */
339 #define INTE2_PLAYBACK_CH_2_LOOP 0x00004000 /* Playback Channel 2 loop …
340 #define INTE2_PLAYBACK_CH_2_HALF_LOOP 0x00000400 /* Playback Channel 2 half loop …
346 /* 0x00000000 2-channel output. */
352 * bit 2: Lock P16V playback memory cache.
356 * bit 11-12: Playback mixer attenuation: 0=0dB, 1=-6dB, 2=-12dB, 3=Mute.
[all …]
|
| H A D | designware_i2s.h | 16 * @sample_rate: sampling frequency (8Khz, 16Khz, 32Khz, 44Khz, 48Khz)
29 #define DW_I2S_SLAVE (1 << 2)
38 #define DW_I2S_QUIRK_16BIT_IDX_OVERRIDE (1 << 2)
62 #define TWO_CHANNEL_SUPPORT 2 /* up to 2.0 */
|
| /openbmc/linux/Documentation/fb/ |
| H A D | viafb.modes | 14 # Scan Frequency 31.469 kHz 59.94 Hz
16 # 12 chars 2 lines
18 # 2 chars 10 lines
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
39 # Scan Frequency 37.500 kHz 75.00 Hz
43 # 2 chars 1 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
60 # Scan Frequency 43.269 kHz 85.00 Hz
[all …]
|
| /openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | cru_rk3399.h | 24 u32 pmucru_clkfrac_con[2];
28 u32 pmucru_softrst_con[2];
29 u32 reserved4[2];
30 u32 pmucru_rstnhold_con[2];
31 u32 reserved5[2];
32 u32 pmucru_gatedis_con[2];
38 u32 reserved[2];
40 u32 reserved1[2];
42 u32 reserved2[2];
44 u32 reserved3[2];
[all …]
|
| H A D | cru_rk3328.h | 27 u32 reserved5[2];
41 u32 sdmmc_con[2];
42 u32 sdio_con[2];
43 u32 emmc_con[2];
44 u32 sdmmc_ext_con[2];
48 #define KHz 1000 macro
58 #define PERIHP_ACLK_HZ (144000 * KHz)
59 #define PERIHP_HCLK_HZ (72000 * KHz)
60 #define PERIHP_PCLK_HZ (72000 * KHz)
|
| /openbmc/linux/tools/testing/selftests/alsa/ |
| H A D | pcm-test.conf | 2 description "8kHz mono large periods"
11 description "8kHz stereo large periods"
15 channels 2
20 description "44.1kHz stereo large periods"
24 channels 2
29 description "48kHz stereo small periods"
33 channels 2
38 description "48kHz stereo large periods"
42 channels 2
47 description "48kHz 6 channel large periods"
[all …]
|
| /openbmc/linux/sound/ppc/ |
| H A D | awacs.h | 60 #define MASK_ADDR2 (0x2 << 12) /* Expanded Data Mode Address 2 */
94 #define MASK_RECALIBRATE (0x1 << 2) /* Recalibrate */
112 #define SAMPLERATE_48000 (0x0 << 3) /* 48 or 44.1 kHz */
113 #define SAMPLERATE_32000 (0x1 << 3) /* 32 or 29.4 kHz */
114 #define SAMPLERATE_24000 (0x2 << 3) /* 24 or 22.05 kHz */
115 #define SAMPLERATE_19200 (0x3 << 3) /* 19.2 or 17.64 kHz */
116 #define SAMPLERATE_16000 (0x4 << 3) /* 16 or 14.7 kHz */
117 #define SAMPLERATE_12000 (0x5 << 3) /* 12 or 11.025 kHz */
118 #define SAMPLERATE_9600 (0x6 << 3) /* 9.6 or 8.82 kHz */
119 #define SAMPLERATE_8000 (0x7 << 3) /* 8 or 7.35 kHz */
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/display/include/ |
| H A D | grph_object_ctrl_defs.h | 45 PANEL_8BIT_COLOR = 2,
122 uint32_t GREY_LEVEL:2;
128 uint32_t pixel_clk; /* in KHz */
160 uint32_t crystal_frequency; /* in KHz */
161 uint32_t min_input_pxl_clk_pll_frequency; /* in KHz */
162 uint32_t max_input_pxl_clk_pll_frequency; /* in KHz */
163 uint32_t min_output_pxl_clk_pll_frequency; /* in KHz */
164 uint32_t max_output_pxl_clk_pll_frequency; /* in KHz */
172 uint32_t default_display_engine_pll_frequency; /* in KHz */
173 uint32_t external_clock_source_frequency_for_dp; /* in KHz */
[all …]
|
| /openbmc/linux/sound/firewire/dice/ |
| H A D | dice-weiss.c | 13 // Weiss DAC202: 192kHz 2-channel DAC
15 .tx_pcm_chs = {{2, 2, 2}, {0, 0, 0} },
16 .rx_pcm_chs = {{2, 2, 2}, {0, 0, 0} },
19 // Weiss MAN301: 192kHz 2-channel music archive network player
21 .tx_pcm_chs = {{2, 2, 2}, {0, 0, 0} },
22 .rx_pcm_chs = {{2, 2, 2}, {0, 0, 0} },
25 // Weiss INT202: 192kHz unidirectional 2-channel digital Firewire nterface
27 .tx_pcm_chs = {{2, 2, 2}, {0, 0, 0} },
28 .rx_pcm_chs = {{2, 2, 2}, {0, 0, 0} },
31 // Weiss INT203: 192kHz bidirectional 2-channel digital Firewire nterface
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/sound/ |
| H A D | ti,j721e-cpb-ivi-audio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
23 In order to support 48KHz and 44.1KHz family of sampling rates the parent clock
24 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
25 44.1KHz). The same PLLs are used for McASP0's AUXCLK clock via different
30 Clocking setup for 48KHz family:
37 Clocking setup for 44.1KHz family:
76 - description: Parent for CPB_McASP auxclk (for 48KHz)
77 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
79 - description: Parent for CPB_SCKI clock (for 48KHz)
80 - description: Parent for CPB_SCKI clock (for 44.1KHz)
[all …]
|
| H A D | ti,j721e-cpb-audio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
18 In order to support 48KHz and 44.1KHz family of sampling rates the parent
19 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
20 PLL15 (for 44.1KHz). The same PLLs are used for McASP10's AUXCLK clock via
24 48KHz family:
28 44.1KHz family:
33 48KHz family:
85 - description: Parent for CPB_McASP auxclk (for 48KHz)
86 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
88 - description: Parent for CPB_SCKI clock (for 48KHz)
[all …]
|
| /openbmc/linux/drivers/video/fbdev/core/ |
| H A D | modedb.c | 38 /* 640x400 @ 70 Hz, 31.5 kHz hsync */
39 { NULL, 70, 640, 400, 39721, 40, 24, 39, 9, 96, 2, 0,
42 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
43 { NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2, 0,
46 /* 800x600 @ 56 Hz, 35.15 kHz hsync */
47 { NULL, 56, 800, 600, 27777, 128, 24, 22, 1, 72, 2, 0,
50 /* 1024x768 @ 87 Hz interlaced, 35.5 kHz hsync */
54 /* 640x400 @ 85 Hz, 37.86 kHz hsync */
58 /* 640x480 @ 72 Hz, 36.5 kHz hsync */
62 /* 640x480 @ 75 Hz, 37.50 kHz hsync */
[all …]
|
| /openbmc/linux/Documentation/sound/cards/ |
| H A D | audiophile-usb.rst | 31 The device has 4 audio interfaces, and 2 MIDI ports:
35 - This port supports 2 pairs of line-level audio inputs (1/4" TS and RCA)
48 * sample rate from 8kHz to 96kHz
57 * 16-bit/48kHz ==> 4 channels in + 4 channels out
61 * 24-bit/48kHz ==> 4 channels in + 2 channels out,
62 or 2 channels in + 4 channels out
66 * 24-bit/96kHz ==> 2 channels in _or_ 2 channels out (half duplex only)
129 * hw:1,2 is Do in AC3/DTS passthrough mode
135 One exception is the hw:1,2 port which was reported to be Little Endian
137 This has been fixed in kernel 2.6.23 and above and now the hw:1,2 interface
[all …]
|
| /openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/fbset/fbset-modes/om-gta01/ |
| H A D | fb.modes | 4 # D: 26.000 MHz, H: 43.334 kHz, V: 65.657 Hz
6 timings 38461 104 8 2 16 8 2
11 # D: 26.000 MHz, H: 43.334 kHz, V: 65.657 Hz
13 timings 38461 104 8 2 16 8 2
18 # D: 8.475 MHz, H: 24.635 kHz, V: 75.569 Hz
20 timings 118000 88 8 2 2 8 2
25 # D: 8.475 MHz, H: 24.635 kHz, V: 75.569 Hz
27 timings 118000 88 8 2 2 8 2
|
| /openbmc/linux/sound/pci/ca0106/ |
| H A D | ca0106.h | 34 * playback periods_min=2, periods_max=8
120 #define HCFG_PLAYBACK_ATTENUATION 0x00006000 /* Playback attenuation mask. 0 = 0dB, 1 = 6dB, 2 = 12…
124 #define HCFG_8_CHANNEL_PLAY 0x00000200 /* 1 = 8 channels, 0 = 2 channels per substream.*/
125 #define HCFG_8_CHANNEL_CAPTURE 0x00000100 /* 1 = 8 channels, 0 = 2 channels per substream.*/
137 /* Here pins 0,1,2,3,4,,6 are output. 5,7 are input */
144 * bit 12 0 = 48 Khz / 1 = 96 Khz Analog out on SB Live 24bit.
203 * Playback rate [23:16] (2 bits per channel) (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
208 * The jack has 4 poles. I will call 1 - Tip, 2 - Next to 1, 3 - Next to 2, 4 - Next to 3
209 * For Analogue: 1 -> Center Speaker, 2 -> Sub Woofer, 3 -> Ground, 4 -> Ground
210 * For Digital: 1 -> Front SPDIF, 2 -> Rear SPDIF, 3 -> Center/Subwoofer SPDIF, 4 -> Ground.
[all …]
|
| /openbmc/linux/drivers/media/dvb-frontends/ |
| H A D | mxl5xx_defs.h | 35 MXL_HYDRA_DEV_SET_OVERWRITE_DEF_CMD = 2,
128 #define MXL_HYDRA_I2C_HDR_SIZE (2 * sizeof(u8)) /* PLID + LEN(0xFF) */
133 #define MXL_HYDRA_SKU_ID_585 2
142 #define MXL_HYDRA_REG_WRITE_LEN (MXL_HYDRA_I2C_HDR_SIZE + (2 * MXL_HYDRA_REG_SIZE_IN_BYTES))
191 cmd_buff[2] = size; \
396 MXL_HYDRA_STEP_SIZE_24_XTAL_102_05KHZ, /* 102.05 KHz for 24 MHz XTAL */
397 MXL_HYDRA_STEP_SIZE_24_XTAL_204_10KHZ, /* 204.10 KHz for 24 MHz XTAL */
398 MXL_HYDRA_STEP_SIZE_24_XTAL_306_15KHZ, /* 306.15 KHz for 24 MHz XTAL */
399 MXL_HYDRA_STEP_SIZE_24_XTAL_408_20KHZ, /* 408.20 KHz for 24 MHz XTAL */
401 MXL_HYDRA_STEP_SIZE_27_XTAL_102_05KHZ, /* 102.05 KHz for 27 MHz XTAL */
[all …]
|
| /openbmc/linux/include/linux/ |
| H A D | clocksource.h | 150 * mult/2^shift = ns/cyc in clocksource_freq2mult()
151 * mult = ns/cyc * 2^shift in clocksource_freq2mult()
152 * mult = from/freq * 2^shift in clocksource_freq2mult()
153 * mult = from * 2^shift / freq in clocksource_freq2mult()
158 tmp += freq/2; /* round for do_div */ in clocksource_freq2mult()
165 * clocksource_khz2mult - calculates mult from khz and shift
166 * @khz: Clocksource frequency in KHz
169 * Helper functions that converts a khz counter frequency to a timsource
172 static inline u32 clocksource_khz2mult(u32 khz, u32 shift_constant) in clocksource_khz2mult() argument
174 return clocksource_freq2mult(khz, shift_constant, NSEC_PER_MSEC); in clocksource_khz2mult()
[all …]
|
| /openbmc/linux/drivers/gpu/drm/radeon/ |
| H A D | atombios.h | 60 #define ATOM_EXT_DAC 2
64 #define ATOM_CRTC3 2
75 #define ATOM_DCPLL 2
76 #define ATOM_PPLL0 2
86 #define ENCODER_REFCLK_SRC_DCPLL 2
95 #define ATOM_SCALER_EXPANSION 2
100 #define ATOM_LCD_BLOFF (ATOM_DISABLE+2)
101 #define ATOM_LCD_BLON (ATOM_ENABLE+2)
122 #define ATOM_TV_NTSCJ 2
132 #define ATOM_DAC1_CV 2
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/include/ |
| H A D | atombios.h | 59 #define ATOM_EXT_DAC 2
63 #define ATOM_CRTC3 2
78 #define ATOM_DCPLL 2
79 #define ATOM_PPLL0 2
103 #define ENCODER_REFCLK_SRC_DCPLL 2
109 #define ATOM_SCALER_EXPANSION 2 //For Fudo, it's 2 Tap alpha blending mode
114 #define ATOM_LCD_BLOFF (ATOM_DISABLE+2)
115 #define ATOM_LCD_BLON (ATOM_ENABLE+2)
131 #define ATOM_TV_NTSCJ 2
141 #define ATOM_DAC1_CV 2
[all …]
|
| /openbmc/linux/drivers/cpufreq/ |
| H A D | powernow-k6.c | 26 static unsigned int busfreq; /* FSB, in 10 kHz */
36 MODULE_PARM_DESC(bus_frequency, "Bus frequency in kHz");
51 static const u8 index_to_register[8] = { 6, 3, 1, 0, 2, 7, 5, 4 };
52 static const u8 register_to_index[8] = { 3, 2, 4, 1, 7, 6, 0, 5 };
157 unsigned khz; in powernow_k6_cpu_init() local
163 khz = cpu_khz; in powernow_k6_cpu_init()
165 if (khz >= usual_frequency_table[i].freq - FREQ_RANGE && in powernow_k6_cpu_init()
166 khz <= usual_frequency_table[i].freq + FREQ_RANGE) { in powernow_k6_cpu_init()
167 khz = usual_frequency_table[i].freq; in powernow_k6_cpu_init()
184 khz); in powernow_k6_cpu_init()
[all …]
|
| /openbmc/u-boot/drivers/i2c/ |
| H A D | aspeed_i2c_global.c | 28 * div : scl : baseclk [APB/((div/2) + 1)] : tBuf [1/bclk * 16]
30 * I2CG10[23:16] base clk3 for Standard-mode (100Khz) min tBuf 4.7us
31 * 0x3c : 100.8Khz : 3.225Mhz : 4.96us
32 * 0x3d : 99.2Khz : 3.174Mhz : 5.04us
33 * 0x3e : 97.65Khz : 3.125Mhz : 5.12us
34 * 0x40 : 97.75Khz : 3.03Mhz : 5.28us
35 * 0x41 : 99.5Khz : 2.98Mhz : 5.36us (default)
36 * I2CG10[15:8] base clk2 for Fast-mode (400Khz) min tBuf 1.3us
37 * 0x12 : 400Khz : 10Mhz : 1.6us
|
| /openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| H A D | gt215.c | 100 sdiv = ((sctl & 0x003f0000) >> 16) + 2; in read_clk()
101 return (sclk * 2) / sdiv; in read_clk()
171 case 2: in gt215_clk_read()
187 gt215_clk_info(struct nvkm_clk *base, int idx, u32 khz, in gt215_clk_info() argument
196 switch (khz) { in gt215_clk_info()
199 return khz; in gt215_clk_info()
202 return khz; in gt215_clk_info()
205 return khz; in gt215_clk_info()
208 sdiv = min((sclk * 2) / khz, (u32)65); in gt215_clk_info()
209 oclk = (sclk * 2) / sdiv; in gt215_clk_info()
[all …]
|
| /openbmc/linux/drivers/media/tuners/ |
| H A D | tda9887.c | 276 "- 12.5 kHz", in dump_read_message()
277 "- 37.5 kHz", in dump_read_message()
278 "- 62.5 kHz", in dump_read_message()
279 "- 87.5 kHz", in dump_read_message()
280 "-112.5 kHz", in dump_read_message()
281 "-137.5 kHz", in dump_read_message()
282 "-162.5 kHz", in dump_read_message()
283 "-187.5 kHz [min]", in dump_read_message()
284 "+187.5 kHz [max]", in dump_read_message()
285 "+162.5 kHz", in dump_read_message()
[all …]
|
| /openbmc/linux/Documentation/hwmon/ |
| H A D | lm85.rst | 92 The LM85 uses the 2-wire interface compatible with the SMBUS 2.0
108 transistor like the 2N3904.
133 for 3-wire and 2-wire mode. For this reason, the 2-wire fan modes are not
153 driven by a 22.5 kHz clock. This is a global mode, not per-PWM output,
154 which means that setting any PWM frequency above 11.3 kHz will switch
155 all 3 PWM outputs to a 22.5 kHz frequency. Conversely, setting any PWM
156 frequency below 11.3 kHz will switch all 3 PWM outputs to a frequency
179 The LM96000 supports additional high frequency PWM modes (22.5 kHz, 24 kHz,
180 25.7 kHz, 27.7 kHz and 30 kHz), which can be configured on a per-PWM basis.
213 sensors and therefore three zones (# 1, 2 and 3). Each zone has the following
[all …]
|