| /openbmc/linux/Documentation/devicetree/bindings/phy/ |
| H A D | apm-xgene-phy.txt | 1 * APM X-Gene 15Gbps Multi-purpose PHY nodes
3 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
11 1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI).
27 - apm,tx-boost-gain : Frequency boost AC (LSB 3-bit) and DC (2-bit)
39 - apm,tx-pre-cursor2 : 2st pre-cursor emphasis taps control. Two set of
48 0 = 1-2Gbps
49 1 = 2-4Gbps (1st tuple default)
50 2 = 4-8Gbps
51 3 = 8-15Gbps (2nd tuple default)
52 4 = 2.5-4Gbps
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| H A D | microchip,sparx5-serdes.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
35 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
36 * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
37 * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
45 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
46 * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
47 * 5 Gbps (QSGMII/USGMII)
48 * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
49 * 10 Gbps (10G-USGMII)
50 * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)
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| H A D | mediatek,hdmi-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
56 TX DRV bias current for < 1.65Gbps
64 TX DRV bias current for >= 1.65Gbps
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| /openbmc/linux/drivers/scsi/mvsas/ |
| H A D | mv_94xx.h | 122 VSR_PHY_MODE10 = 0x0A * 4, /* Event Counter 2 */
143 MVS_IRQ_COM_IN_I2O_IOP2 = (1 << 2),
180 * bit 2: 6Gbps support
181 * bit 1: 3Gbps support
182 * bit 0: 1.5Gbps support
188 * bit 5: G1 (1.5Gbps) Without SSC
189 * bit 4: G1 (1.5Gbps) with SSC
190 * bit 3: G2 (3.0Gbps) Without SSC
191 * bit 2: G2 (3.0Gbps) with SSC
192 * bit 1: G3 (6.0Gbps) without SSC
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| /openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| H A D | README.soc | 4 2. LS1088A
35 - Up to 2 x SGMII supporting 2500Mbps
36 - Up to 2 x RGMII supporting 1000Mbps
63 - Cores are in 2 cluster of 4-cores each
72 - 3 PCIe3.0 , 1 SATA3.0, 2 USB3.0, 1 SDXC, 2 DUARTs etc
73 - 2 DUARTs
101 - Cryptography acceleration (SEC) at up to 10 Gbps
102 - RegEx pattern matching acceleration (PME) at up to 10 Gbps
103 - Decompression/compression acceleration (DCE) at up to 20 Gbps
104 - Accelerated I/O processing (AIOP) at up to 20 Gbps
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| /openbmc/linux/Documentation/scsi/ |
| H A D | bfa.rst | 16 1657:0013:1657:0014 425 4Gbps dual port FC HBA
17 1657:0013:1657:0014 825 8Gbps PCIe dual port FC HBA
18 1657:0013:103c:1742 HP 82B 8Gbps PCIedual port FC HBA
19 1657:0013:103c:1744 HP 42B 4Gbps dual port FC HBA
20 1657:0017:1657:0014 415 4Gbps single port FC HBA
21 1657:0017:1657:0014 815 8Gbps single port FC HBA
22 1657:0017:103c:1741 HP 41B 4Gbps single port FC HBA
23 1657:0017:103c 1743 HP 81B 8Gbps single port FC HBA
24 1657:0021:103c:1779 804 8Gbps FC HBA for HP Bladesystem c-class
26 1657:0014:1657:0014 1010 10Gbps single port CNA - FCOE
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| /openbmc/linux/Documentation/devicetree/bindings/media/i2c/ |
| H A D | maxim,max96712.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 title: Quad GMSL2 to CSI-2 Deserializer with GMSL1 Compatibility
15 CSI-2 D-PHY or C-PHY formatted outputs. The device allows each link to
21 Each GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
23 MAX96712 can be paired with first-generation 3.12Gbps or 1.5Gbps GMSL1
24 serializers or operate up to 3.12Gbps with GMSL2 serializers in GMSL1 mode.
48 port@2:
50 description: GMSL Input 2
59 description: CSI-2 Output
112 data-lanes = <1 2 3 4>;
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| /openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
| H A D | smu11_driver_if_arcturus.h | 37 #define NUM_MP0CLK_DPM_LEVELS 2
41 #define NUM_XGMI_LEVELS 2
58 #define FEATURE_DPM_UCLK_BIT 2
189 #define THROTTLER_TEMP_HOTSPOT_BIT 2
214 #define WORKLOAD_PPLIB_VIDEO_BIT 2
265 uint8_t Padding[2];
429 XGMI_LINK_RATE_2 = 2, // 2Gbps
430 XGMI_LINK_RATE_4 = 4, // 4Gbps
431 XGMI_LINK_RATE_8 = 8, // 8Gbps
432 XGMI_LINK_RATE_12 = 12, // 12Gbps
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| H A D | smu11_driver_if_sienna_cichlid.h | 35 #define NUM_SMNCLK_DPM_LEVELS 2
37 #define NUM_MP0CLK_DPM_LEVELS 2
46 #define NUM_MP1CLK_DPM_LEVELS 2
47 #define NUM_LINK_LEVELS 2
49 #define NUM_XGMI_LEVELS 2
72 #define PPSMC_GeminiModeSlave 2 //Slave GPU on a Gemini board
78 #define FEATURE_DPM_GFX_GPO_BIT 2
197 #define THROTTLER_TEMP_HOTSPOT_BIT 2
221 #define FW_DSTATE_G6_PHY_VDDCI_OFF_BIT 2
264 #define LED_DISPLAY_ERROR_BIT 2
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| /openbmc/linux/drivers/scsi/bfa/ |
| H A D | bfad_attr.c | 193 fc_host_active_fc4s(shost)[2] = 1; in bfad_im_get_host_active_fc4s()
414 fc_host_supported_fc4s(vshost)[2] = 1; in bfad_im_vport_create()
747 "QLogic BR-series 4Gbps PCIe dual port FC HBA"); in bfad_im_model_desc_show()
750 "QLogic BR-series 8Gbps PCIe dual port FC HBA"); in bfad_im_model_desc_show()
753 "QLogic BR-series 4Gbps PCIe dual port FC HBA for HP"); in bfad_im_model_desc_show()
756 "QLogic BR-series 8Gbps PCIe dual port FC HBA for HP"); in bfad_im_model_desc_show()
759 "QLogic BR-series 10Gbps single port CNA"); in bfad_im_model_desc_show()
762 "QLogic BR-series 10Gbps dual port CNA"); in bfad_im_model_desc_show()
765 "QLogic BR-series 10Gbps CNA for IBM Blade Center"); in bfad_im_model_desc_show()
768 "QLogic BR-series 4Gbps PCIe single port FC HBA"); in bfad_im_model_desc_show()
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| /openbmc/linux/drivers/scsi/be2iscsi/ |
| H A D | Kconfig | 3 tristate "Emulex 10Gbps iSCSI - BladeEngine 2"
11 10Gbps Storage adapter - BladeEngine 2.
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| /openbmc/linux/drivers/net/ethernet/ezchip/ |
| H A D | nps_enet.h | 59 /* Gbps Eth MAC Configuration 0 register masks and shifts */
65 #define CFG_0_TX_FC_EN_SHIFT 2
93 /* Gbps Eth MAC Configuration 1 register masks and shifts */
103 /* Gbps Eth MAC Configuration 2 register masks and shifts */
119 /* Gbps Eth MAC Configuration 3 register masks and shifts */
125 #define CFG_3_RX_CBFC_REDIR_EN_SHIFT 2
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| /openbmc/u-boot/board/freescale/t208xqds/ |
| H A D | README | 13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
19 - Up to four 10 Gbps Ethernet MACs
20 - Up to eight 1 Gbps Ethernet MACs
21 - Up to four 2.5 Gbps Ethernet MACs
31 - Four 2-pin UARTs or two 4-pin UARTs
41 10G Ethernet numbers: 4 2
43 Serial RapidIO,RMan: 2 no
44 SATA Controller: 2 no
57 - Two 1Gbps RGMII on-board ports
58 - Four 10Gbps XFI on-board cages
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| /openbmc/u-boot/drivers/video/meson/ |
| H A D | meson_dw_hdmi.c | 50 HDMI_COMPATIBLE_GXM = 2,
208 mdelay(2); in meson_dw_hdmi_phy_reset()
213 mdelay(2); in meson_dw_hdmi_phy_reset()
224 /* 5.94Gbps, 3.7125Gbps */ in meson_dw_hdmi_phy_setup_mode()
228 /* 2.97Gbps */ in meson_dw_hdmi_phy_setup_mode()
232 /* 1.485Gbps */ in meson_dw_hdmi_phy_setup_mode()
242 /* 5.94Gbps, 3.7125Gbps */ in meson_dw_hdmi_phy_setup_mode()
246 /* 2.97Gbps */ in meson_dw_hdmi_phy_setup_mode()
250 /* 1.485Gbps, and below */ in meson_dw_hdmi_phy_setup_mode()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_dp_types.h | 35 LANE_COUNT_TWO = 2,
50 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane
51 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane
52 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane
53 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane
54 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2) - 3.24 Gbps/Lane
55 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane
56 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2) - 5.40 Gbps/Lane
57 LINK_RATE_RATE_8 = 0x19, // Rate_8 - 6.75 Gbps/Lane
58 LINK_RATE_HIGH3 = 0x1E, // Rate_9 (HBR3) - 8.10 Gbps/Lane
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| /openbmc/linux/drivers/gpu/drm/meson/ |
| H A D | meson_dw_hdmi.c | 87 * - PHY, Clock and Mode setup for 2k && 4k modes
121 MESON_VENC_SOURCE_ENCP = 2,
185 return readl(dw_hdmi->hdmitx + HDMITX_TOP_G12A_OFFSET + (addr << 2)); in dw_hdmi_g12a_top_read()
208 writel(data, dw_hdmi->hdmitx + HDMITX_TOP_G12A_OFFSET + (addr << 2)); in dw_hdmi_g12a_top_write()
300 if (mode_is_420) pixel_clock /= 2; in meson_hdmi_phy_setup_mode()
305 /* 5.94Gbps, 3.7125Gbps */ in meson_hdmi_phy_setup_mode()
309 /* 2.97Gbps */ in meson_hdmi_phy_setup_mode()
313 /* 1.485Gbps */ in meson_hdmi_phy_setup_mode()
324 /* 5.94Gbps, 3.7125Gbps */ in meson_hdmi_phy_setup_mode()
328 /* 2.97Gbps */ in meson_hdmi_phy_setup_mode()
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| /openbmc/linux/tools/testing/selftests/drivers/net/mlxsw/ |
| H A D | qos_lib.sh | 29 # 1Gbps. That wouldn't saturate egress and MC would thus get through,
30 # seemingly winning bandwidth on account of UC. Demand at least 2Gbps
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| H A D | sch_red_core.sh | 3 # This test sends a >1Gbps stream of traffic from H1, to the switch, which
4 # forwards it to a 1Gbps port. This 1Gbps stream is then looped back to the
5 # switch and forwarded to the port under test $swp3, which is also 1Gbps.
35 # | >1Gbps |
60 # | | | 1Gbps
83 echo 192.0.2.$((16 * (vlan - 10) + host))
123 host_create $h2 2
138 # 1Gbps.
289 ping_test $h2.10 $(ipaddr 3 10) " from host 2, vlan 10"
290 ping_test $h2.11 $(ipaddr 3 11) " from host 2, vlan 11"
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| /openbmc/u-boot/board/freescale/t208xrdb/ |
| H A D | README | 13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
19 - Up to four 10 Gbps Ethernet MACs
20 - Up to eight 1 Gbps Ethernet MACs
21 - Up to four 2.5 Gbps Ethernet MACs
31 - Four 2-pin UARTs or two 4-pin UARTs
41 10G Ethernet numbers: 4 2
43 Serial RapidIO,RMan: 2 no
44 SATA Controller: 2 no
55 - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
56 - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2)
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| /openbmc/u-boot/cmd/aspeed/ |
| H A D | dptest.h | 145 #define F_EMPHASIS_NULL 0x00000001 // No emphasis : 2
146 #define F_EMPHASIS 0x00000002 // Emphasis : 1-0-2
147 #define F_EMPHASIS_1 0x00000004 // Emphasis 1 : 2-0-1
158 #define PRINT_RATE_1_62 printf("DP Rate 1.62 Gbps !\n")
159 #define PRINT_RATE_2_70 printf("DP Rate 2.70 Gbps !\n")
160 #define PRINT_RATE_5_40 printf("DP Rate 5.40 Gbps !\n")
164 #define PRINT_SWING_2 printf("DP Swing Level 2!\n")
168 #define PRINT_DEEMP_2 printf("DP Pre - Emphasis Level 2!\n")
172 #define PRINT_EMPVAL_2 printf("DP Pre - Emphasis Level 2 !\n")
195 #define PRINT_ITEM_G printf("3.12 Total Jitter Test with No Cable Model -D10.2\n");\
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| /openbmc/u-boot/arch/arm/mach-mvebu/serdes/axp/ |
| H A D | high_speed_env_spec.h | 28 PEX_BUS_MODE_X4 = 2,
59 * SGMII 1.25 Gbps 3.125 Gbps
69 {0, 1, -1 , -1, -1, -1, -1, -1, 2}, /* Lane 1 */ \
70 {0, 1, -1 , 2, -1, -1, -1, -1, 3}, /* Lane 2 */ \
71 {0, 1, -1 , -1, 2, -1, -1, 3, -1}, /* Lane 3 */ \
72 {0, 1, 2 , -1, -1, 3, -1, -1, 4}, /* Lane 4 */ \
73 {0, 1, 2 , -1, 3, -1, -1, 4, -1}, /* Lane 5 */ \
74 {0, 1, 2 , 4, -1, 3, -1, -1, -1}, /* Lane 6 */ \
75 {0, 1, -1 , 2, -1, -1, 3, -1, 4}, /* Lane 7*/ \
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| /openbmc/linux/arch/arm64/boot/dts/marvell/ |
| H A D | armada-8040-puzzle-m801.dts | 81 mod-def0-gpios = <&sfpplus_gpio 2 GPIO_ACTIVE_LOW>;
94 /* SFP+ port 2: Activity */
107 led-2 {
108 /* SFP+ port 2: 10 Gbps indicator */
110 function-enumerator = <2>;
115 /* SFP+ port 2: 1 Gbps indicator */
122 /* SFP+ port 1: 10 Gbps indicator */
129 /* SFP+ port 1: 1 Gbps indicator */
245 #cooling-cells = <2>;
251 #cooling-cells = <2>;
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| /openbmc/u-boot/board/freescale/t102xqds/ |
| H A D | README | 23 - 150 Gbps coherent read bandwidth
33 - Four 1 Gbps Ethernet controllers
79 - PCI Express: supports Gen 1 and Gen 2
92 - NAND Flash: 8-bit, async, up to 2GB
102 - Four SGMII interface supporting 1Gbps
103 - Three SGMII interfaces supporting 2.5Gbps
104 - one 10Gbps XFI or 10Base-KR interface
159 0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
167 0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
231 2. NAND Boot:
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| /openbmc/linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/ |
| H A D | hclge_main.h | 26 #define HCLGE_RD_FIRST_STATS_NUM 2
87 #define HCLGE_RSS_TC_SIZE_1 2
136 #define HCLGE_PF_ID_M GENMASK(2, 0)
150 #define HCLGE_IMP_RESET_BIT 2
181 (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN)
187 #define HCLGE_SUPPORT_25G_BIT BIT(2)
235 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */
236 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */
237 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */
238 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */
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| /openbmc/linux/include/rdma/ |
| H A D | opa_port_info.h | 16 #define OPA_PORT_PACKET_FORMAT_9B 2 /* Format 9B */
22 #define OPA_PORT_LTP_CRC_MODE_16 2 /* 16-bit LTP CRC mode */
29 #define OPA_LINKDOWN_REASON_BAD_PKT_LEN 2
90 #define OPA_LINKINIT_REASON_FLAPPING (2 << 4)
96 #define OPA_LINK_SPEED_NOP 0x0000 /* Reserved (1-5 Gbps) */
97 #define OPA_LINK_SPEED_12_5G 0x0001 /* 12.5 Gbps */
98 #define OPA_LINK_SPEED_25G 0x0002 /* 25.78125? Gbps (EDR) */
111 /* reserved (1 << 2) */
118 OPA_PORT_PHYS_CONF_FIXED = 2,
146 /* Filter Raw In/Out bits 1 and 2 were removed */
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