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/openbmc/linux/drivers/gpu/drm/exynos/
H A Dregs-scaler.h206 #define SCALER_SRC_CFG_SET_BYTE_SWAP(v) SCALER_SET(v, 6, 5) argument
208 #define SCALER_SRC_CFG_SET_COLOR_FORMAT(v) SCALER_SET(v, 4, 0) argument
231 #define SCALER_SRC_SPAN_GET_C_SPAN(r) SCALER_GET(r, 29, 16)
232 #define SCALER_SRC_SPAN_SET_C_SPAN(v) SCALER_SET(v, 29, 16) argument
234 #define SCALER_SRC_SPAN_SET_Y_SPAN(v) SCALER_SET(v, 13, 0) argument
238 #define SCALER_SRC_Y_POS_SET_YH_POS(v) SCALER_SET(v, 31, 16) argument
240 #define SCALER_SRC_Y_POS_SET_YV_POS(v) SCALER_SET(v, 15, 0) argument
243 #define SCALER_SRC_WH_GET_WIDTH(r) SCALER_GET(r, 29, 16)
244 #define SCALER_SRC_WH_SET_WIDTH(v) SCALER_SET(v, 29, 16) argument
246 #define SCALER_SRC_WH_SET_HEIGHT(v) SCALER_SET(v, 13, 0) argument
[all …]
/openbmc/linux/arch/arm64/crypto/
H A Dsha512-ce-core.S85 ld1 {v\rc1\().2d}, [x4], #16
87 add v5.2d, v\rc0\().2d, v\in0\().2d
88 ext v6.16b, v\i2\().16b, v\i3\().16b, #8
90 ext v7.16b, v\i1\().16b, v\i2\().16b, #8
91 add v\i3\().2d, v\i3\().2d, v5.2d
93 ext v5.16b, v\in3\().16b, v\in4\().16b, #8
94 sha512su0 v\in0\().2d, v\in1\().2d
98 sha512su1 v\in0\().2d, v\in2\().2d, v5.2d
100 add v\i4\().2d, v\i1\().2d, v\i3\().2d
101 sha512h2 q\i3, q\i1, v\i0\().2d
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/openbmc/u-boot/drivers/usb/host/
H A Dehci-mxc.c18 #define MX25_OTG_SIC_SHIFT 29
34 #define MX31_OTG_SIC_SHIFT 29
48 #define MX35_OTG_SIC_SHIFT 29
66 unsigned int v; in mxc_set_usbcontrol() local
68 v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); in mxc_set_usbcontrol()
72 v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT | in mxc_set_usbcontrol()
74 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT; in mxc_set_usbcontrol()
77 v |= MX25_OTG_PM_BIT; in mxc_set_usbcontrol()
80 v |= MX25_OTG_PP_BIT; in mxc_set_usbcontrol()
83 v |= MX25_OTG_OCPOL_BIT; in mxc_set_usbcontrol()
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/openbmc/linux/drivers/staging/media/sunxi/cedrus/
H A Dcedrus_regs.h13 #define SHIFT_AND_MASK_BITS(v, h, l) \ argument
14 (((unsigned long)(v) << (l)) & GENMASK(h, l))
104 #define VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST(v) \ argument
105 ((v) ? BIT(7) : 0)
106 #define VE_DEC_MPEG_MP12HDR_FRAME_PRED_FRAME_DCT(v) \ argument
107 ((v) ? BIT(6) : 0)
108 #define VE_DEC_MPEG_MP12HDR_CONCEALMENT_MOTION_VECTORS(v) \ argument
109 ((v) ? BIT(5) : 0)
110 #define VE_DEC_MPEG_MP12HDR_Q_SCALE_TYPE(v) \ argument
111 ((v) ? BIT(4) : 0)
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/openbmc/linux/sound/soc/qcom/
H A Dlpass-sc7280.c113 struct lpass_variant *v = drvdata->variant; in sc7280_lpass_alloc_dma_channel() local
120 v->rdma_channels); in sc7280_lpass_alloc_dma_channel()
122 if (chan >= v->rdma_channels) in sc7280_lpass_alloc_dma_channel()
126 v->wrdma_channel_start + in sc7280_lpass_alloc_dma_channel()
127 v->wrdma_channels, in sc7280_lpass_alloc_dma_channel()
128 v->wrdma_channel_start); in sc7280_lpass_alloc_dma_channel()
130 if (chan >= v->wrdma_channel_start + v->wrdma_channels) in sc7280_lpass_alloc_dma_channel()
137 v->hdmi_rdma_channels); in sc7280_lpass_alloc_dma_channel()
138 if (chan >= v->hdmi_rdma_channels) in sc7280_lpass_alloc_dma_channel()
144 v->rxtx_rdma_channels); in sc7280_lpass_alloc_dma_channel()
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/openbmc/linux/drivers/i3c/master/mipi-i3c-hci/
H A Dcmd_v1.c27 #define CMD_A0_DEV_COUNT(v) FIELD_PREP(W0_MASK(29, 26), v) argument
28 #define CMD_A0_DEV_INDEX(v) FIELD_PREP(W0_MASK(20, 16), v) argument
29 #define CMD_A0_CMD(v) FIELD_PREP(W0_MASK(14, 7), v) argument
30 #define CMD_A0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v) argument
38 #define CMD_I1_DATA_BYTE_4(v) FIELD_PREP(W1_MASK(63, 56), v) argument
39 #define CMD_I1_DATA_BYTE_3(v) FIELD_PREP(W1_MASK(55, 48), v) argument
40 #define CMD_I1_DATA_BYTE_2(v) FIELD_PREP(W1_MASK(47, 40), v) argument
41 #define CMD_I1_DATA_BYTE_1(v) FIELD_PREP(W1_MASK(39, 32), v) argument
42 #define CMD_I1_DEF_BYTE(v) FIELD_PREP(W1_MASK(39, 32), v) argument
45 #define CMD_I0_RNW W0_BIT_(29)
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/openbmc/openbmc/poky/bitbake/lib/toaster/toastergui/static/fonts/
H A Dfontawesome-webfont.svg34 <glyph unicode="&#xf000;" horiz-adv-x="1792" d="M1699 1350q0 -35 -43 -78l-632 -632v-768h320q26 0 45…
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42 …v-128q0 -26 19 -45t45 -19h128q26 0 45 19t19 45zM384 320v128q0 26 -19 45t-45 19h-128q-26 0 -45 -19t…
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48 …v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-224v-224q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22…
49 <glyph unicode="&#xf010;" horiz-adv-x="1664" d="M1024 736v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-576q-13 …
50 ….5 84.5t24.5 94.5q31 43 84 50t95 -25q146 -109 226.5 -270t80.5 -343zM896 1408v-640q0 -52 -38 -90t-9…
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H A Dglyphicons-halflings-regular.svg12 …v-224l158 158q7 7 18 8t19 -6l106 -106q7 -8 6 -19t-8 -18l-158 -158h224q10 0 18.5 -7.5t10.5 -17.5q6 …
13 …50 1100h200q21 0 35.5 -14.5t14.5 -35.5v-350h350q21 0 35.5 -14.5t14.5 -35.5v-200q0 -21 -14.5 -35.5t…
15 …6t-3 -14l-120 -160q-6 -8 -18 -14t-22 -6h-125v-100h275q10 0 13 -6t-3 -14l-120 -160q-6 -8 -18 -14t-2…
29 …00q-6 -50 -6 -100h406l-100 -100h-300q9 -74 33 -132t52.5 -91t61.5 -54.5t59 -29 t47 -7.5q22 0 50.5 7…
30 …v-16.5v-16.5q0 -36 -0.5 -57t-6.5 -61t-17 -65t-35 -57t-57 -50.5t-86 -31.5t-120 -13h-178l-2 -100h288…
31 <glyph unicode="&#x2212;" d="M250 700h800q21 0 35.5 -14.5t14.5 -35.5v-200q0 -21 -14.5 -35.5t-35.5 -…
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35 …v-42h-1200v42q0 21 15 39.5t35 18.5h30l468 746l-135 183q-10 16 -5.5 34t20.5 28t34 5.5t28 -20.5l111 …
36 …-13 -5.5t-5 12.5v550q0 10 5 12.5t13 -5.5zM918 618l264 264q8 8 13 5.5t5 -12.5v-550q0 -10 -5 -12.5t-…
38 <glyph unicode="&#xe001;" d="M700 650v-550h250q21 0 35.5 -14.5t14.5 -35.5v-50h-800v50q0 21 14.5 35.…
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/openbmc/linux/drivers/media/platform/verisilicon/
H A Dhantro_g1_regs.h136 #define G1_REG_DEC_CTRL4_DIR_8X8_INFER_E BIT(29)
144 #define G1_REG_DEC_CTRL4_BITPLANE2_E BIT(29)
173 #define G1_REG_DEC_CTRL5_RDPIC_CNT_PRES BIT(29)
313 #define G1_REG_PP_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24)) argument
314 #define G1_REG_PP_AXI_WR_ID(v) (((v) << 16) & GENMASK(23, 16)) argument
315 #define G1_REG_PP_INSWAP32_E(v) ((v) ? BIT(10) : 0) argument
316 #define G1_REG_PP_DATA_DISC_E(v) ((v) ? BIT(9) : 0) argument
317 #define G1_REG_PP_CLK_GATE_E(v) ((v) ? BIT(8) : 0) argument
318 #define G1_REG_PP_IN_ENDIAN(v) ((v) ? BIT(7) : 0) argument
319 #define G1_REG_PP_OUT_ENDIAN(v) ((v) ? BIT(6) : 0) argument
[all …]
H A Drockchip_vpu2_hw_h264_dec.c28 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
30 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
31 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
32 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
33 #define VDPU_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(7) : 0) argument
34 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
36 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
37 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
39 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
40 #define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) argument
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dsiul.h50 #define SIUL2_MSCR_DDR_DO_TRIM(v) ((v) & 0xC0000000) argument
56 #define SIUL2_MSCR_DDR_INPUT(v) ((v) & 0x20000000) argument
57 #define SIUL2_MSCR_DDR_INPUT_CMOS (0 << 29)
58 #define SIUL2_MSCR_DDR_INPUT_DIFF_DDR (1 << 29)
60 #define SIUL2_MSCR_DDR_SEL(v) ((v) & 0x18000000) argument
64 #define SIUL2_MSCR_DDR_ODT(v) ((v) & 0x07000000) argument
73 #define SIUL2_MSCR_DCYCLE_TRIM(v) ((v) & 0x00C00000) argument
78 #define SIUL2_MSCR_OBE(v) ((v) & 0x00200000) argument
81 #define SIUL2_MSCR_ODE(v) ((v) & 0x00100000) argument
84 #define SIUL2_MSCR_IBE(v) ((v) & 0x00010000) argument
[all …]
/openbmc/linux/drivers/media/platform/sunxi/sun6i-mipi-csi2/
H A Dsun6i_mipi_csi2_reg.h17 #define SUN6I_MIPI_CSI2_CFG_CHANNEL_MODE(v) ((((v) - 1) << 8) & \ argument
19 #define SUN6I_MIPI_CSI2_CFG_LANE_COUNT(v) (((v) - 1) & GENMASK(1, 0)) argument
32 #define SUN6I_MIPI_CSI2_CH_INT_EN_EOT_ERR BIT(29)
49 #define SUN6I_MIPI_CSI2_CH_INT_PD_EOT_ERR BIT(29)
/openbmc/linux/arch/alpha/kernel/
H A Dentry.S47 * regs 29-30 saved and set up by PAL-code
314 .cfi_rel_offset $29, 29*8
373 .cfi_restore $29
691 #define V(n) stt $f##n, FR(n) macro
692 V( 0); V( 1); V( 2); V( 3)
693 V( 4); V( 5); V( 6); V( 7)
694 V( 8); V( 9); V(10); V(11)
695 V(12); V(13); V(14); V(15)
696 V(16); V(17); V(18); V(19)
697 V(20); V(21); V(22); V(23)
[all …]
/openbmc/u-boot/include/net/pfe_eth/pfe/cbus/
H A Demac.h34 #define EMAC_IEVENT_BABT BIT(29)
48 #define EMAC_IMASKT_BABT BIT(29)
118 #define EMAC_MII_DATA_RA(v) ((v & EMAC_MII_DATA_RA_MASK) <<\ argument
120 #define EMAC_MII_DATA_PA(v) ((v & EMAC_MII_DATA_RA_MASK) <<\ argument
122 #define EMAC_MII_DATA(v) (v & 0xffff) argument
127 #define EMAC_HOLDTIME(v) ((v & EMAC_HOLDTIME_MASK) << EMAC_HOLDTIME_SHIFT) argument
/openbmc/linux/include/linux/spi/
H A Dmxs-spi.h20 #define BM_SSP_CTRL0_RUN (1 << 29)
58 #define BF_SSP_TIMING_CLOCK_DIVIDE(v) \ argument
59 (((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE)
62 #define BF_SSP_TIMING_CLOCK_RATE(v) \ argument
63 (((v) << 0) & BM_SSP_TIMING_CLOCK_RATE)
67 #define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29)
86 #define BF_SSP_CTRL1_WORD_LENGTH(v) \ argument
87 (((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH)
93 #define BF_SSP_CTRL1_SSP_MODE(v) \ argument
94 (((v) << 0) & BM_SSP_CTRL1_SSP_MODE)
/openbmc/linux/drivers/platform/x86/intel/pmt/
H A Dcrashlog.c29 * Bits 29 and 30 control the state of bit 31.
31 * Bit 29 will clear bit 31, if set, allowing a new crashlog to be captured.
35 #define CRASHLOG_FLAG_TRIGGER_CLEAR BIT(29)
45 #define GET_ACCESS(v) ((v) & GENMASK(3, 0)) argument
46 #define GET_TYPE(v) (((v) & GENMASK(7, 4)) >> 4) argument
47 #define GET_VERSION(v) (((v) & GENMASK(19, 16)) >> 16) argument
49 #define GET_SIZE(v) ((v) * sizeof(u32)) argument
/openbmc/linux/drivers/video/fbdev/
H A Dvalkyriefb.h8 * Vmode-switching changes and vmode 15/17 modifications created 29 August
102 { 11, 28, 3 }, /* pixel clock = 79.55MHz for V=74.50Hz */
108 /* This used to be 12, 30, 3 for pixel clock = 78.12MHz for V=72.12Hz, but
118 { 12, 29, 3 }, /* pixel clock = 75.52MHz for V=69.71Hz? */
119 /* I interpolated the V=69.71 from the vmode 14 and old 15
129 { 15, 31, 3 }, /* pixel clock = 64.58MHz for V=59.62Hz */
138 { 23, 42, 3 }, /* pixel clock = 57.07MHz for V=74.27Hz */
146 { 17, 27, 3 }, /* pixel clock = 49.63MHz for V=71.66Hz */
155 used to be 20,53,2, pixel clock 41.41MHz for V=59.78Hz */
163 { 14, 27, 2 }, /* pixel clock = 30.13MHz for V=66.43Hz */
[all …]
/openbmc/u-boot/doc/
H A DREADME.ae3505 base on RISC-V architecture.
66 RISC-V # version
72 RISC-V # setenv ipaddr 10.0.4.200 ;
73 RISC-V # setenv serverip 10.0.4.97 ;
74 RISC-V # ping 10.0.4.97 ;
78 RISC-V # mmc rescan
79 RISC-V # fatls mmc 0:1
86 RISC-V # sf probe 0:0 50000000 0
89 RISC-V # sf test 0x100000 0x1000
92 1 check: 29 ticks, 137 KiB/s 1.096 Mbps
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-vf610/
H A Dcrm_regs.h118 #define CCM_CCR_OSCNT(v) ((v) & 0xff) argument
122 #define CCM_CCSR_PLL2_PFD_CLK_SEL(v) (((v) & 0x7) << 19) argument
126 #define CCM_CCSR_PLL1_PFD_CLK_SEL(v) (((v) & 0x7) << 16) argument
137 #define CCM_CCSR_DDRC_CLK_SEL(v) ((v) << 6) argument
138 #define CCM_CCSR_FAST_CLK_SEL(v) ((v) << 5) argument
142 #define CCM_CCSR_SYS_CLK_SEL(v) ((v) & 0x7) argument
146 #define CCM_CACRR_IPG_CLK_DIV(v) (((v) & 0x3) << 11) argument
149 #define CCM_CACRR_BUS_CLK_DIV(v) (((v) & 0x7) << 3) argument
152 #define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7) argument
154 #define CCM_CSCMR1_DCU1_CLK_SEL (1 << 29)
[all …]
/openbmc/linux/drivers/scsi/pm8001/
H A Dpm80xx_hwi.h125 #define OPC_OUB_SAS_DIAG_EXECUTE 29 /* 0x01D */
343 /* Bits [30:29] - Reserved */
366 u32 reserved[29];
467 u32 reserved[29];
488 u32 reserved1[29];
693 u32 reserved[29];
755 __le32 enc_addr_high; /* dword 29. Encryption SGL address low */
819 __le32 enc_addr_high; /* dword 29: Encryption sgl addr hi */
970 __le32 reserved[29];
980 __le32 profile[29];
[all …]
/openbmc/linux/drivers/media/platform/nxp/dw100/
H A Ddw100_regs.h37 #define DW100_MAP_LUT_ADDR_ADDR(addr) (((addr) >> 4) & GENMASK(29, 0))
42 #define DW100_IMG_Y_BASE(base) (((base) >> 4) & GENMASK(29, 0))
44 #define DW100_IMG_UV_BASE(base) (((base) >> 4) & GENMASK(29, 0))
86 #define DW100_BOUNDARY_PIXEL_V(v) (((v) & GENMASK(7, 0)) << 0) argument
111 #define DW100_DST_IMG_Y_SIZE(sz) (((sz) >> 4) & GENMASK(29, 0))
112 #define DW100_DST_IMG_UV_SIZE(sz) (((sz) >> 4) & GENMASK(29, 0))
/openbmc/webui-vue/src/assets/images/
H A Dlogo-header.svg1 …v-6.61c-1.17-.274-2.058-.918-2.626-1.978a3.713 3.713 0 01-.436-1.736h1.749c.046.723.343 1.313.954 …
/openbmc/linux/drivers/media/v4l2-core/
H A Dv4l2-vp9.c18 { 92, 45, 102, 136, 116, 180, 74, 90, 100 }, /*left = v */
27 }, { /* above = v */
29 { 43, 46, 168, 134, 107, 128, 69, 142, 92 }, /*left = v */
30 { 44, 29, 68, 159, 201, 177, 50, 57, 77 }, /*left = h */
40 { 55, 44, 68, 166, 179, 192, 57, 57, 108 }, /*left = v */
51 { 59, 38, 83, 112, 103, 162, 98, 136, 90 }, /*left = v */
53 { 67, 30, 29, 84, 86, 191, 102, 91, 59 }, /*left = d45 */
57 { 77, 19, 29, 112, 142, 228, 55, 66, 36 }, /*left = d207*/
58 { 61, 29, 29, 93, 97, 165, 83, 175, 162 }, /*left = d63 */
61 { 69, 23, 29, 128, 83, 199, 46, 44, 101 }, /*left = dc */
[all …]
/openbmc/qemu/target/xtensa/
H A Dmmu_helper.c73 void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v) in HELPER()
75 v = (v & 0xffffff00) | 0x1; in HELPER()
76 if (v != env->sregs[RASID]) { in HELPER()
77 env->sregs[RASID] = v; in HELPER()
172 static void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, in split_tlb_entry_spec_way() argument
188 *ei = (v >> 12) & (is32 ? 0x7 : 0x3); in split_tlb_entry_spec_way()
194 *ei = (v >> eibase) & 0x3; in split_tlb_entry_spec_way()
201 *ei = (v >> eibase) & 0x3; in split_tlb_entry_spec_way()
203 *ei = (v >> 27) & 0x1; in split_tlb_entry_spec_way()
209 uint32_t eibase = 29 - get_page_size(env, dtlb, wi); in split_tlb_entry_spec_way()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx6/
H A Dcrm_regs.h263 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29)
264 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29
297 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29)
298 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
411 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21) argument
414 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << 18) argument
417 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15) argument
421 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21) argument
424 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18) argument
428 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) (((v) & 0x7) << 15) argument
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