Lines Matching +full:29 +full:v

263 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK		(0x7 << 29)
264 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29
297 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29)
298 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
411 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21) argument
414 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << 18) argument
417 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15) argument
421 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21) argument
424 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18) argument
428 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) (((v) & 0x7) << 15) argument
431 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16) argument
441 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \ argument
443 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) : \
444 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v))
457 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29)
458 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29
985 #define BF_ANADIG_PLL_SYS_RSVD0(v) \ argument
986 (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0)
993 #define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \ argument
994 (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
1008 #define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \ argument
1009 (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT)
1014 #define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \ argument
1015 (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1)
1019 #define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \ argument
1020 (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
1036 #define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \ argument
1037 (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
1040 #define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \ argument
1041 (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
1046 #define BF_ANADIG_PLL_528_RSVD1(v) \ argument
1047 (((v) << 19) & BM_ANADIG_PLL_528_RSVD1)
1053 #define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \ argument
1054 (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
1068 #define BF_ANADIG_PLL_528_RSVD0(v) \ argument
1069 (((v) << 1) & BM_ANADIG_PLL_528_RSVD0)
1074 #define BF_ANADIG_PLL_528_SS_STOP(v) \ argument
1075 (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP)
1079 #define BF_ANADIG_PLL_528_SS_STEP(v) \ argument
1080 (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP)
1084 #define BF_ANADIG_PLL_528_NUM_RSVD0(v) \ argument
1085 (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0)
1088 #define BF_ANADIG_PLL_528_NUM_A(v) \ argument
1089 (((v) << 0) & BM_ANADIG_PLL_528_NUM_A)
1093 #define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \ argument
1094 (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0)
1097 #define BF_ANADIG_PLL_528_DENOM_B(v) \ argument
1098 (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B)
1103 #define BF_ANADIG_PLL_AUDIO_RSVD0(v) \ argument
1104 (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0)
1108 #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \ argument
1109 (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
1115 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \ argument
1116 (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
1130 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \ argument
1131 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
1135 #define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \ argument
1136 (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0)
1139 #define BF_ANADIG_PLL_AUDIO_NUM_A(v) \ argument
1140 (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A)
1144 #define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \ argument
1145 (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0)
1148 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \ argument
1149 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B)
1154 #define BF_ANADIG_PLL_VIDEO_RSVD0(v) \ argument
1155 (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
1159 #define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \ argument
1160 (((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
1166 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \ argument
1167 (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
1181 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \ argument
1182 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
1186 #define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \ argument
1187 (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0)
1190 #define BF_ANADIG_PLL_VIDEO_NUM_A(v) \ argument
1191 (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A)
1195 #define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \ argument
1196 (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0)
1199 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \ argument
1200 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B)
1205 #define BF_ANADIG_PLL_ENET_RSVD1(v) \ argument
1206 (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1)
1215 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \ argument
1216 (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
1230 #define BF_ANADIG_PLL_ENET_RSVD0(v) \ argument
1231 (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0)
1234 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ argument
1235 (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
1240 #define BF_ANADIG_PLL_ENET2_DIV_SELECT(v) \ argument
1241 (((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT)
1247 #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \ argument
1248 (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC)
1253 #define BF_ANADIG_PFD_480_PFD2_FRAC(v) \ argument
1254 (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC)
1259 #define BF_ANADIG_PFD_480_PFD1_FRAC(v) \ argument
1260 (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC)
1265 #define BF_ANADIG_PFD_480_PFD0_FRAC(v) \ argument
1266 (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC)
1272 #define BF_ANADIG_PFD_528_PFD3_FRAC(v) \ argument
1273 (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC)
1278 #define BF_ANADIG_PFD_528_PFD2_FRAC(v) \ argument
1279 (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC)
1284 #define BF_ANADIG_PFD_528_PFD1_FRAC(v) \ argument
1285 (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC)
1290 #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ argument
1291 (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
1303 #define PMU_MISC2_AUDIO_DIV(v) \ argument
1304 (((v & BM_PMU_MISC2_AUDIO_DIV_MSB) >> \
1306 ((v & BM_PMU_MISC2_AUDIO_DIV_LSB) >> \