Home
last modified time | relevance | path

Searched +full:1 +full:khz (Results 1 – 25 of 1015) sorted by relevance

12345678910>>...41

/openbmc/linux/Documentation/fb/
H A Dviafb.modes14 # Scan Frequency 31.469 kHz 59.94 Hz
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
33 geometry 480 640 480 640 32 timings 39722 72 24 19 1 48 3 endmode
39 # Scan Frequency 37.500 kHz 75.00 Hz
43 # 2 chars 1 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
54 geometry 640 480 640 480 32 timings 31747 120 16 16 1 64 3 endmode
60 # Scan Frequency 43.269 kHz 85.00 Hz
64 # 7 chars 1 lines
[all …]
/openbmc/linux/include/sound/
H A Dasoundef.h17 #define IEC958_AES0_PROFESSIONAL (1<<0) /* 0 = consumer, 1 = professional */
18 #define IEC958_AES0_NONAUDIO (1<<1) /* 0 = audio, 1 = non-audio */
21 #define IEC958_AES0_PRO_EMPHASIS_NONE (1<<2) /* none emphasis */
24 #define IEC958_AES0_PRO_FREQ_UNLOCKED (1<<5) /* source sample frequency: 0 = locked, 1 = unlocked */
27 #define IEC958_AES0_PRO_FS_44100 (1<<6) /* 44.1kHz */
28 #define IEC958_AES0_PRO_FS_48000 (2<<6) /* 48kHz */
29 #define IEC958_AES0_PRO_FS_32000 (3<<6) /* 32kHz */
30 #define IEC958_AES0_CON_NOT_COPYRIGHT (1<<2) /* 0 = copyright, 1 = not copyright */
33 #define IEC958_AES0_CON_EMPHASIS_5015 (1<<3) /* 50/15us emphasis */
98 #define IEC958_AES1_CON_ORIGINAL (1<<7) /* this bits depends on the category code */
[all …]
H A Demu10k1.h62 #define REG_MASK0(r) ((1U << REG_SIZE(r)) - 1U)
89 /* Clear pending interrupts by writing a 1 to */
186 /* NOTE: Each channel takes 1/64th of a sample */
203 #define HCFG_LEGACYWRITE 0x00800000 /* 1 = write, 0 = read */
204 #define HCFG_LEGACYWORD 0x00400000 /* 1 = word, 0 = byte */
205 #define HCFG_LEGACYINT 0x00200000 /* 1 = legacy event captured. Write 1 to clear. */
209 #define HCFG_BAUD_RATE 0x00080000 /* 0 = 48kHz, 1 = 44.1kHz */
210 #define HCFG_EXPANDED_MEM 0x00040000 /* 1 = any 16M of 4G addr, 0 = 32M of 2G addr */
224 #define HCFG_EMU32_SLAVE 0x00002000 /* 0 = Master, 1 = Slave. Slave for EMU1010 */
247 /* 1 = Force all 3 async digital inputs to use */
[all …]
H A Ddesignware_i2s.h16 * @sample_rate: sampling frequency (8Khz, 16Khz, 32Khz, 44Khz, 48Khz)
27 #define DWC_I2S_PLAY (1 << 0)
28 #define DWC_I2S_RECORD (1 << 1)
29 #define DW_I2S_SLAVE (1 << 2)
30 #define DW_I2S_MASTER (1 << 3)
36 #define DW_I2S_QUIRK_COMP_REG_OFFSET (1 << 0)
37 #define DW_I2S_QUIRK_COMP_PARAM1 (1 << 1)
38 #define DW_I2S_QUIRK_16BIT_IDX_OVERRIDE (1 << 2)
/openbmc/linux/sound/ppc/
H A Dawacs.h25 unsigned byteswap; /* Data is little-endian if 1 */
45 #define MASK_NEWECMD (0x1 << 24) /* Lock: don't write to reg when 1 */
56 #define MASK_ADDR1 (0x1 << 12) /* Expanded Data Mode Address 1 */
91 /* Address 1 Bit Masks */
98 #define MASK_CMUTE (0x1 << 7) /* Output C (Speaker) Mute when 1 */
102 #define MASK_AMUTE (0x1 << 9) /* Output A (Headphone) Mute when 1 */
112 #define SAMPLERATE_48000 (0x0 << 3) /* 48 or 44.1 kHz */
113 #define SAMPLERATE_32000 (0x1 << 3) /* 32 or 29.4 kHz */
114 #define SAMPLERATE_24000 (0x2 << 3) /* 24 or 22.05 kHz */
115 #define SAMPLERATE_19200 (0x3 << 3) /* 19.2 or 17.64 kHz */
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/include/
H A Dgrph_object_ctrl_defs.h44 PANEL_6BIT_COLOR = 1,
67 uint32_t enum_id:16; /* 1 based enum */
110 uint32_t HORIZONTAL_CUT_OFF:1;
111 /* 0=Active High, 1=Active Low */
112 uint32_t H_SYNC_POLARITY:1;
113 /* 0=Active High, 1=Active Low */
114 uint32_t V_SYNC_POLARITY:1;
115 uint32_t VERTICAL_CUT_OFF:1;
116 uint32_t H_REPLICATION_BY2:1;
117 uint32_t V_REPLICATION_BY2:1;
[all …]
/openbmc/linux/drivers/video/fbdev/core/
H A Dmodedb.c38 /* 640x400 @ 70 Hz, 31.5 kHz hsync */
42 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
46 /* 800x600 @ 56 Hz, 35.15 kHz hsync */
47 { NULL, 56, 800, 600, 27777, 128, 24, 22, 1, 72, 2, 0,
50 /* 1024x768 @ 87 Hz interlaced, 35.5 kHz hsync */
54 /* 640x400 @ 85 Hz, 37.86 kHz hsync */
55 { NULL, 85, 640, 400, 31746, 96, 32, 41, 1, 64, 3,
58 /* 640x480 @ 72 Hz, 36.5 kHz hsync */
62 /* 640x480 @ 75 Hz, 37.50 kHz hsync */
63 { NULL, 75, 640, 480, 31746, 120, 16, 16, 1, 64, 3, 0,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dlpc1850-creg-clk.txt5 32 kHz oscillator driver with power up/down and clock gating. Next
6 is a fixed divider that creates a 1 kHz clock from the 32 kHz osc.
9 The 32 kHz can also be routed to other peripherals to enable low
19 Shall have value <1>.
21 Shall contain a phandle to the fixed 32 kHz crystal.
28 0 1 kHz clock
29 1 32 kHz Oscillator
40 #clock-cells = <1>;
/openbmc/u-boot/drivers/i2c/
H A Daspeed_i2c_global.c28 * div : scl : baseclk [APB/((div/2) + 1)] : tBuf [1/bclk * 16]
30 * I2CG10[23:16] base clk3 for Standard-mode (100Khz) min tBuf 4.7us
31 * 0x3c : 100.8Khz : 3.225Mhz : 4.96us
32 * 0x3d : 99.2Khz : 3.174Mhz : 5.04us
33 * 0x3e : 97.65Khz : 3.125Mhz : 5.12us
34 * 0x40 : 97.75Khz : 3.03Mhz : 5.28us
35 * 0x41 : 99.5Khz : 2.98Mhz : 5.36us (default)
36 * I2CG10[15:8] base clk2 for Fast-mode (400Khz) min tBuf 1.3us
37 * 0x12 : 400Khz : 10Mhz : 1.6us
38 * I2CG10[7:0] base clk1 for Fast-mode Plus (1Mhz) min tBuf 0.5us
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3399.h34 check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134);
68 check_member(rk3399_cru, sdio1_con[1], 0x594);
70 #define KHz 1000 macro
88 #define PERIHP_ACLK_HZ (148500*KHz)
89 #define PERIHP_HCLK_HZ (148500*KHz)
90 #define PERIHP_PCLK_HZ (37125*KHz)
92 #define PERILP0_ACLK_HZ (99000*KHz)
93 #define PERILP0_HCLK_HZ (99000*KHz)
94 #define PERILP0_PCLK_HZ (49500*KHz)
96 #define PERILP1_HCLK_HZ (99000*KHz)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dti,j721e-cpb-ivi-audio.yaml23 In order to support 48KHz and 44.1KHz family of sampling rates the parent clock
24 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
25 44.1KHz). The same PLLs are used for McASP0's AUXCLK clock via different
30 Clocking setup for 48KHz family:
37 Clocking setup for 44.1KHz family:
76 - description: Parent for CPB_McASP auxclk (for 48KHz)
77 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
79 - description: Parent for CPB_SCKI clock (for 48KHz)
80 - description: Parent for CPB_SCKI clock (for 44.1KHz)
82 - description: Parent for IVI_McASP auxclk (for 48KHz)
[all …]
H A Dti,j721e-cpb-audio.yaml18 In order to support 48KHz and 44.1KHz family of sampling rates the parent
19 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
20 PLL15 (for 44.1KHz). The same PLLs are used for McASP10's AUXCLK clock via
24 48KHz family:
28 44.1KHz family:
33 48KHz family:
85 - description: Parent for CPB_McASP auxclk (for 48KHz)
86 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
88 - description: Parent for CPB_SCKI clock (for 48KHz)
89 - description: Parent for CPB_SCKI clock (for 44.1KHz)
[all …]
/openbmc/linux/Documentation/sound/cards/
H A Daudiophile-usb.rst35 - This port supports 2 pairs of line-level audio inputs (1/4" TS and RCA)
36 - When the 1/4" TS (jack) connectors are connected, the RCA connectors
48 * sample rate from 8kHz to 96kHz
57 * 16-bit/48kHz ==> 4 channels in + 4 channels out
61 * 24-bit/48kHz ==> 4 channels in + 2 channels out,
66 * 24-bit/96kHz ==> 2 channels in _or_ 2 channels out (half duplex only)
125 way (I suppose the device's index is 1):
127 * hw:1,0 is Ao in playback and Di in capture
128 * hw:1,1 is Do in playback and Ai in capture
129 * hw:1,2 is Do in AC3/DTS passthrough mode
[all …]
/openbmc/linux/tools/testing/selftests/alsa/
H A Dpcm-test.conf2 description "8kHz mono large periods"
6 channels 1
11 description "8kHz stereo large periods"
20 description "44.1kHz stereo large periods"
29 description "48kHz stereo small periods"
38 description "48kHz stereo large periods"
47 description "48kHz 6 channel large periods"
56 description "96kHz stereo large periods"
/openbmc/linux/sound/pci/ca0106/
H A Dca0106.h65 /* CNL[1:0], ADDR[27:16] */
71 /* Clear pending interrupts by writing a 1 to */
116 #define HCFG_CAPTURE_I2S_BYPASS 0x08000000 /* 1 = bypass I2S input async SRC. */
117 #define HCFG_CAPTURE_SPDIF_BYPASS 0x04000000 /* 1 = bypass SPDIF input async SRC. */
118 #define HCFG_PLAYBACK_I2S_BYPASS 0x02000000 /* 0 = I2S IN mixer output, 1 = I2S IN1. */
120 #define HCFG_PLAYBACK_ATTENUATION 0x00006000 /* Playback attenuation mask. 0 = 0dB, 1 = 6dB, 2 = 12…
121 #define HCFG_PLAYBACK_DITHER 0x00001000 /* 1 = Add dither bit to all playback channels. */
122 #define HCFG_PLAYBACK_S32_LE 0x00000800 /* 1 = S32_LE, 0 = S16_LE */
123 #define HCFG_CAPTURE_S32_LE 0x00000400 /* 1 = S32_LE, 0 = S16_LE (S32_LE current not working) */
124 #define HCFG_8_CHANNEL_PLAY 0x00000200 /* 1 = 8 channels, 0 = 2 channels per substream.*/
[all …]
/openbmc/linux/drivers/media/dvb-frontends/
H A Dmxl5xx_defs.h14 MXL_ENABLE = 1,
17 MXL_TRUE = 1,
20 MXL_VALID = 1,
23 MXL_YES = 1,
26 MXL_ON = 1
34 MXL_HYDRA_DEV_SET_POWER_MODE_CMD = 1,
132 #define MXL_HYDRA_SKU_ID_584 1
153 #define MBIN_FORMAT_VERSION '1'
156 #define MBIN_MAX_FILE_LENGTH (1<<23)
171 u8 data[1];
[all …]
/openbmc/linux/include/linux/
H A Dclocksource.h57 * 1-99: Unfit for real use
145 #define CLOCKSOURCE_MASK(bits) GENMASK_ULL((bits) - 1, 0)
165 * clocksource_khz2mult - calculates mult from khz and shift
166 * @khz: Clocksource frequency in KHz
169 * Helper functions that converts a khz counter frequency to a timsource
172 static inline u32 clocksource_khz2mult(u32 khz, u32 shift_constant) in clocksource_khz2mult() argument
174 return clocksource_freq2mult(khz, shift_constant, NSEC_PER_MSEC); in clocksource_khz2mult()
228 * clocksource_register_hz/khz
241 return __clocksource_register_scale(cs, 1, 0); in __clocksource_register()
246 return __clocksource_register_scale(cs, 1, hz); in clocksource_register_hz()
[all …]
/openbmc/u-boot/arch/arm/mach-imx/mx7ulp/
H A Dclock.c151 /* 158MHz / 1 = 158MHz */ in init_clk_usdhc()
153 pcc_clock_div_config(PER_CLK_USDHC0, false, 1); in init_clk_usdhc()
156 case 1: in init_clk_usdhc()
160 /* 158MHz / 1 = 158MHz */ in init_clk_usdhc()
162 pcc_clock_div_config(PER_CLK_USDHC1, false, 1); in init_clk_usdhc()
204 if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1) { in enable_usboh3_clk()
290 * 1. Enable PFD1-3 of APLL for A7 side. Enable FIRC and DIVs. in clock_init()
312 enable_usboh3_clk(1); in clock_init()
344 printf("CORE %8d kHz\n", scg_clk_get_rate(SCG_CORE_CLK) / 1000); in do_mx7_showclocks()
345 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); in do_mx7_showclocks()
[all …]
/openbmc/linux/drivers/gpu/drm/radeon/
H A Datombios.h59 #define ATOM_DAC_B 1
63 #define ATOM_CRTC2 1
71 #define ATOM_DIGB 1
74 #define ATOM_PPLL2 1
85 #define ENCODER_REFCLK_SRC_P2PLL 1
91 #define ATOM_SCALER2 1
94 #define ATOM_SCALER_CENTER 1
99 #define ATOM_ENABLE 1
109 #define ATOM_BLANKING 1
113 #define ATOM_CURSOR2 1
[all …]
/openbmc/linux/drivers/cpufreq/
H A Dpowernow-k6.c26 static unsigned int busfreq; /* FSB, in 10 kHz */
36 MODULE_PARM_DESC(bus_frequency, "Bus frequency in kHz");
51 static const u8 index_to_register[8] = { 6, 3, 1, 0, 2, 7, 5, 4 };
52 static const u8 register_to_index[8] = { 3, 2, 4, 1, 7, 6, 0, 5 };
118 outvalue = (1<<12) | (1<<10) | (1<<9) | (index_to_register[best_i]<<5); in powernow_k6_set_cpu_multiplier()
157 unsigned khz; in powernow_k6_cpu_init() local
163 khz = cpu_khz; in powernow_k6_cpu_init()
165 if (khz >= usual_frequency_table[i].freq - FREQ_RANGE && in powernow_k6_cpu_init()
166 khz <= usual_frequency_table[i].freq + FREQ_RANGE) { in powernow_k6_cpu_init()
167 khz = usual_frequency_table[i].freq; in powernow_k6_cpu_init()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/
H A Datombios.h58 #define ATOM_DAC_B 1
62 #define ATOM_CRTC2 1
74 #define ATOM_DIGB 1
77 #define ATOM_PPLL2 1
102 #define ENCODER_REFCLK_SRC_P2PLL 1
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
113 #define ATOM_ENABLE 1
123 #define ATOM_BLANKING 1
128 #define ATOM_CRT2 1
130 #define ATOM_TV_NTSC 1
[all …]
/openbmc/linux/Documentation/i2c/busses/
H A Di2c-ismt.rst21 Specify the bus speed in kHz.
27 80 kHz
28 100 kHz
29 400 kHz
30 1000 kHz
44 00:13.1 System peripheral: Intel Corporation Centerton SMBus 2.0 Controller 1
/openbmc/linux/arch/arm/mach-omap1/
H A Dtimer32k.c59 * 32KHz OS timer
62 * 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track
63 * of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
65 * with the 32KHz synchronized timer.
79 * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1
82 #define OMAP_32K_TIMER_TICK_PERIOD ((OMAP_32K_TICKS_PER_SEC / HZ) - 1)
95 load_val = 1; in omap_32k_timer_start()
152 IRQF_TIMER | IRQF_IRQPOLL, "32KHz timer", NULL)) in omap_init_32k_timer()
153 pr_err("Failed to request irq %d(32KHz timer)\n", INT_OS_TIMER); in omap_init_32k_timer()
157 OMAP_32K_TICKS_PER_SEC, 1, 0xfffffffe); in omap_init_32k_timer()
[all …]
/openbmc/linux/drivers/media/tuners/
H A Dtda9887.c46 #define UNSET (-1U)
101 #define cAudioIF_4_5 0x00 // bit e0:1
102 #define cAudioIF_5_5 0x01 // bit e0:1
103 #define cAudioIF_6_0 0x02 // bit e0:1
104 #define cAudioIF_6_5 0x03 // bit e0:1
118 /* IF1 selection in Radio Mode (bit B3=1) */
122 /* Output of AFC pin in radio mode when bit E7=1 */
276 "- 12.5 kHz", in dump_read_message()
277 "- 37.5 kHz", in dump_read_message()
278 "- 62.5 kHz", in dump_read_message()
[all …]
/openbmc/u-boot/arch/m68k/cpu/mcf532x/
H A Dspeed.c20 #define MAX_FVCO 500000 /* KHz */
21 #define MAX_FSYS 80000 /* KHz */
22 #define MIN_FSYS 58333 /* KHz */
25 #define FREF 20000 /* KHz */
37 #define FREF 16000 /* KHz */
42 #define MIN_LPD (1 << 0) /* Divider (not encoded) */
43 #define MAX_LPD (1 << 15) /* Divider (not encoded) */
44 #define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */
60 return (FREF / (3 * (1 << divider))); in get_sys_clock()
67 u32 pfdr = (in_be32(&pll->pcr) & 0x3F) + 1; in get_sys_clock()
[all …]

12345678910>>...41