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/openbmc/linux/arch/arm/include/asm/hardware/
H A Dcp14.h35 * Available only in DBGv7.1
45 #define RCP14_DBGDIDR() MRC14(0, c0, c0, 0)
46 #define RCP14_DBGDSCRint() MRC14(0, c0, c1, 0)
47 #define RCP14_DBGDTRRXint() MRC14(0, c0, c5, 0)
48 #define RCP14_DBGWFAR() MRC14(0, c0, c6, 0)
49 #define RCP14_DBGVCR() MRC14(0, c0, c7, 0)
50 #define RCP14_DBGECR() MRC14(0, c0, c9, 0)
51 #define RCP14_DBGDSCCR() MRC14(0, c0, c10, 0)
52 #define RCP14_DBGDSMCR() MRC14(0, c0, c11, 0)
53 #define RCP14_DBGDTRRXext() MRC14(0, c0, c0, 2)
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/openbmc/bmcweb/static/images/
H A DDMTF_Redfish_logo_2017.svg5 …1;} .st0{fill:url(#SVGID_2_);} .st1{fill:url(#SVGID_3_);} .st2{fill:#D31245;} .st3{fil…
17 <stop offset="1" style="stop-color:#EFB5AF"/>
24 <stop offset="1" style="stop-color:#EFB5AF"/>
26 …c0,0-4,2.5-10.8,6.7c-1.2,0.7-2.5,1.5-3.8,2.4c-2.7,1.7-5.7,3.6-9,5.6c-1.2,0.7-2.4,1.5-3.6,2.2 c-1.6…
27 …1l-0.5-0.4 c-0.7-0.6-1.4-1.2-2-1.8c-0.1-0.1-0.2-0.2-0.3-0.3c-0.6-0.7-1.1-1.2-1.5-1.7c-0.2-0.2-0.4-…
32 <stop offset="1" style="stop-color:#EFB5AF"/>
38 …c0.6,1.3,1,2.8,1.3,4.4c0.3,1.6,0.5,3.2,0.5,4.8c0,5.8-1.4,10.4-4.2,13.7c-2.8,3.3-7,5.3-12.5,6l25.1,…
39 …c0,2.2,0.3,4.1,1,5.8c0.7,1.7,1.6,3.2,2.9,4.6c2.4,2.5,5.5,3.7,9.4,3.7c3.5,0,6.4-0.7,8.7-2.2 c2.3-1.…
40 …c0-7.5,1.9-13.6,5.8-18.3c3.9-4.6,9-7,15.4-7c3.9,0,7.1,0.8,9.9,2.4c2.7,1.6,4.7,3.9,6,6.9V429.8z M38…
41 …c0-6.3,1.3-10.9,3.9-13.9c2.6-3,6.6-4.5,12.1-4.5c0.6,0,1.1,0,1.7,0 c0.6,0,1.2,0.1,1.8,0.2c0.6,0.1,1…
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/openbmc/linux/tools/testing/selftests/hid/tests/
H A Dtest_multitouch.py24 return 1 << x
29 "SLOT_IS_CONTACTID": BIT(1),
109 input_info=(BusType.USB, 1, 2), argument
130 self.max_contacts = 1
155 self.scantime += 1
179 return (1, [])
187 return (1, [])
190 return (1, [])
198 return 1
206 return 1
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H A Dtest_tablet.py374 input_info=(BusType.USB, 1, 2), argument
400 return (1, [])
408 return (1, [])
410 return (1, [])
414 return 1
422 return 1
424 return 1
448 events = events[idx + 1 :]
477 p.x += 1
478 p.y -= 1
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/openbmc/linux/arch/arm/mm/
H A Dproc-v7.S34 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
37 mcr p15, 0, r0, c1, c0, 0 @ disable caches
57 mrc p15, 0, r2, c1, c0, 0 @ ctrl register
59 THUMB( bic r2, r2, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
60 mcr p15, 0, r2, c1, c0, 0 @ disable MMU
85 ALT_UP_B(1f)
87 1: dcache_line_size r2, r3
88 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
136 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
137 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
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H A Dproc-v6.S22 #define TTB_C (1 << 0)
23 #define TTB_S (1 << 1)
24 #define TTB_IMP (1 << 2)
26 #define TTB_RGN_WBWA (1 << 3)
41 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
59 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
61 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
78 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
82 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
[all …]
H A Dproc-arm740.S37 mrc p15, 0, r0, c1, c0, 0
40 mcr p15, 0, r0, c1, c0, 0 @ disable caches
51 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
52 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
54 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
62 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
71 mcr p15, 0, r0, c6, c0 @ set area 0, default
76 1: add r4, r4, #1 @ area size *= 2
77 movs r3, r3, lsr #1
78 bne 1b @ count not zero r-shift
[all …]
H A Dproc-xsc3.S56 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
68 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
70 bcc 1b
72 bpl 1b
89 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
92 mcr p15, 0, r0, c1, c0, 0 @ disable caches
109 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
112 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
136 mov r0, #1
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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/
H A Dg98.fuc0s51 .b32 #cmd_query_get + 0x00000 ~1
154 shl b32 $r5 $r4 1
165 mov $r4 1
173 shl b32 $r15 $r4 1
183 mov $r6 #dma_count - 1
189 sub b32 $r6 1
264 cmpu b32 $r6 1
276 or $r2 1
294 mov $r4 1
353 xor $r3 1
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/openbmc/phosphor-webui/app/common/directives/
H A Dvt100plus.js36 F1 key | <ESC>1
52 var modifiers = (ev.shiftKey ? 1 : 0) | (ev.altKey ? 2 : 0) |
62 term.handler(EscapeSequences.C0.BS); // Backspace
64 term.handler(EscapeSequences.C0.DEL); // Delete
68 term.handler(EscapeSequences.C0.ESC + '?');
71 term.handler(EscapeSequences.C0.ESC + '/');
74 term.handler(EscapeSequences.C0.ESC + 'k');
77 term.handler(EscapeSequences.C0.ESC + 'h');
80 term.handler(EscapeSequences.C0.ESC + '+');
83 term.handler(EscapeSequences.C0.ESC + '-');
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/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dstart.S84 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
86 cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT)
109 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register
111 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register
116 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
191 mrc p15, 0, r0, c1, c0, 0
194 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
201 mcr p15, 0, r0, c1, c0, 0
204 mrc p15, 0, r0, c1, c0, 0 @ read system control register
205 orr r0, r0, #1 << 11 @ set bit #11
[all …]
H A Dcache_v7_asm.S27 mrc p15, 1, r0, c0, c0, 1 @ read clidr
29 ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
34 add r2, r10, r10, lsr #1 @ work out 3x current cache level
39 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
41 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
59 subs r9, r9, #1 @ decrement the index
61 subs r4, r4, #1 @ decrement the way
69 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
98 mrc p15, 1, r0, c0, c0, 1 @ read clidr
100 ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
[all …]
H A Dpsci.S67 mov r0, #ARM_PSCI_RET_NI @ Return -1 (Not Implemented)
159 bic r4, r7, #1
164 1: ldr r5, [r4] @ Load PSCI function ID
171 bne 1b
183 mrc p15, 0, r0, c0, c0, 5 /* read MPIDR */
193 mrc p15, 1, r0, c0, c0, 1 @ read clidr
199 add r2, r10, r10, lsr #1 @ work out 3x current cache level
205 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
207 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
222 subs r9, r9, #1 @ decrement the index
[all …]
/openbmc/u-boot/board/keymile/kmp204x/
H A Dpbi.cfg10 091380c0 000009C4
12 091380c0 000009C4
14 091380c0 000009C4
17 091380c0 000009C4
19 091380c0 000009C4
21 091380c0 000009C4
23 091380c0 000009C4
25 091380c0 000009C4
27 091380c0 000009C4
29 091380c0 000009C4
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/openbmc/u-boot/arch/arm/mach-rmobile/
H A Dlowlevel_init_ca15.S14 mrc p15, 0, r4, c0, c0, 5 /* mpidr */
16 and r4, r4, #7 /* id 0-3 = ca15.0,1,2,3 */
23 * CPU ID #1-#3 come here
28 1: ldr r0, [r1, #0x20] /* sbar */
30 beq 1b
47 mrceq p15, 0, r0, c1, c0, 1 /* actlr */
48 orreq r0, r0, #(1<<7)
49 mcreq p15, 0, r0, c1, c0, 1
52 mrc p15, 0, r0, c0, c0, 5 /* r0 = MPIDR */
55 tst r0, #1 /* only need for cluster 0 */
[all …]
/openbmc/linux/arch/arm/include/debug/
H A Dicedcc.S16 mcr p14, 0, \rd, c0, c5, 0
21 mrc p14, 0, \rx, c0, c1, 0
32 subs \rd, \rd, #1
34 mrc p14, 0, \rx, c0, c1, 0
43 mcr p14, 0, \rd, c8, c0, 0
48 mrc p14, 0, \rx, c14, c0, 0
59 subs \rd, \rd, #1
61 mrc p14, 0, \rx, c14, c0, 0
70 mcr p14, 0, \rd, c1, c0, 0
75 mrc p14, 0, \rx, c0, c0, 0
[all …]
/openbmc/linux/arch/arm/kernel/
H A Dhyp-stub.S116 mcr p15, 4, r7, c12, c0, 0 @ set hypervisor vector base (HVBAR)
124 THUMB( orr r7, #(1 << 30) ) @ HSCTLR.TE
125 ARM_BE8(orr r7, r7, #(1 << 25)) @ HSCTLR.EE
126 mcr p15, 4, r7, c1, c0, 0 @ HSCTLR
128 mrc p15, 4, r7, c1, c1, 1 @ HDCR
130 mcr p15, 4, r7, c1, c1, 1 @ HDCR
133 mrc p15, 0, r7, c1, c0, 0 @ SCTLR
134 orr r7, #(1 << 5) @ CP15 barriers enabled
137 mcr p15, 0, r7, c1, c0, 0 @ SCTLR
139 mrc p15, 0, r7, c0, c0, 0 @ MIDR
[all …]
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Dsystem.h37 #define USB20_PHY_CFG_HOST_LINK_EN (1 << 0)
71 ("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(x) : )
75 ("mrc p15, 0, %0, c0, c0, 5\n\t" : "=r"(x) : )
79 ("mrc p15, 0, %0, c1, c0, 0\n\t" : "=r"(x) : )
83 ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(x) : )
87 ("mrc p15, 1, %0, c9, c0, 2\n\t" : "=r"(x) : )
91 ("mrc p15, 1, %0, c15, c0, 0\n\t" : "=r"(x) : )
95 ("mcr p15, 0, %0, c1, c0, 0\n\t" : : "r"(x))
99 ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(x))
111 ("mcr p15, 1, %0, c9, c0, 2\n\t" : : "r"(x))
[all …]
/openbmc/linux/arch/arm/boot/compressed/
H A Dhead.S38 mcr p14, 0, \ch, c0, c5, 0
44 mcr p14, 0, \ch, c8, c0, 0
50 mcr p14, 0, \ch, c1, c0, 0
141 mrc p15, 0, \reg, c1, c0, 0 @ read SCTLR
142 tst \reg, #(1 << 5) @ CP15BEN bit set?
144 orr \reg, \reg, #(1 << 5) @ CP15 barrier instructions
145 mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR
162 ldrb \tmp2, [\tmp1, #1]
191 * These 7 nops along with the 1 nop immediately below for
213 W(b) 1f
[all …]
/openbmc/linux/arch/s390/crypto/
H A Dchacha-s390.S21 .long 1,0,0,0
26 .long 0,1,2,3
100 VREPF XB1,K1,1
105 VREPF XD1,K3,1
111 VREPF XC1,K2,1
402 la %r1,1(%r1)
442 #define C0 %v2 macro
508 VAF D1,K3,T1 # K[3]+1
514 VLR C0,K2
545 VAF C0,C0,D0
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dsleep44xx.S47 * 1 - CPUx L1 and logic lost: MPUSS CSWR
88 mrc p15, 0, r0, c1, c0, 0
89 bic r0, r0, #(1 << 2) @ Disable the C bit
90 mcr p15, 0, r0, c1, c0, 0
108 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
119 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
127 tst r0, #(1 << 18)
128 mrcne p15, 0, r0, c1, c0, 1
129 bicne r0, r0, #(1 << 6) @ Disable SMP bit
130 mcrne p15, 0, r0, c1, c0, 1
[all …]
/openbmc/linux/arch/arm/mach-sunxi/
H A Dheadsmp.S25 mrc p15, 0, r1, c0, c0, 0
37 mrc p15, 1, r1, c15, c0, 4
39 mcr p15, 1, r1, c15, c0, 4
42 mrc p15, 1, r1, c15, c0, 0
47 mcr p15, 1, r1, c15, c0, 0
50 mrc p15, 1, r1, c9, c0, 2
53 mcr p15, 1, r1, c9, c0, 2
/openbmc/linux/tools/testing/selftests/net/forwarding/
H A Dbridge_igmp.sh17 MZPKT_IS_INC="22:00:9d:de:00:00:00:01:01:00:00:03:ef:0a:0a:0a:c0:00:02:01:c0:00:02:02:c0:00:02:03"
19 MZPKT_IS_INC2="22:00:9d:c3:00:00:00:01:01:00:00:03:ef:0a:0a:0a:c0:00:02:0a:c0:00:02:0b:c0:00:02:0c"
21 MZPKT_IS_INC3="22:00:5f:b4:00:00:00:01:01:00:00:02:ef:0a:0a:0a:c0:00:02:14:c0:00:02:1e"
23 MZPKT_ALLOW="22:00:99:c3:00:00:00:01:05:00:00:03:ef:0a:0a:0a:c0:00:02:0a:c0:00:02:0b:c0:00:02:0c"
25 MZPKT_ALLOW2="22:00:5b:b4:00:00:00:01:05:00:00:02:ef:0a:0a:0a:c0:00:02:14:c0:00:02:1e"
27 …_IS_EXC="22:00:da:b6:00:00:00:01:02:00:00:04:ef:0a:0a:0a:c0:00:02:01:c0:00:02:02:c0:00:02:14:c0:00…
29 MZPKT_IS_EXC2="22:00:5e:b4:00:00:00:01:02:00:00:02:ef:0a:0a:0a:c0:00:02:14:c0:00:02:1e"
31 MZPKT_TO_EXC="22:00:9a:b1:00:00:00:01:04:00:00:03:ef:0a:0a:0a:c0:00:02:01:c0:00:02:14:c0:00:02:1e"
33 MZPKT_BLOCK="22:00:98:b1:00:00:00:01:06:00:00:03:ef:0a:0a:0a:c0:00:02:01:c0:00:02:14:c0:00:02:1e"
39 simple_if_init $h1 192.0.2.1/24 2001:db8:1::1/64
[all …]
/openbmc/linux/arch/arm/mach-spear/
H A Dhotplug.c23 " mcr p15, 0, %1, c7, c5, 0\n" in cpu_enter_lowpower()
28 " mrc p15, 0, %0, c1, c0, 1\n" in cpu_enter_lowpower()
30 " mcr p15, 0, %0, c1, c0, 1\n" in cpu_enter_lowpower()
31 " mrc p15, 0, %0, c1, c0, 0\n" in cpu_enter_lowpower()
33 " mcr p15, 0, %0, c1, c0, 0\n" in cpu_enter_lowpower()
43 asm volatile("mrc p15, 0, %0, c1, c0, 0\n" in cpu_leave_lowpower()
44 " orr %0, %0, %1\n" in cpu_leave_lowpower()
45 " mcr p15, 0, %0, c1, c0, 0\n" in cpu_leave_lowpower()
46 " mrc p15, 0, %0, c1, c0, 1\n" in cpu_leave_lowpower()
48 " mcr p15, 0, %0, c1, c0, 1\n" in cpu_leave_lowpower()
/openbmc/linux/arch/arm/mach-versatile/
H A Dhotplug.c25 "mcr p15, 0, %1, c7, c5, 0\n" in versatile_immitation_enter_lowpower()
26 " mcr p15, 0, %1, c7, c10, 4\n" in versatile_immitation_enter_lowpower()
30 " mrc p15, 0, %0, c1, c0, 1\n" in versatile_immitation_enter_lowpower()
32 " mcr p15, 0, %0, c1, c0, 1\n" in versatile_immitation_enter_lowpower()
33 " mrc p15, 0, %0, c1, c0, 0\n" in versatile_immitation_enter_lowpower()
35 " mcr p15, 0, %0, c1, c0, 0\n" in versatile_immitation_enter_lowpower()
46 "mrc p15, 0, %0, c1, c0, 0\n" in versatile_immitation_leave_lowpower()
47 " orr %0, %0, %1\n" in versatile_immitation_leave_lowpower()
48 " mcr p15, 0, %0, c1, c0, 0\n" in versatile_immitation_leave_lowpower()
49 " mrc p15, 0, %0, c1, c0, 1\n" in versatile_immitation_leave_lowpower()
[all …]

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