| /openbmc/linux/drivers/pinctrl/mvebu/ |
| H A D | pinctrl-kirkwood.c | 19 #define V(f6180, f6190, f6192, f6281, f6282, dx4122, dx1135) \ macro
20 ((f6180 << 0) | (f6190 << 1) | (f6192 << 2) | \
25 VARIANT_MV88F6180 = V(1, 0, 0, 0, 0, 0, 0),
26 VARIANT_MV88F6190 = V(0, 1, 0, 0, 0, 0, 0),
27 VARIANT_MV88F6192 = V(0, 0, 1, 0, 0, 0, 0),
28 VARIANT_MV88F6281 = V(0, 0, 0, 1, 0, 0, 0),
29 VARIANT_MV88F6282 = V(0, 0, 0, 0, 1, 0, 0),
30 VARIANT_MV98DX4122 = V(0, 0, 0, 0, 0, 1, 0),
31 VARIANT_MV98DX1135 = V(0, 0, 0, 0, 0, 0, 1),
36 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1, 1)),
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | display_mode_vba_30.c | 397 struct vba_vars_st *v,
676 // valid bpp = increments of 1/16 of a bit in dscceComputeDelay()
678 // max = such that compression is 1:1 in dscceComputeDelay()
680 …mSlices = number of slices in the horiziontal direction per DSC engine in the set of {1, 2, 3, 4} in dscceComputeDelay()
692 // #all other modes operate at 1 pixel per clock in dscceComputeDelay()
694 pixelsPerClock = 1; in dscceComputeDelay()
698 pixelsPerClock = 1; in dscceComputeDelay()
718 s = 1; in dscceComputeDelay()
726 ax = (a + 2) / 3 + D + 6 + 1; in dscceComputeDelay()
727 L = (ax + wx - 1) / wx; in dscceComputeDelay()
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| /openbmc/linux/arch/x86/lib/ |
| H A D | atomic64_386_32.S | 27 IRQ_SAVE v;
32 IRQ_RESTORE v; \
35 #define v %ecx macro
37 movl (v), %eax
38 movl 4(v), %edx
41 #undef v
43 #define v %esi macro
45 movl %ebx, (v)
46 movl %ecx, 4(v)
49 #undef v
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| /openbmc/linux/tools/memory-model/ |
| H A D | linux-kernel.def | 10 WRITE_ONCE(X,V) { __store{once}(X,V); }
13 smp_store_release(X,V) { __store{release}(*X,V); }
15 rcu_assign_pointer(X,V) { __store{release}(X,V); }
17 smp_store_mb(X,V) { __store{once}(X,V); __fence{mb}; }
31 xchg(X,V) __xchg{mb}(X,V)
32 xchg_relaxed(X,V) __xchg{once}(X,V)
33 xchg_release(X,V) __xchg{release}(X,V)
34 xchg_acquire(X,V) __xchg{acquire}(X,V)
35 cmpxchg(X,V,W) __cmpxchg{mb}(X,V,W)
36 cmpxchg_relaxed(X,V,W) __cmpxchg{once}(X,V,W)
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| H A D | dcn_calc_auto.c | 40 void scaler_settings_calculation(struct dcn_bw_internal_vars *v) in scaler_settings_calculation() argument
43 for (k = 0; k <= v->number_of_active_planes - 1; k++) { in scaler_settings_calculation()
44 if (v->allow_different_hratio_vratio == dcn_bw_yes) { in scaler_settings_calculation()
45 if (v->source_scan[k] == dcn_bw_hor) { in scaler_settings_calculation()
46 v->h_ratio[k] = v->viewport_width[k] / v->scaler_rec_out_width[k]; in scaler_settings_calculation()
47 v->v_ratio[k] = v->viewport_height[k] / v->scaler_recout_height[k]; in scaler_settings_calculation()
50 v->h_ratio[k] = v->viewport_height[k] / v->scaler_rec_out_width[k]; in scaler_settings_calculation()
51 v->v_ratio[k] = v->viewport_width[k] / v->scaler_recout_height[k]; in scaler_settings_calculation()
55 if (v->source_scan[k] == dcn_bw_hor) { in scaler_settings_calculation()
56 …v->h_ratio[k] =dcn_bw_max2(v->viewport_width[k] / v->scaler_rec_out_width[k], v->viewport_height[k… in scaler_settings_calculation()
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| /openbmc/u-boot/arch/arm/include/asm/arch-vf610/ |
| H A D | imx-regs.h | 93 /* AIPS 1 */
113 #define MSCM_IRSPRC_CP0_EN 1
125 #define DDRMC_PHY50_DDR3_MODE (1 << 12)
126 #define DDRMC_PHY50_EN_SW_HALF_CYCLE (1 << 8)
130 #define DDRMC_CR00_START 1
131 #define DDRMC_CR02_DRAM_TINIT(v) ((v) & 0xffffff) argument
132 #define DDRMC_CR10_TRST_PWRON(v) (v) argument
133 #define DDRMC_CR11_CKE_INACTIVE(v) (v) argument
134 #define DDRMC_CR12_WRLAT(v) (((v) & 0x1f) << 8) argument
135 #define DDRMC_CR12_CASLAT_LIN(v) ((v) & 0x3f) argument
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | display_mode_vba_314.c | 57 // Delay in DCFCLK from ARB to DET (1st num is ARB to SDPIF, 2nd number is SDPIF to DET)
700 // valid bpp = increments of 1/16 of a bit in dscceComputeDelay()
702 // max = such that compression is 1:1 in dscceComputeDelay()
704 …mSlices = number of slices in the horiziontal direction per DSC engine in the set of {1, 2, 3, 4} in dscceComputeDelay()
716 pixelsPerClock = 1; in dscceComputeDelay()
719 // #all other modes operate at 1 pixel per clock in dscceComputeDelay()
721 pixelsPerClock = 1; in dscceComputeDelay()
741 s = 1; in dscceComputeDelay()
749 ax = (a + 2) / 3 + D + 6 + 1; in dscceComputeDelay()
750 L = (ax + wx - 1) / wx; in dscceComputeDelay()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | display_mode_vba_31.c | 56 // Delay in DCFCLK from ARB to DET (1st num is ARB to SDPIF, 2nd number is SDPIF to DET)
679 // valid bpp = increments of 1/16 of a bit in dscceComputeDelay()
681 // max = such that compression is 1:1 in dscceComputeDelay()
683 …mSlices = number of slices in the horiziontal direction per DSC engine in the set of {1, 2, 3, 4} in dscceComputeDelay()
695 pixelsPerClock = 1; in dscceComputeDelay()
698 // #all other modes operate at 1 pixel per clock in dscceComputeDelay()
700 pixelsPerClock = 1; in dscceComputeDelay()
720 s = 1; in dscceComputeDelay()
728 ax = (a + 2) / 3 + D + 6 + 1; in dscceComputeDelay()
729 L = (ax + wx - 1) / wx; in dscceComputeDelay()
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| /openbmc/linux/drivers/gpu/drm/exynos/ |
| H A D | regs-scaler.h | 56 * 1 70 74 78 7c 150 154 158 15c
61 * 6 c0 c4 c8 cc 1a0 1a4 1a8 1ac
62 * 7 d0 d4 d8 dc 1b0 1b4 1b8 1bc
63 * 8 e0 e4 e8 ec 1c0 1c4 1c8 1cc
69 * 0 f0 f4 1d0 1d4
70 * 1 f8 fc 1d8 1dc
71 * 2 100 104 1e0 1e4
72 * 3 108 10c 1e8 1ec
73 * 4 110 114 1f0 1f4
74 * 5 118 11c 1f8 1fc
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| /openbmc/u-boot/drivers/mtd/nand/raw/ |
| H A D | nand_ids.c | 28 LEGACY_ID_NAND("NAND 1MiB 5V 8-bit", 0x6e, 1, SZ_4K, SP_OPTIONS),
29 LEGACY_ID_NAND("NAND 2MiB 5V 8-bit", 0x64, 2, SZ_4K, SP_OPTIONS),
30 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xe8, 1, SZ_4K, SP_OPTIONS),
31 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xec, 1, SZ_4K, SP_OPTIONS),
32 LEGACY_ID_NAND("NAND 2MiB 3,3V 8-bit", 0xea, 2, SZ_4K, SP_OPTIONS),
33 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS),
35 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xe6, 8, SZ_8K, SP_OPTIONS),
42 {"TC58NVG0S3E 1G 3.3V 8-bit",
44 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512),
46 {"TC58NVG2S0F 4G 3.3V 8-bit",
[all …]
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| /openbmc/linux/drivers/media/platform/verisilicon/ |
| H A D | rockchip_vpu2_hw_mpeg2_dec.c | 23 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
25 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
26 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
27 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
28 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
30 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
31 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
33 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
34 #define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) argument
35 #define VDPU_REG_STARTMB_Y(v) (((v) << 0) & GENMASK(7, 0)) argument
[all …]
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| H A D | hantro_g1_mpeg2_dec.c | 25 #define G1_REG_DEC_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24)) argument
26 #define G1_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(23) : 0) argument
27 #define G1_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(22) : 0) argument
28 #define G1_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(21) : 0) argument
29 #define G1_REG_DEC_INSWAP32_E(v) ((v) ? BIT(20) : 0) argument
30 #define G1_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(19) : 0) argument
31 #define G1_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(18) : 0) argument
32 #define G1_REG_DEC_LATENCY(v) (((v) << 11) & GENMASK(16, 11)) argument
33 #define G1_REG_DEC_CLK_GATE_E(v) ((v) ? BIT(10) : 0) argument
34 #define G1_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(9) : 0) argument
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| /openbmc/linux/arch/sh/mm/ |
| H A D | flush-sh4.c | 16 reg_size_t aligned_start, v, cnt, end; in sh4__flush_wback_region() local
19 v = aligned_start & ~(L1_CACHE_BYTES-1); in sh4__flush_wback_region()
20 end = (aligned_start + size + L1_CACHE_BYTES-1) in sh4__flush_wback_region()
21 & ~(L1_CACHE_BYTES-1); in sh4__flush_wback_region()
22 cnt = (end - v) / L1_CACHE_BYTES; in sh4__flush_wback_region()
25 __ocbwb(v); v += L1_CACHE_BYTES; in sh4__flush_wback_region()
26 __ocbwb(v); v += L1_CACHE_BYTES; in sh4__flush_wback_region()
27 __ocbwb(v); v += L1_CACHE_BYTES; in sh4__flush_wback_region()
28 __ocbwb(v); v += L1_CACHE_BYTES; in sh4__flush_wback_region()
29 __ocbwb(v); v += L1_CACHE_BYTES; in sh4__flush_wback_region()
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| /openbmc/linux/tools/testing/selftests/kvm/aarch64/ |
| H A D | vgic_init.c | 64 GUEST_SYNC(1); in guest_code()
79 struct vm_gic v; in vm_gic_create_with_vcpus() local
81 v.gic_dev_type = gic_dev_type; in vm_gic_create_with_vcpus()
82 v.vm = vm_create_with_vcpus(nr_vcpus, guest_code, vcpus); in vm_gic_create_with_vcpus()
83 v.gic_fd = kvm_create_device(v.vm, gic_dev_type); in vm_gic_create_with_vcpus()
85 return v; in vm_gic_create_with_vcpus()
90 struct vm_gic v; in vm_gic_create_barebones() local
92 v.gic_dev_type = gic_dev_type; in vm_gic_create_barebones()
93 v.vm = vm_create_barebones(); in vm_gic_create_barebones()
94 v.gic_fd = kvm_create_device(v.vm, gic_dev_type); in vm_gic_create_barebones()
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| /openbmc/linux/drivers/md/ |
| H A D | dm-verity-target.c | 53 struct dm_verity *v; member
63 * it can be changed to 1 and it is never reset to 0 again.
67 * and write 1 to hash_verified simultaneously.
87 static sector_t verity_map_sector(struct dm_verity *v, sector_t bi_sector) in verity_map_sector() argument
89 return v->data_start + dm_target_offset(v->ti, bi_sector); in verity_map_sector()
98 static sector_t verity_position_at_level(struct dm_verity *v, sector_t block, in verity_position_at_level() argument
101 return block >> (level * v->hash_per_block_bits); in verity_position_at_level()
104 static int verity_hash_update(struct dm_verity *v, struct ahash_request *req, in verity_hash_update() argument
121 sg_init_table(&sg, 1); in verity_hash_update()
137 static int verity_hash_init(struct dm_verity *v, struct ahash_request *req, in verity_hash_init() argument
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| /openbmc/entity-manager/test/ |
| H A D | test_entity-manager.cpp | 79 nlohmann::json j = {{"foo", "3 plus 1 equals $TEST + 1"}}; in TEST()
86 nlohmann::json expected = "3 plus 1 equals 4"; in TEST()
92 nlohmann::json j = {{"foo", "3 minus 1 equals $TEST - 1 !"}}; in TEST()
99 nlohmann::json expected = "3 minus 1 equals 2 !"; in TEST()
112 nlohmann::json expected = "3 mod 2 equals 1"; in TEST()
245 DBusValueVariant v = "foo"s; in TEST() local
246 EXPECT_TRUE(matchProbe(j, v)); in TEST()
252 DBusValueVariant v = "foobar"s; in TEST() local
253 EXPECT_TRUE(matchProbe(j, v)); in TEST()
259 DBusValueVariant v = "foo"s; in TEST() local
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| /openbmc/linux/sound/soc/qcom/ |
| H A D | lpass-lpaif-reg.h | 11 #define LPAIF_I2SCTL_REG_ADDR(v, addr, port) \ argument
12 (v->i2sctrl_reg_base + (addr) + v->i2sctrl_reg_stride * (port))
14 #define LPAIF_I2SCTL_REG(v, port) LPAIF_I2SCTL_REG_ADDR(v, 0x0, (port)) argument
17 #define LPAIF_I2SCTL_LOOPBACK_ENABLE 1
20 #define LPAIF_I2SCTL_SPKEN_ENABLE 1
23 #define LPAIF_I2SCTL_MODE_SD0 1
46 #define LPAIF_I2SCTL_SPKMONO_MONO 1
49 #define LPAIF_I2SCTL_MICEN_ENABLE 1
54 #define LPAIF_I2SCTL_MICMONO_MONO 1
57 #define LPAIF_I2SCTL_WSSRC_EXTERNAL 1
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| /openbmc/linux/drivers/mtd/nand/raw/ |
| H A D | nand_ids.c | 29 {"TC58NVG0S3E 1G 3.3V 8-bit",
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
41 {"TC58NVG5D2 32G 3.3V 8-bit",
44 {"TC58NVG6D2 64G 3.3V 8-bit",
47 {"SDTNQGAMA 64G 3.3V 8-bit",
50 {"SDTNRGAMA 64G 3.3V 8-bit",
53 {"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
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| /openbmc/linux/arch/powerpc/include/asm/ |
| H A D | atomic.h | 27 static __inline__ int arch_atomic_read(const atomic_t *v) in arch_atomic_read() argument
33 __asm__ __volatile__("lwz %0,0(%1)" : "=r"(t) : "b"(&v->counter)); in arch_atomic_read()
35 __asm__ __volatile__("lwz%U1%X1 %0,%1" : "=r"(t) : "m<>"(v->counter)); in arch_atomic_read()
40 static __inline__ void arch_atomic_set(atomic_t *v, int i) in arch_atomic_set() argument
44 __asm__ __volatile__("stw %1,0(%2)" : "=m"(v->counter) : "r"(i), "b"(&v->counter)); in arch_atomic_set()
46 __asm__ __volatile__("stw%U0%X0 %1,%0" : "=m<>"(v->counter) : "r"(i)); in arch_atomic_set()
50 static __inline__ void arch_atomic_##op(int a, atomic_t *v) \
55 "1: lwarx %0,0,%3 # atomic_" #op "\n" \
58 " bne- 1b\n" \
59 : "=&r" (t), "+m" (v->counter) \
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| /openbmc/linux/crypto/ |
| H A D | aegis128-neon-inner.c | 26 uint8x16_t v[5]; member
44 vst1q_u8(state, st.v[0]); in aegis128_save_state_neon()
45 vst1q_u8(state + 16, st.v[1]); in aegis128_save_state_neon()
46 vst1q_u8(state + 32, st.v[2]); in aegis128_save_state_neon()
47 vst1q_u8(state + 48, st.v[3]); in aegis128_save_state_neon()
48 vst1q_u8(state + 64, st.v[4]); in aegis128_save_state_neon()
57 if (!__builtin_expect(aegis128_have_aes_insn, 1)) { in aegis_aes_round()
66 uint8x16_t v; in aegis_aes_round() local
73 v = vqtbl4q_u8(vld1q_u8_x4(crypto_aes_sbox), w); in aegis_aes_round()
74 v = vqtbx4q_u8(v, vld1q_u8_x4(crypto_aes_sbox + 0x40), w - 0x40); in aegis_aes_round()
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| /openbmc/linux/drivers/media/dvb-frontends/ |
| H A D | mb86a16.c | 39 #define MB86A16_NOTICE 1
59 #define TRACE_IN dprintk(verbose, MB86A16_DEBUG, 1, "-->()")
60 #define TRACE_OUT dprintk(verbose, MB86A16_DEBUG, 1, "()-->")
74 dprintk(verbose, MB86A16_DEBUG, 1, in mb86a16_write()
76 state->config->demod_address, buf[0], buf[1]); in mb86a16_write()
78 ret = i2c_transfer(state->i2c_adap, &msg, 1); in mb86a16_write()
80 return (ret != 1) ? -EREMOTEIO : 0; in mb86a16_write()
94 .len = 1 in mb86a16_read()
99 .len = 1 in mb86a16_read()
104 dprintk(verbose, MB86A16_ERROR, 1, "read error(reg=0x%02x, ret=%i)", in mb86a16_read()
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| /openbmc/u-boot/drivers/usb/host/ |
| H A D | ehci-mx5.c | 35 #define MXC_OTG_UCTRL_OWIE_BIT (1 << 27)
37 #define MXC_OTG_UCTRL_OPM_BIT (1 << 24)
39 #define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24)
41 #define MXC_H1_UCTRL_H1UIE_BIT (1 << 12)
43 #define MXC_H1_UCTRL_H1WIE_BIT (1 << 11)
45 #define MXC_H1_UCTRL_H1PM_BIT (1 << 8)
47 #define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8)
51 #define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9)
53 #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8)
55 #define MXC_H1_OC_POL_BIT (1 << 6)
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| H A D | ehci-mxc.c | 20 #define MX25_OTG_PM_BIT (1 << 24)
21 #define MX25_OTG_PP_BIT (1 << 11)
22 #define MX25_OTG_OCPOL_BIT (1 << 3)
26 #define MX25_H1_PP_BIT (1 << 18)
27 #define MX25_H1_PM_BIT (1 << 16)
28 #define MX25_H1_IPPUE_UP_BIT (1 << 7)
29 #define MX25_H1_IPPUE_DOWN_BIT (1 << 6)
30 #define MX25_H1_TLL_BIT (1 << 5)
31 #define MX25_H1_USBTE_BIT (1 << 4)
32 #define MX25_H1_OCPOL_BIT (1 << 2)
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| /openbmc/linux/Documentation/hwmon/ |
| H A D | dme1737.rst | 64 temp[1-3] (2 remote diodes and 1 internal), 8 voltages in[0-7] (7 external and
65 1 internal) and up to 6 fan speeds fan[1-6]. Additionally, the chips implement
66 up to 5 PWM outputs pwm[1-3,5-6] for controlling fan speeds both manually and
69 For the DME1737, A8000 and SCH5027, fan[1-2] and pwm[1-2] are always present.
74 For the SCH311x and SCH5127, fan[1-3] and pwm[1-3] are always present and
94 in0: +5VTR (+5V standby) 0V - 6.64V
95 in1: Vccp (processor core) 0V - 3V
96 in2: VCC (internal +3.3V) 0V - 4.38V
97 in3: +5V 0V - 6.64V
98 in4: +12V 0V - 16V
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| /openbmc/qemu/tests/unit/ |
| H A D | test-string-input-visitor.c | 20 Visitor *v; member
26 if (data->v) { in visitor_input_teardown()
27 visit_free(data->v); in visitor_input_teardown()
28 data->v = NULL; in visitor_input_teardown()
41 data->v = string_input_visitor_new(string); in visitor_input_test_init()
42 g_assert(data->v); in visitor_input_test_init()
43 return data->v; in visitor_input_test_init()
51 Visitor *v; in test_visitor_in_int() local
53 v = visitor_input_test_init(data, "-42"); in test_visitor_in_int()
55 visit_type_int(v, NULL, &res, &error_abort); in test_visitor_in_int()
[all …]
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