Home
last modified time | relevance | path

Searched +full:100 +full:khz (Results 1 – 25 of 833) sorted by relevance

12345678910>>...34

/openbmc/linux/Documentation/fb/
H A Dviafb.modes14 # Scan Frequency 31.469 kHz 59.94 Hz
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
39 # Scan Frequency 37.500 kHz 75.00 Hz
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
60 # Scan Frequency 43.269 kHz 85.00 Hz
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
81 # Scan Frequency 50.900 kHz 100.00 Hz
94 mode "640x480-100"
[all …]
/openbmc/linux/drivers/cpufreq/
H A Dpowernow-k6.c26 static unsigned int busfreq; /* FSB, in 10 kHz */
36 MODULE_PARM_DESC(bus_frequency, "Bus frequency in kHz");
47 {0, 20, /* 100 -> 2.0x */ 0},
58 { 350000, 35 }, // 100 * 3.5
59 { 400000, 40 }, // 100 * 4
60 { 450000, 45 }, // 100 * 4.5
62 { 500000, 50 }, // 100 * 5
65 { 550000, 55 }, // 100 * 5.5
68 { 600000, 60 }, // 100 * 6
157 unsigned khz; in powernow_k6_cpu_init() local
[all …]
H A Dlongrun.c21 * longrun_{low,high}_freq is needed for the conversion of cpufreq kHz
56 ((longrun_high_freq - longrun_low_freq) / 100); in longrun_get_policy()
58 ((longrun_high_freq - longrun_low_freq) / 100); in longrun_get_policy()
81 pctg_lo = pctg_hi = 100; in longrun_set_policy()
84 ((longrun_high_freq - longrun_low_freq) / 100); in longrun_set_policy()
86 ((longrun_high_freq - longrun_low_freq) / 100); in longrun_set_policy()
89 if (pctg_hi > 100) in longrun_set_policy()
90 pctg_hi = 100; in longrun_set_policy()
183 *low_freq = msr_lo * 1000; /* to kHz */ in longrun_determine_freqs()
188 *high_freq = msr_lo * 1000; /* to kHz */ in longrun_determine_freqs()
[all …]
H A Dgx-suspmod.c89 #define PCI_VIDTC 0x8d /* video speedup timer counter register: typical 50 to 100ms */
132 * though. 781.25 kHz(!) for a 200 MHz processor -- wow. */
217 static unsigned int gx_validate_speed(unsigned int khz, u8 *on_duration, in gx_validate_speed() argument
229 tmp_off = ((khz * i) / stock_freq) & 0xff; in gx_validate_speed()
232 /* if this relation is closer to khz, use this. If it's equal, in gx_validate_speed()
234 if (abs(tmp_freq - khz) <= abs(old_tmp_freq - khz)) { in gx_validate_speed()
247 * set cpu speed in khz.
250 static void gx_set_cpuspeed(struct cpufreq_policy *policy, unsigned int khz) in gx_set_cpuspeed() argument
259 new_khz = gx_validate_speed(khz, &gx_params->on_duration, in gx_set_cpuspeed()
268 /* if new khz == 100% of CPU speed, it is special case */ in gx_set_cpuspeed()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3399.h70 #define KHz 1000 macro
82 #define PCLK_DBG_L_HZ (100*MHz)
86 #define PCLK_DBG_B_HZ (100*MHz)
88 #define PERIHP_ACLK_HZ (148500*KHz)
89 #define PERIHP_HCLK_HZ (148500*KHz)
90 #define PERIHP_PCLK_HZ (37125*KHz)
92 #define PERILP0_ACLK_HZ (99000*KHz)
93 #define PERILP0_HCLK_HZ (99000*KHz)
94 #define PERILP0_PCLK_HZ (49500*KHz)
96 #define PERILP1_HCLK_HZ (99000*KHz)
[all …]
/openbmc/u-boot/drivers/i2c/
H A Daspeed_i2c_global.c27 * APB clk : 100Mhz
30 * I2CG10[23:16] base clk3 for Standard-mode (100Khz) min tBuf 4.7us
31 * 0x3c : 100.8Khz : 3.225Mhz : 4.96us
32 * 0x3d : 99.2Khz : 3.174Mhz : 5.04us
33 * 0x3e : 97.65Khz : 3.125Mhz : 5.12us
34 * 0x40 : 97.75Khz : 3.03Mhz : 5.28us
35 * 0x41 : 99.5Khz : 2.98Mhz : 5.36us (default)
36 * I2CG10[15:8] base clk2 for Fast-mode (400Khz) min tBuf 1.3us
37 * 0x12 : 400Khz : 10Mhz : 1.6us
/openbmc/u-boot/arch/m68k/cpu/mcf532x/
H A Dspeed.c20 #define MAX_FVCO 500000 /* KHz */
21 #define MAX_FSYS 80000 /* KHz */
22 #define MIN_FSYS 58333 /* KHz */
25 #define FREF 20000 /* KHz */
37 #define FREF 16000 /* KHz */
131 * fref PLL reference clock frequency in KHz
132 * fsys Desired PLL output frequency in KHz
173 * Multiplying by 100 when calculating the temp value, in clock_pll()
174 * and then dividing by 100 to calculate the mfd allows in clock_pll()
178 temp = (100 * fsys) / fref; in clock_pll()
[all …]
/openbmc/linux/drivers/video/fbdev/core/
H A Dmodedb.c38 /* 640x400 @ 70 Hz, 31.5 kHz hsync */
42 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
46 /* 800x600 @ 56 Hz, 35.15 kHz hsync */
50 /* 1024x768 @ 87 Hz interlaced, 35.5 kHz hsync */
54 /* 640x400 @ 85 Hz, 37.86 kHz hsync */
58 /* 640x480 @ 72 Hz, 36.5 kHz hsync */
62 /* 640x480 @ 75 Hz, 37.50 kHz hsync */
66 /* 800x600 @ 60 Hz, 37.8 kHz hsync */
71 /* 640x480 @ 85 Hz, 43.27 kHz hsync */
75 /* 1152x864 @ 89 Hz interlaced, 44 kHz hsync */
[all …]
/openbmc/linux/Documentation/i2c/busses/
H A Di2c-ismt.rst21 Specify the bus speed in kHz.
27 80 kHz
28 100 kHz
29 400 kHz
30 1000 kHz
/openbmc/linux/drivers/gpu/drm/amd/display/include/
H A Dgrph_object_ctrl_defs.h128 uint32_t pixel_clk; /* in KHz */
160 uint32_t crystal_frequency; /* in KHz */
161 uint32_t min_input_pxl_clk_pll_frequency; /* in KHz */
162 uint32_t max_input_pxl_clk_pll_frequency; /* in KHz */
163 uint32_t min_output_pxl_clk_pll_frequency; /* in KHz */
164 uint32_t max_output_pxl_clk_pll_frequency; /* in KHz */
172 uint32_t default_display_engine_pll_frequency; /* in KHz */
173 uint32_t external_clock_source_frequency_for_dp; /* in KHz */
174 uint32_t smu_gpu_pll_output_freq; /* in KHz */
177 uint32_t default_memory_clk; /* in KHz */
[all …]
/openbmc/linux/drivers/comedi/drivers/
H A Ddt2811.c74 #define DT2811_OSC_BASE 1666 /* 600 kHz = 1666.6667ns */
80 * 0 1 600 kHz 0 1
81 * 1 10 60 kHz 1 10
82 * 2 2 300 kHz 2 100
83 * 3 3 200 kHz 3 1000
84 * 4 4 150 kHz 4 10000
85 * 5 5 120 kHz 5 100000
86 * 6 6 100 kHz 6 1000000
87 * 7 12 50 kHz 7 10000000
94 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000
[all …]
/openbmc/linux/drivers/nvmem/
H A Dlpc18xx_eeprom.c38 /* EEPROM device requires a ~1500 kHz clock (min 800 kHz, max 1600 kHz) */
109 /* Wait 100 us while the EEPROM wakes up */ in lpc18xx_eeprom_gather_write()
110 usleep_range(100, 200); in lpc18xx_eeprom_gather_write()
137 /* Wait 100 us while the EEPROM wakes up */ in lpc18xx_eeprom_read()
138 usleep_range(100, 200); in lpc18xx_eeprom_read()
/openbmc/linux/drivers/devfreq/
H A Dtegra30-devfreq.c68 #define KHZ 1000 macro
70 #define KHZ_MAX (ULONG_MAX / KHZ)
94 * Threshold of activity (cycles translated to kHz) below which the
125 .avg_dependency_threshold = 16000, /* 16MHz in kHz units */
147 .avg_dependency_threshold = 16000, /* 16MHz in kHz units */
154 * Frequencies are in kHz.
242 do_div(val, 100); in do_percent()
254 u32 avg_band_freq = tegra->max_freq * ACTMON_DEFAULT_AVG_BAND / KHZ; in tegra_devfreq_update_avg_wmark()
348 avg_sustain_coef = 100 * 100 / dev->config->boost_up_threshold; in actmon_device_target_freq()
412 tegra->cur_freq = data->new_rate / KHZ; in tegra_actmon_clk_notify_cb()
[all …]
/openbmc/linux/Documentation/hwmon/
H A Dmcp3021.rst36 compatible interface. Standard (100 kHz) and Fast (400 kHz) I2C modes are
H A Dlm85.rst153 driven by a 22.5 kHz clock. This is a global mode, not per-PWM output,
154 which means that setting any PWM frequency above 11.3 kHz will switch
155 all 3 PWM outputs to a 22.5 kHz frequency. Conversely, setting any PWM
156 frequency below 11.3 kHz will switch all 3 PWM outputs to a frequency
157 between 10 and 100 Hz, which can then be tuned separately.
179 The LM96000 supports additional high frequency PWM modes (22.5 kHz, 24 kHz,
180 25.7 kHz, 27.7 kHz and 30 kHz), which can be configured on a per-PWM basis.
266 -1 PWM always 100% (full on)
H A Df71805f.rst85 in2 VIN2 VRAM 100K 100K 2.00 ~1.25 V [1]_
86 in3 VIN3 VCHIPSET 47K 100K 1.47 2.24 V [2]_
150 from 187.5 kHz (default) to 31 Hz. The best frequency depends on the
153 above the audible range, such as 25 kHz, may be a good choice; if this
155 not going below 1 kHz, as the fan tachometers get confused by lower
/openbmc/linux/drivers/iio/humidity/
H A Ddht11.c52 * 34uS > timeres > 30uS ... no problem (30kHz and 32kHz clocks)
56 * Luckily clocks in the 33-44kHz range are quite uncommon, so we can
59 * 40kHz, where this driver is most unreliable, there are two options.
151 if (hum_int < 4) { /* DHT22: 100000 = (3*256+232)*100 */ in dht11_decode()
153 ((temp_int & 0x80) ? -100 : 100); in dht11_decode()
154 dht11->humidity = ((hum_int << 8) + hum_dec) * 100; in dht11_decode()
/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-exynos5.yaml14 at various speeds ranging from 100kHz to 3.4MHz.
43 If not specified, the bus operates in fast-speed mode at 100kHz.
/openbmc/linux/sound/soc/codecs/
H A Dmax9860.c126 static const DECLARE_TLV_DB_SCALE(dva_tlv, -9100, 100, 1);
128 static const DECLARE_TLV_DB_SCALE(adc_tlv, -1200, 100, 0);
132 static const DECLARE_TLV_DB_SCALE(pgam_tlv, 0, 100, 0);
134 static const DECLARE_TLV_DB_SCALE(agcth_tlv, -1800, 100, 0);
137 "AGC Disabled", "50ms", "100ms", "400ms"
167 "Elliptical HP 217Hz notch (16kHz)",
168 "Butterworth HP 500Hz (16kHz)",
169 "Elliptical HP 217Hz notch (8kHz)",
170 "Butterworth HP 500Hz (8kHz)",
171 "Butterworth HP 200Hz (48kHz)"
[all …]
/openbmc/linux/drivers/i2c/busses/
H A Di2c-stm32.h19 STM32_I2C_SPEED_STANDARD, /* 100 kHz */
20 STM32_I2C_SPEED_FAST, /* 400 kHz */
H A Di2c-isch.c49 static int backbone_speed = 33000; /* backbone speed in kHz */
51 MODULE_PARM_DESC(backbone_speed, "Backbone speed in kHz, (default = 33000)");
94 usleep_range(100, 200); in sch_transaction()
154 * 100 kHz. If we actually run at 25 MHz the bus will be in sch_access()
155 * run ~75 kHz instead which should do no harm. in sch_access()
159 outw(backbone_speed / (4 * 100), SMBHSTCLK); in sch_access()
/openbmc/linux/drivers/media/radio/si470x/
H A Dradio-si470x-common.c108 /* Spacing (kHz) */
109 /* 0: 200 kHz (USA, Australia) */
110 /* 1: 100 kHz (Europe, Japan) */
111 /* 2: 50 kHz */
114 MODULE_PARM_DESC(space, "Spacing: 0=200kHz 1=100kHz *2=50kHz*");
241 /* Spacing (kHz) */ in si470x_get_step()
243 /* 0: 200 kHz (USA, Australia) */ in si470x_get_step()
246 /* 1: 100 kHz (Europe, Japan) */ in si470x_get_step()
248 return 100 * 16; in si470x_get_step()
249 /* 2: 50 kHz */ in si470x_get_step()
[all …]
/openbmc/linux/arch/arm/boot/dts/allwinner/
H A Dsun5i-reference-design-tablet.dtsi55 brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
88 * The gsl1680 is rated at 400KHz and it will not work reliable at
89 * 100KHz, this has been confirmed on multiple different q8 tablets.
90 * All other devices on this bus are also rated for 400KHz.
/openbmc/u-boot/arch/arm/cpu/arm1136/mx35/
H A Dtimer.c22 * The 32KHz 32-bit timer overruns in 134217 seconds
35 for (i = 0; i < 100; i++) in timer_init()
38 /* Freerun Mode, 32KHz input */ in timer_init()
/openbmc/u-boot/arch/arm/cpu/arm926ejs/mx25/
H A Dtimer.c27 /* The 32KHz 32-bit timer overruns in 134217 seconds */
39 for (i = 0; i < 100; i++) in timer_init()
42 /* Freerun Mode, 32KHz input */ in timer_init()

12345678910>>...34