Lines Matching +full:100 +full:khz
20 #define MAX_FVCO 500000 /* KHz */
21 #define MAX_FSYS 80000 /* KHz */
22 #define MIN_FSYS 58333 /* KHz */
25 #define FREF 20000 /* KHz */
37 #define FREF 16000 /* KHz */
131 * fref PLL reference clock frequency in KHz
132 * fsys Desired PLL output frequency in KHz
173 * Multiplying by 100 when calculating the temp value, in clock_pll()
174 * and then dividing by 100 to calculate the mfd allows in clock_pll()
178 temp = (100 * fsys) / fref; in clock_pll()
180 mfd = (BUSDIV * temp) / 100; in clock_pll()
186 mfd = (4 * BUSDIV * temp) / 100; in clock_pll()