/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/ |
H A D | mmhub_9_4_1_default.h | 26 #define mmDAGB0_RDCLI0_DEFAULT 0xfe5fe0f9 27 #define mmDAGB0_RDCLI1_DEFAULT 0xfe5fe0f9 28 #define mmDAGB0_RDCLI2_DEFAULT 0xfe5fe0f9 29 #define mmDAGB0_RDCLI3_DEFAULT 0xfe5fe0f9 30 #define mmDAGB0_RDCLI4_DEFAULT 0xfe5fe0f9 31 #define mmDAGB0_RDCLI5_DEFAULT 0xfe5fe0f9 32 #define mmDAGB0_RDCLI6_DEFAULT 0xfe5fe0f9 33 #define mmDAGB0_RDCLI7_DEFAULT 0xfe5fe0f9 34 #define mmDAGB0_RDCLI8_DEFAULT 0xfe5fe0f9 35 #define mmDAGB0_RDCLI9_DEFAULT 0xfe5fe0f9 [all …]
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H A D | mmhub_1_0_default.h | 26 #define mmDAGB0_RDCLI0_DEFAULT 0xfe5fe0f9 27 #define mmDAGB0_RDCLI1_DEFAULT 0xfe5fe0f9 28 #define mmDAGB0_RDCLI2_DEFAULT 0xfe5fe0f9 29 #define mmDAGB0_RDCLI3_DEFAULT 0xfe5fe0f9 30 #define mmDAGB0_RDCLI4_DEFAULT 0xfe5fe0f9 31 #define mmDAGB0_RDCLI5_DEFAULT 0xfe5fe0f9 32 #define mmDAGB0_RDCLI6_DEFAULT 0xfe5fe0f9 33 #define mmDAGB0_RDCLI7_DEFAULT 0xfe5fe0f9 34 #define mmDAGB0_RDCLI8_DEFAULT 0xfe5fe0f9 35 #define mmDAGB0_RDCLI9_DEFAULT 0xfe5fe0f9 [all …]
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H A D | mmhub_2_3_0_default.h | 26 #define mmDAGB0_RDCLI0_DEFAULT 0xfe5fe0f9 27 #define mmDAGB0_RDCLI1_DEFAULT 0xfe5fe0f9 28 #define mmDAGB0_RDCLI2_DEFAULT 0xfe5fe0f9 29 #define mmDAGB0_RDCLI3_DEFAULT 0xfe5fe0f9 30 #define mmDAGB0_RDCLI4_DEFAULT 0xfe5fe0f9 31 #define mmDAGB0_RDCLI5_DEFAULT 0xfe5fe0f9 32 #define mmDAGB0_RDCLI6_DEFAULT 0xfe5fe0f9 33 #define mmDAGB0_RDCLI7_DEFAULT 0xfe5fe0f9 34 #define mmDAGB0_RDCLI8_DEFAULT 0xfe5fe0f9 35 #define mmDAGB0_RDCLI9_DEFAULT 0xfe5fe0f9 [all …]
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H A D | mmhub_2_0_0_default.h | 26 #define mmDAGB0_RDCLI0_DEFAULT 0xfe5fe0f9 27 #define mmDAGB0_RDCLI1_DEFAULT 0xfe5fe0f9 28 #define mmDAGB0_RDCLI2_DEFAULT 0xfe5fe0f9 29 #define mmDAGB0_RDCLI3_DEFAULT 0xfe5fe0f9 30 #define mmDAGB0_RDCLI4_DEFAULT 0xfe5fe0f9 31 #define mmDAGB0_RDCLI5_DEFAULT 0xfe5fe0f9 32 #define mmDAGB0_RDCLI6_DEFAULT 0xfe5fe0f9 33 #define mmDAGB0_RDCLI7_DEFAULT 0xfe5fe0f9 34 #define mmDAGB0_RDCLI8_DEFAULT 0xfe5fe0f9 35 #define mmDAGB0_RDCLI9_DEFAULT 0xfe5fe0f9 [all …]
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/openbmc/linux/drivers/gpu/drm/radeon/ |
H A D | rs600d.h | 32 #define R_000040_GEN_INT_CNTL 0x000040 33 #define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18) 34 #define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1) 35 #define C_000040_SCRATCH_INT_MASK 0xFFFBFFFF 36 #define S_000040_GUI_IDLE_MASK(x) (((x) & 0x1) << 19) 37 #define G_000040_GUI_IDLE_MASK(x) (((x) >> 19) & 0x1) 38 #define C_000040_GUI_IDLE_MASK 0xFFF7FFFF 39 #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) 40 #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) 41 #define C_000040_DMA_VIPH1_INT_EN 0xFFFFDFFF [all …]
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H A D | rv515d.h | 34 #define PCIE_INDEX 0x0030 35 #define PCIE_DATA 0x0034 36 #define MC_IND_INDEX 0x0070 38 #define MC_IND_DATA 0x0074 39 #define RBBM_SOFT_RESET 0x00F0 40 #define CONFIG_MEMSIZE 0x00F8 41 #define HDP_FB_LOCATION 0x0134 42 #define CP_CSQ_CNTL 0x0740 43 #define CP_CSQ_MODE 0x0744 44 #define CP_CSQ_ADDR 0x07F0 [all …]
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/openbmc/qemu/bsd-user/arm/ |
H A D | target_arch_thread.h | 33 sp = (u_int)(stack_base + stack_size) & ~0x7; in target_thread_set_upcall() 38 env->regs[15] = entry & 0xfffffffe; in target_thread_set_upcall() 40 env->regs[0] = arg; in target_thread_set_upcall() 54 memset(regs, 0, sizeof(*regs)); in target_thread_init() 64 regs->ARM_pc = infop->entry & 0xfffffffe; in target_thread_init() 66 regs->ARM_lr = infop->entry & 0xfffffffe; in target_thread_init() 70 * support that functionality, so it's ignored. When set to 0, FreeBSD's csu in target_thread_init() 75 * r0 ps_strings 0 passed since ps arg setting not supported in target_thread_init() 76 * r1 obj_main ignored by _start(), so 0 passed in target_thread_init() 77 * r2 cleanup generated by rtld or ignored by _start(), so 0 passed in target_thread_init()
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/openbmc/qemu/hw/misc/ |
H A D | xlnx-versal-pmc-iou-slcr.c | 37 #define XILINX_VERSAL_PMC_IOU_SLCR_ERR_DEBUG 0 40 REG32(MIO_PIN_0, 0x0) 45 REG32(MIO_PIN_1, 0x4) 50 REG32(MIO_PIN_2, 0x8) 55 REG32(MIO_PIN_3, 0xc) 60 REG32(MIO_PIN_4, 0x10) 65 REG32(MIO_PIN_5, 0x14) 70 REG32(MIO_PIN_6, 0x18) 75 REG32(MIO_PIN_7, 0x1c) 80 REG32(MIO_PIN_8, 0x20) [all …]
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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/ |
H A D | gk110.c | 39 { 0x020520, 0xfffffffc }, in gk110_pmu_pgob() 40 { 0x020524, 0xfffffffe }, in gk110_pmu_pgob() 41 { 0x020524, 0xfffffffc }, in gk110_pmu_pgob() 42 { 0x020524, 0xfffffff8 }, in gk110_pmu_pgob() 43 { 0x020524, 0xffffffe0 }, in gk110_pmu_pgob() 44 { 0x020530, 0xfffffffe }, in gk110_pmu_pgob() 45 { 0x02052c, 0xfffffffa }, in gk110_pmu_pgob() 46 { 0x02052c, 0xfffffff0 }, in gk110_pmu_pgob() 47 { 0x02052c, 0xffffffc0 }, in gk110_pmu_pgob() 48 { 0x02052c, 0xffffff00 }, in gk110_pmu_pgob() [all …]
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/openbmc/qemu/hw/usb/ |
H A D | xlnx-versal-usb2-ctrl-regs.c | 3 * USB2.0 controller 40 #define XILINX_VERSAL_USB2_CTRL_REGS_ERR_DEBUG 0 43 REG32(BUS_FILTER, 0x30) 44 FIELD(BUS_FILTER, BYPASS, 0, 4) 45 REG32(PORT, 0x34) 50 FIELD(PORT, HUB_PERM_ATTACH, 0, 1) 51 REG32(JITTER_ADJUST, 0x38) 52 FIELD(JITTER_ADJUST, FLADJ, 0, 6) 53 REG32(BIGENDIAN, 0x40) 54 FIELD(BIGENDIAN, ENDIAN_GS, 0, 1) [all …]
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/openbmc/linux/drivers/gpu/drm/sti/ |
H A D | sti_hqvdp_lut.h | 24 0x0000ffff, 0x00010000, 0x000100ff, 0x00000000, 25 0x00000000, 0x00050000, 0xfffc00ff, 0x00000000, 26 0x00000000, 0x00090000, 0xfff900fe, 0x00000000, 27 0x00000000, 0x0010ffff, 0xfff600fb, 0x00000000, 28 0x00000000, 0x0017fffe, 0xfff400f7, 0x00000000, 29 0x00000000, 0x001ffffd, 0xfff200f2, 0x00000000, 30 0x00000000, 0x0027fffc, 0xfff100ec, 0x00000000, 31 0x00000000, 0x0030fffb, 0xfff000e5, 0x00000000, 32 0x00000000, 0x003afffa, 0xffee00de, 0x00000000, 33 0x00000000, 0x0044fff9, 0xffed00d6, 0x00000000, [all …]
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/openbmc/linux/drivers/net/phy/ |
H A D | uPD60620.c | 12 #define UPD60620_PHY_ID 0xb8242824 16 #define PHY_PHYSCR 0x1F /* PHY.31 */ 17 #define PHY_PHYSCR_10MB 0x0004 /* PHY speed = 10mb */ 18 #define PHY_PHYSCR_100MB 0x0008 /* PHY speed = 100mb */ 19 #define PHY_PHYSCR_DUPLEX 0x0010 /* PHY Duplex */ 22 #define PHY_SPM 0x12 /* PHY.18 */ 30 return phy_write(phydev, PHY_SPM, 0x0180 | phydev->mdio.addr); in upd60620_config_init() 41 if (phy_state < 0) in upd60620_read_status() 44 phydev->link = 0; in upd60620_read_status() 46 phydev->pause = 0; in upd60620_read_status() [all …]
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/openbmc/linux/net/netfilter/ipset/ |
H A D | pfxlen.c | 12 E(0x00000000, 0x00000000, 0x00000000, 0x00000000), \ 13 E(0x80000000, 0x00000000, 0x00000000, 0x00000000), \ 14 E(0xC0000000, 0x00000000, 0x00000000, 0x00000000), \ 15 E(0xE0000000, 0x00000000, 0x00000000, 0x00000000), \ 16 E(0xF0000000, 0x00000000, 0x00000000, 0x00000000), \ 17 E(0xF8000000, 0x00000000, 0x00000000, 0x00000000), \ 18 E(0xFC000000, 0x00000000, 0x00000000, 0x00000000), \ 19 E(0xFE000000, 0x00000000, 0x00000000, 0x00000000), \ 20 E(0xFF000000, 0x00000000, 0x00000000, 0x00000000), \ 21 E(0xFF800000, 0x00000000, 0x00000000, 0x00000000), \ [all …]
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/openbmc/linux/arch/csky/kernel/probes/ |
H A D | simulate-insn.c | 18 *ptr = *(®s->exregs[0] + index - 16); in csky_insn_reg_get_val() 47 *(®s->exregs[0] + index - 16) = val; in csky_insn_reg_set_val() 72 addr + sign_extend32((opcode & 0x3ff) << 1, 9)); in simulate_br16() 79 addr + sign_extend32((opcode & 0xffff0000) >> 15, 15)); in simulate_br32() 87 addr + sign_extend32((opcode & 0x3ff) << 1, 9)); in simulate_bt16() 97 addr + sign_extend32((opcode & 0xffff0000) >> 15, 15)); in simulate_bt32() 107 addr + sign_extend32((opcode & 0x3ff) << 1, 9)); in simulate_bf16() 117 addr + sign_extend32((opcode & 0xffff0000) >> 15, 15)); in simulate_bf32() 125 unsigned long tmp = (opcode >> 2) & 0xf; in simulate_jmp16() 129 instruction_pointer_set(regs, tmp & 0xfffffffe); in simulate_jmp16() [all …]
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/openbmc/qemu/tests/tcg/xtensa/ |
H A D | test_b.S | 6 movi a2, 0xa5a5ff00 7 movi a3, 0x5a5a00ff 11 movi a2, 0xa5a5ff01 20 movi a2, 0 21 movi a3, 0 39 movi a2, 0xffffffff 63 movi a2, 0xffffffff 72 movi a2, 0xa5a5ffa5 73 movi a3, 0xa5a5ff00 77 movi a2, 0xa5a5a5a5 [all …]
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/openbmc/linux/drivers/firmware/broadcom/ |
H A D | bcm47xx_sprom.c | 76 if (err < 0) \ 78 err = kstrto ## type(strim(buf), 0, &var); \ 104 if (err < 0) in NVRAM_READ_VAL() 106 err = kstrtou32(strim(buf), 0, &val); in NVRAM_READ_VAL() 112 *val_lo = (val & 0x0000FFFFU); in NVRAM_READ_VAL() 113 *val_hi = (val & 0xFFFF0000U) >> 16; in NVRAM_READ_VAL() 125 if (err < 0) in nvram_read_leddc() 127 err = kstrtou32(strim(buf), 0, &val); in nvram_read_leddc() 134 if (val == 0xffff || val == 0xffffffff) in nvram_read_leddc() 137 *leddc_on_time = val & 0xff; in nvram_read_leddc() [all …]
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/openbmc/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
H A D | network.txt | 40 #size-cells = <0>; 95 Definition : Must be 0,2,4...64. the number of TDM entry. 106 fsl,hmask = /bits/ 16 <0x0000>; 116 fsl,tx-timeslot-mask = <0xfffffffe>; 117 fsl,rx-timeslot-mask = <0xfffffffe>; 119 fsl,tdm-id = <0>; 120 fsl,siram-entry-id = <0>;
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/openbmc/qemu/tests/tcg/tricore/asm/ |
H A D | test_muls.S | 5 TEST_D_DD_PSW(muls.u, 1, 0xffffffff, 0x78000b80, 0x80000001, 0xffffffff) 6 TEST_D_DD_PSW(muls.u, 2, 0xffffffff, 0x60000b80, 0xfffffffe, 0xffffffff)
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/openbmc/openbmc/meta-facebook/meta-harma/recipes-phosphor/initrdscripts/phosphor-static-norootfs-init/ |
H A D | 99-platform-init | 10 FMC_WDT2_CTRL_VAL=$(/sbin/devmem 0x1e620064) 11 FMC_WDT2_CTRL_VAL=$((16#${FMC_WDT2_CTRL_VAL#"0x"})) 12 SET_VAL=$((FMC_WDT2_CTRL_VAL & 0xFFFFFFFE)) 13 /sbin/devmem 0x1e620064 32 "$SET_VAL" 18 if [ "$((FMC_WDT2_CTRL_VAL & 0x00000010))" != "0" ]; then 21 echo "0" > "$SLOT_FILE" 24 exit 0
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/openbmc/openbmc/meta-facebook/meta-bletchley/recipes-phosphor/initrdscripts/phosphor-static-norootfs-init/ |
H A D | 99-platform-init | 9 FMC_WDT2_CTRL_VAL=$(/sbin/devmem 0x1e620064) 10 FMC_WDT2_CTRL_VAL=$((16#${FMC_WDT2_CTRL_VAL#"0x"})) 11 SET_VAL=$((FMC_WDT2_CTRL_VAL & 0xFFFFFFFE)) 12 /sbin/devmem 0x1e620064 32 "$SET_VAL" 17 if [ "$((FMC_WDT2_CTRL_VAL & 0x00000010))" != "0" ]; then 20 echo "0" > "$SLOT_FILE" 23 exit 0
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/openbmc/openbmc/meta-facebook/meta-ventura/recipes-phosphor/initrdscripts/phosphor-static-norootfs-init/ |
H A D | 99-platform-init | 9 FMC_WDT2_CTRL_VAL=$(/sbin/devmem 0x1e620064) 10 FMC_WDT2_CTRL_VAL=$((16#${FMC_WDT2_CTRL_VAL#"0x"})) 11 SET_VAL=$((FMC_WDT2_CTRL_VAL & 0xFFFFFFFE)) 12 /sbin/devmem 0x1e620064 32 "$SET_VAL" 17 if [ "$((FMC_WDT2_CTRL_VAL & 0x00000010))" != "0" ]; then 20 echo "0" > "$SLOT_FILE" 23 exit 0
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/openbmc/linux/arch/arm64/boot/dts/freescale/ |
H A D | fsl-ls1043a-rdb.dts | 35 reg = <0x40>; 41 reg = <0x4c>; 46 reg = <0x51>; 51 reg = <0x52>; 56 reg = <0x53>; 61 reg = <0x68>; 70 ranges = <0x0 0x0 0x0 0x60000000 0x08000000 71 0x1 0x0 0x0 0x7e800000 0x00010000 72 0x2 0x0 0x0 0x7fb00000 0x00000100>; 74 nor@0,0 { [all …]
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/openbmc/qemu/tests/tcg/mips/user/ase/dsp/ |
H A D | test_dsp_r2_addqh_r_w.c | 9 rs = 0x00000010; in main() 10 rt = 0x00000001; in main() 11 result = 0x00000009; in main() 14 ("addqh_r.w %0, %1, %2\n\t" in main() 21 rs = 0xFFFFFFFE; in main() 22 rt = 0x00000001; in main() 23 result = 0x00000000; in main() 26 ("addqh_r.w %0, %1, %2\n\t" in main() 33 return 0; in main()
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H A D | test_dsp_r2_addqh_w.c | 9 rs = 0x00000010; in main() 10 rt = 0x00000001; in main() 11 result = 0x00000008; in main() 14 ("addqh.w %0, %1, %2\n\t" in main() 21 rs = 0xFFFFFFFE; in main() 22 rt = 0x00000001; in main() 23 result = 0xFFFFFFFF; in main() 26 ("addqh.w %0, %1, %2\n\t" in main() 33 return 0; in main()
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/openbmc/linux/include/uapi/linux/netfilter/ |
H A D | xt_time.h | 19 XT_TIME_LOCAL_TZ = 1 << 0, 25 XT_TIME_ALL_MONTHDAYS = 0xFFFFFFFE, 26 XT_TIME_ALL_WEEKDAYS = 0xFE, 27 XT_TIME_MIN_DAYTIME = 0,
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