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Searched +full:0 +full:xffffff7f (Results 1 – 23 of 23) sorted by relevance

/openbmc/linux/arch/parisc/kernel/
H A Dperf_images.h27 0x4c00c000, 0x00000000, 0x00060000, 0x00000000,
28 0xe0e0e0e0, 0x004e0004, 0x07ffffff, 0xffc01380,
29 0x0101ffff, 0xfffff104, 0xe000c07f, 0xfffffffc,
30 0x01380010, 0x1fffffff, 0xff000000, 0x00000000,
31 0x00000fff, 0xff00000f, 0xffff0000, 0x0fffff00,
32 0x000fffff, 0x00000000, 0x00000000, 0x00ffffff,
33 0xfffff000, 0x0000000f, 0xffffffff, 0xff000000,
34 0x0000ffff, 0xfffffff0, 0x00000000, 0x0fffffff,
35 0xffff0000, 0x00000000, 0x6fffffff, 0xffffffff,
36 0xfff55fff, 0xffffffff, 0xffffffff, 0xf0000000,
[all …]
/openbmc/qemu/tests/qtest/
H A Ddm163-test.c29 GPIO_OUT(name, 0); \
30 } while (0)
36 qtest_writel(qts, 0x48000400, 0xFFFFFEB7); in rise_gpio_pin_dck()
38 qtest_writel(qts, 0x48000414, 0x00000002); in rise_gpio_pin_dck()
44 qtest_writel(qts, 0x48000400, 0xFFFFFEB7); in lower_gpio_pin_dck()
45 /* Write 0 in ODR for PB1 */ in lower_gpio_pin_dck()
46 qtest_writel(qts, 0x48000414, 0x00000000); in lower_gpio_pin_dck()
52 qtest_writel(qts, 0x48000800, 0xFFFFF7FF); in rise_gpio_pin_selbk()
54 qtest_writel(qts, 0x48000814, 0x00000020); in rise_gpio_pin_selbk()
60 qtest_writel(qts, 0x48000800, 0xFFFFF7FF); in lower_gpio_pin_selbk()
[all …]
/openbmc/qemu/tests/tcg/xtensa/
H A Dtest_clamps.S8 movi a2, 0
9 movi a3, 0
13 movi a2, 0x7f
14 movi a3, 0x7f
18 movi a2, 0xffffff80
19 movi a3, 0xffffff80
23 movi a2, 0x80
24 movi a3, 0x7f
28 movi a2, 0xffffff7f
29 movi a3, 0xffffff80
[all …]
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Ds3c6410.dtsi27 valid-mask = <0xffffff7f>;
28 valid-wakeup-mask = <0x00200004>;
32 valid-mask = <0xffffffff>;
33 valid-wakeup-mask = <0x53020000>;
39 reg = <0x7e00f000 0x1000>;
45 reg = <0x7f00f000 0x1000>;
52 #size-cells = <0>;
/openbmc/linux/drivers/net/ethernet/dec/tulip/
H A Dpnic2.c23 * CSR 6 (mask = 0xfe3bd1fd of bits not to change)
29 * Bit 13 - Start - 1, Stop - 0 Transmissions
32 * Bit 1 - Start - 1, Stop - 0 Receive
35 * CSR 14 (mask = 0xfff0ee39 of bits not to change)
55 * Bit 15 - LPN is 1 if all above bits are valid other wise 0
58 * Bit 2 - LS10B - link state of 10baseT 0 - good, 1 - failed
59 * Bit 1 - LS100B - link state of 100baseT 0 - good, 1 - failed
66 * 1 0 0 (X) 0 (X) 1 NWAY
67 * 0 0 1 0 (X) 0 10baseT
68 * 0 1 0 1 1 (X) 100baseT
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,vic.yaml45 represents single interrupt source, starting from source 0 at
75 reg = <0x60000 0x1000>;
77 valid-mask = <0xffffff7f>;
78 valid-wakeup-mask = <0x0000ff7f>;
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dr100d.h31 #define CP_PACKET0 0x00000000
32 #define PACKET0_BASE_INDEX_SHIFT 0
33 #define PACKET0_BASE_INDEX_MASK (0x1ffff << 0)
35 #define PACKET0_COUNT_MASK (0x3fff << 16)
36 #define CP_PACKET1 0x40000000
37 #define CP_PACKET2 0x80000000
38 #define PACKET2_PAD_SHIFT 0
39 #define PACKET2_PAD_MASK (0x3fffffff << 0)
40 #define CP_PACKET3 0xC0000000
42 #define PACKET3_IT_OPCODE_MASK (0xff << 8)
[all …]
H A Drv250d.h31 #define R_00000D_SCLK_CNTL_M6 0x00000D
32 #define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0)
33 #define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7)
34 #define C_00000D_SCLK_SRC_SEL 0xFFFFFFF8
35 #define S_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 3)
36 #define G_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) >> 3) & 0x1)
37 #define C_00000D_CP_MAX_DYN_STOP_LAT 0xFFFFFFF7
38 #define S_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 4)
39 #define G_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) >> 4) & 0x1)
40 #define C_00000D_HDP_MAX_DYN_STOP_LAT 0xFFFFFFEF
[all …]
H A Dr300d.h31 #define CP_PACKET0 0x00000000
32 #define PACKET0_BASE_INDEX_SHIFT 0
33 #define PACKET0_BASE_INDEX_MASK (0x1ffff << 0)
35 #define PACKET0_COUNT_MASK (0x3fff << 16)
36 #define CP_PACKET1 0x40000000
37 #define CP_PACKET2 0x80000000
38 #define PACKET2_PAD_SHIFT 0
39 #define PACKET2_PAD_MASK (0x3fffffff << 0)
40 #define CP_PACKET3 0xC0000000
42 #define PACKET3_IT_OPCODE_MASK (0xff << 8)
[all …]
H A Drv515d.h34 #define PCIE_INDEX 0x0030
35 #define PCIE_DATA 0x0034
36 #define MC_IND_INDEX 0x0070
38 #define MC_IND_DATA 0x0074
39 #define RBBM_SOFT_RESET 0x00F0
40 #define CONFIG_MEMSIZE 0x00F8
41 #define HDP_FB_LOCATION 0x0134
42 #define CP_CSQ_CNTL 0x0740
43 #define CP_CSQ_MODE 0x0744
44 #define CP_CSQ_ADDR 0x07F0
[all …]
H A Dr420d.h31 #define R_0001F8_MC_IND_INDEX 0x0001F8
32 #define S_0001F8_MC_IND_ADDR(x) (((x) & 0x7F) << 0)
33 #define G_0001F8_MC_IND_ADDR(x) (((x) >> 0) & 0x7F)
34 #define C_0001F8_MC_IND_ADDR 0xFFFFFF80
35 #define S_0001F8_MC_IND_WR_EN(x) (((x) & 0x1) << 8)
36 #define G_0001F8_MC_IND_WR_EN(x) (((x) >> 8) & 0x1)
37 #define C_0001F8_MC_IND_WR_EN 0xFFFFFEFF
38 #define R_0001FC_MC_IND_DATA 0x0001FC
39 #define S_0001FC_MC_IND_DATA(x) (((x) & 0xFFFFFFFF) << 0)
40 #define G_0001FC_MC_IND_DATA(x) (((x) >> 0) & 0xFFFFFFFF)
[all …]
H A Drs600d.h32 #define R_000040_GEN_INT_CNTL 0x000040
33 #define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18)
34 #define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1)
35 #define C_000040_SCRATCH_INT_MASK 0xFFFBFFFF
36 #define S_000040_GUI_IDLE_MASK(x) (((x) & 0x1) << 19)
37 #define G_000040_GUI_IDLE_MASK(x) (((x) >> 19) & 0x1)
38 #define C_000040_GUI_IDLE_MASK 0xFFF7FFFF
39 #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13)
40 #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1)
41 #define C_000040_DMA_VIPH1_INT_EN 0xFFFFDFFF
[all …]
H A Dr600d.h30 #define CP_PACKET2 0x80000000
31 #define PACKET2_PAD_SHIFT 0
32 #define PACKET2_PAD_MASK (0x3fffffff << 0)
41 #define R6XX_MAX_BACKENDS_MASK 0xff
43 #define R6XX_MAX_SIMDS_MASK 0xff
45 #define R6XX_MAX_PIPES_MASK 0xff
48 #define ARRAY_LINEAR_GENERAL 0x00000000
49 #define ARRAY_LINEAR_ALIGNED 0x00000001
50 #define ARRAY_1D_TILED_THIN1 0x00000002
51 #define ARRAY_2D_TILED_THIN1 0x00000004
[all …]
H A Devergreend.h33 #define EVERGREEN_MAX_BACKENDS_MASK 0xFF
35 #define EVERGREEN_MAX_SIMDS_MASK 0xFFFF
37 #define EVERGREEN_MAX_PIPES_MASK 0xFF
38 #define EVERGREEN_MAX_LDS_NUM 0xFFFF
40 #define CYPRESS_GB_ADDR_CONFIG_GOLDEN 0x02011003
41 #define BARTS_GB_ADDR_CONFIG_GOLDEN 0x02011003
42 #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003
43 #define JUNIPER_GB_ADDR_CONFIG_GOLDEN 0x02010002
44 #define REDWOOD_GB_ADDR_CONFIG_GOLDEN 0x02010002
45 #define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002
[all …]
H A Dcik.c150 * Returns 0 for success or -EINVAL for an invalid register
170 return 0; in cik_get_allowed_info_register()
205 int actual_temp = 0; in ci_get_temp()
210 if (temp & 0x200) in ci_get_temp()
213 actual_temp = temp & 0x1ff; in ci_get_temp()
222 int actual_temp = 0; in kv_get_temp()
224 temp = RREG32_SMC(0xC0300E0C); in kv_get_temp()
229 actual_temp = 0; in kv_get_temp()
264 (0x0e00 << 16) | (0xc12c >> 2),
265 0x00000000,
[all …]
/openbmc/linux/drivers/char/agp/
H A Dali-agp.c13 #define ALI_AGPCTRL 0xb8
14 #define ALI_ATTBASE 0xbc
15 #define ALI_TLBCTRL 0xc0
16 #define ALI_TAGCTRL 0xc4
17 #define ALI_CACHE_FLUSH_CTRL 0xD0
18 #define ALI_CACHE_FLUSH_ADDR_MASK 0xFFFFF000
19 #define ALI_CACHE_FLUSH_EN 0x100
28 temp &= ~(0xfffffff0); in ali_fetch_size()
31 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { in ali_fetch_size()
40 return 0; in ali_fetch_size()
[all …]
/openbmc/linux/drivers/media/pci/cx25821/
H A Dcx25821-medusa-video.c24 u32 value = 0; in medusa_enable_bluefield_output()
25 u32 tmp = 0; in medusa_enable_bluefield_output()
63 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl, &tmp); in medusa_enable_bluefield_output()
64 value &= 0xFFFFFF7F; /* clear BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
66 value |= 0x00000080; /* set BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
67 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl, value); in medusa_enable_bluefield_output()
69 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl_ns, &tmp); in medusa_enable_bluefield_output()
70 value &= 0xFFFFFF7F; in medusa_enable_bluefield_output()
72 value |= 0x00000080; /* set BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
73 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl_ns, value); in medusa_enable_bluefield_output()
[all …]
/openbmc/linux/Documentation/core-api/
H A Dprintk-formats.rst113 %pS versatile_init+0x0/0x110
115 %pSR versatile_init+0x9/0x110
117 %pB prev_fn_of_versatile_init+0x88/0x88
135 %pS versatile_init+0x0/0x110 [module_name]
136 %pSb versatile_init+0x0/0x110 [module_name ed5019fdf5e53be37cb1ba7899292d7e143b259e]
137 %pSRb versatile_init+0x9/0x110 [module_name ed5019fdf5e53be37cb1ba7899292d7e143b259e]
139 %pBb prev_fn_of_versatile_init+0x88/0x88 [module_name ed5019fdf5e53be37cb1ba7899292d7e143b259e]
211 %pr [mem 0x60000000-0x6fffffff flags 0x2200] or
212 [mem 0x0000000060000000-0x000000006fffffff flags 0x2200]
213 %pR [mem 0x60000000-0x6fffffff pref] or
[all …]
/openbmc/linux/arch/sh/kernel/cpu/sh4a/
H A Dsetup-sh7786.c35 DEFINE_RES_MEM(0xffea0000, 0x100),
36 DEFINE_RES_IRQ(evt2irq(0x700)),
37 DEFINE_RES_IRQ(evt2irq(0x720)),
38 DEFINE_RES_IRQ(evt2irq(0x760)),
39 DEFINE_RES_IRQ(evt2irq(0x740)),
44 .id = 0,
62 DEFINE_RES_MEM(0xffeb0000, 0x100),
63 DEFINE_RES_IRQ(evt2irq(0x780)),
67 DEFINE_RES_MEM(0xffeb0000, 0x100),
69 DEFINE_RES_IRQ(0),
[all …]
/openbmc/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl/
H A Dhw_atl_llh_internal.h16 #define HW_ATL_TS_RESET_ADR 0x00003100
17 #define HW_ATL_TS_RESET_MSK 0x00000004
22 #define HW_ATL_TS_POWER_DOWN_ADR 0x00003100
23 #define HW_ATL_TS_POWER_DOWN_MSK 0x00000001
24 #define HW_ATL_TS_POWER_DOWN_SHIFT 0
28 #define HW_ATL_TS_READY_ADR 0x00003120
29 #define HW_ATL_TS_READY_MSK 0x80000000
34 #define HW_ATL_TS_READY_LATCH_HIGH_ADR 0x00003120
35 #define HW_ATL_TS_READY_LATCH_HIGH_MSK 0x40000000
39 /* COM Temperature Sense Data Out [B:0] Bitfield Definitions */
[all …]
/openbmc/qemu/hw/net/can/
H A Dxlnx-versal-canfd.c48 REG32(SOFTWARE_RESET_REGISTER, 0x0)
50 FIELD(SOFTWARE_RESET_REGISTER, SRST, 0, 1)
51 REG32(MODE_SELECT_REGISTER, 0x4)
60 FIELD(MODE_SELECT_REGISTER, SLEEP, 0, 1)
61 REG32(ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, 0x8)
62 FIELD(ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, BRP, 0, 8)
63 REG32(ARBITRATION_PHASE_BIT_TIMING_REGISTER, 0xc)
66 FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, TS1, 0, 8)
67 REG32(ERROR_COUNTER_REGISTER, 0x10)
69 FIELD(ERROR_COUNTER_REGISTER, TEC, 0, 8)
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v10_0.c60 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
62 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087
64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
69 …R_CONFIG__NUM_PKRS__SHIFT 0x8
70 …__NUM_PKRS_MASK 0x00000700L
72 #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006
74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007
77 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55
78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0
[all …]
/openbmc/linux/drivers/net/ethernet/intel/e1000e/
H A Dnetdev.c37 module_param(debug, int, 0);
38 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
76 {E1000_RDLEN(0), "RDLEN"},
77 {E1000_RDH(0), "RDH"},
78 {E1000_RDT(0), "RDT"},
80 {E1000_RXDCTL(0), "RXDCTL"},
82 {E1000_RDBAL(0), "RDBAL"},
83 {E1000_RDBAH(0), "RDBAH"},
92 {E1000_TDBAL(0), "TDBAL"},
93 {E1000_TDBAH(0), "TDBAH"},
[all …]