Lines Matching +full:0 +full:xffffff7f
48 REG32(SOFTWARE_RESET_REGISTER, 0x0)
50 FIELD(SOFTWARE_RESET_REGISTER, SRST, 0, 1)
51 REG32(MODE_SELECT_REGISTER, 0x4)
60 FIELD(MODE_SELECT_REGISTER, SLEEP, 0, 1)
61 REG32(ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, 0x8)
62 FIELD(ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, BRP, 0, 8)
63 REG32(ARBITRATION_PHASE_BIT_TIMING_REGISTER, 0xc)
66 FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, TS1, 0, 8)
67 REG32(ERROR_COUNTER_REGISTER, 0x10)
69 FIELD(ERROR_COUNTER_REGISTER, TEC, 0, 8)
70 REG32(ERROR_STATUS_REGISTER, 0x14)
79 FIELD(ERROR_STATUS_REGISTER, CRCER, 0, 1)
80 REG32(STATUS_REGISTER, 0x18)
92 FIELD(STATUS_REGISTER, CONFIG, 0, 1)
93 REG32(INTERRUPT_STATUS_REGISTER, 0x1c)
119 FIELD(INTERRUPT_STATUS_REGISTER, ARBLST, 0, 1)
120 REG32(INTERRUPT_ENABLE_REGISTER, 0x20)
139 FIELD(INTERRUPT_ENABLE_REGISTER, EARBLOST, 0, 1)
140 REG32(INTERRUPT_CLEAR_REGISTER, 0x24)
159 FIELD(INTERRUPT_CLEAR_REGISTER, CARBLOST, 0, 1)
160 REG32(TIMESTAMP_REGISTER, 0x28)
162 FIELD(TIMESTAMP_REGISTER, CTS, 0, 1)
163 REG32(DATA_PHASE_BAUD_RATE_PRESCALER_REGISTER, 0x88)
166 FIELD(DATA_PHASE_BAUD_RATE_PRESCALER_REGISTER, DP_BRP, 0, 8)
167 REG32(DATA_PHASE_BIT_TIMING_REGISTER, 0x8c)
170 FIELD(DATA_PHASE_BIT_TIMING_REGISTER, DP_TS1, 0, 5)
171 REG32(TX_BUFFER_READY_REQUEST_REGISTER, 0x90)
203 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR0, 0, 1)
204 REG32(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, 0x94)
236 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS0, 0, 1)
237 REG32(TX_BUFFER_CANCEL_REQUEST_REGISTER, 0x98)
269 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR0, 0, 1)
270 REG32(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, 0x9c)
324 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS0, 0, 1)
325 REG32(TX_EVENT_FIFO_STATUS_REGISTER, 0xa0)
328 FIELD(TX_EVENT_FIFO_STATUS_REGISTER, TXE_RI, 0, 5)
329 REG32(TX_EVENT_FIFO_WATERMARK_REGISTER, 0xa4)
330 FIELD(TX_EVENT_FIFO_WATERMARK_REGISTER, TXE_FWM, 0, 5)
331 REG32(ACCEPTANCE_FILTER_CONTROL_REGISTER, 0xe0)
363 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF0, 0, 1)
364 REG32(RX_FIFO_STATUS_REGISTER, 0xe8)
370 FIELD(RX_FIFO_STATUS_REGISTER, RI, 0, 6)
371 REG32(RX_FIFO_WATERMARK_REGISTER, 0xec)
374 FIELD(RX_FIFO_WATERMARK_REGISTER, RXFWM, 0, 6)
375 REG32(TB_ID_REGISTER, 0x100)
380 FIELD(TB_ID_REGISTER, RTR_RRS, 0, 1)
381 REG32(TB0_DLC_REGISTER, 0x104)
388 FIELD(TB0_DLC_REGISTER, RSVD1, 0, 16)
389 REG32(TB_DW0_REGISTER, 0x108)
393 FIELD(TB_DW0_REGISTER, DATA_BYTES3, 0, 8)
394 REG32(TB_DW1_REGISTER, 0x10c)
398 FIELD(TB_DW1_REGISTER, DATA_BYTES7, 0, 8)
399 REG32(TB_DW2_REGISTER, 0x110)
403 FIELD(TB_DW2_REGISTER, DATA_BYTES11, 0, 8)
404 REG32(TB_DW3_REGISTER, 0x114)
408 FIELD(TB_DW3_REGISTER, DATA_BYTES15, 0, 8)
409 REG32(TB_DW4_REGISTER, 0x118)
413 FIELD(TB_DW4_REGISTER, DATA_BYTES19, 0, 8)
414 REG32(TB_DW5_REGISTER, 0x11c)
418 FIELD(TB_DW5_REGISTER, DATA_BYTES23, 0, 8)
419 REG32(TB_DW6_REGISTER, 0x120)
423 FIELD(TB_DW6_REGISTER, DATA_BYTES27, 0, 8)
424 REG32(TB_DW7_REGISTER, 0x124)
428 FIELD(TB_DW7_REGISTER, DATA_BYTES31, 0, 8)
429 REG32(TB_DW8_REGISTER, 0x128)
433 FIELD(TB_DW8_REGISTER, DATA_BYTES35, 0, 8)
434 REG32(TB_DW9_REGISTER, 0x12c)
438 FIELD(TB_DW9_REGISTER, DATA_BYTES39, 0, 8)
439 REG32(TB_DW10_REGISTER, 0x130)
443 FIELD(TB_DW10_REGISTER, DATA_BYTES43, 0, 8)
444 REG32(TB_DW11_REGISTER, 0x134)
448 FIELD(TB_DW11_REGISTER, DATA_BYTES47, 0, 8)
449 REG32(TB_DW12_REGISTER, 0x138)
453 FIELD(TB_DW12_REGISTER, DATA_BYTES51, 0, 8)
454 REG32(TB_DW13_REGISTER, 0x13c)
458 FIELD(TB_DW13_REGISTER, DATA_BYTES55, 0, 8)
459 REG32(TB_DW14_REGISTER, 0x140)
463 FIELD(TB_DW14_REGISTER, DATA_BYTES59, 0, 8)
464 REG32(TB_DW15_REGISTER, 0x144)
468 FIELD(TB_DW15_REGISTER, DATA_BYTES63, 0, 8)
469 REG32(AFMR_REGISTER, 0xa00)
474 FIELD(AFMR_REGISTER, AMRTR, 0, 1)
475 REG32(AFIR_REGISTER, 0xa04)
480 FIELD(AFIR_REGISTER, AIRTR, 0, 1)
481 REG32(TXE_FIFO_TB_ID_REGISTER, 0x2000)
486 FIELD(TXE_FIFO_TB_ID_REGISTER, RTR_RRS, 0, 1)
487 REG32(TXE_FIFO_TB_DLC_REGISTER, 0x2004)
493 FIELD(TXE_FIFO_TB_DLC_REGISTER, TIMESTAMP, 0, 16)
494 REG32(RB_ID_REGISTER, 0x2100)
499 FIELD(RB_ID_REGISTER, RTR_RRS, 0, 1)
500 REG32(RB_DLC_REGISTER, 0x2104)
506 FIELD(RB_DLC_REGISTER, TIMESTAMP, 0, 16)
507 REG32(RB_DW0_REGISTER, 0x2108)
511 FIELD(RB_DW0_REGISTER, DATA_BYTES3, 0, 8)
512 REG32(RB_DW1_REGISTER, 0x210c)
516 FIELD(RB_DW1_REGISTER, DATA_BYTES7, 0, 8)
517 REG32(RB_DW2_REGISTER, 0x2110)
521 FIELD(RB_DW2_REGISTER, DATA_BYTES11, 0, 8)
522 REG32(RB_DW3_REGISTER, 0x2114)
526 FIELD(RB_DW3_REGISTER, DATA_BYTES15, 0, 8)
527 REG32(RB_DW4_REGISTER, 0x2118)
531 FIELD(RB_DW4_REGISTER, DATA_BYTES19, 0, 8)
532 REG32(RB_DW5_REGISTER, 0x211c)
536 FIELD(RB_DW5_REGISTER, DATA_BYTES23, 0, 8)
537 REG32(RB_DW6_REGISTER, 0x2120)
541 FIELD(RB_DW6_REGISTER, DATA_BYTES27, 0, 8)
542 REG32(RB_DW7_REGISTER, 0x2124)
546 FIELD(RB_DW7_REGISTER, DATA_BYTES31, 0, 8)
547 REG32(RB_DW8_REGISTER, 0x2128)
551 FIELD(RB_DW8_REGISTER, DATA_BYTES35, 0, 8)
552 REG32(RB_DW9_REGISTER, 0x212c)
556 FIELD(RB_DW9_REGISTER, DATA_BYTES39, 0, 8)
557 REG32(RB_DW10_REGISTER, 0x2130)
561 FIELD(RB_DW10_REGISTER, DATA_BYTES43, 0, 8)
562 REG32(RB_DW11_REGISTER, 0x2134)
566 FIELD(RB_DW11_REGISTER, DATA_BYTES47, 0, 8)
567 REG32(RB_DW12_REGISTER, 0x2138)
571 FIELD(RB_DW12_REGISTER, DATA_BYTES51, 0, 8)
572 REG32(RB_DW13_REGISTER, 0x213c)
576 FIELD(RB_DW13_REGISTER, DATA_BYTES55, 0, 8)
577 REG32(RB_DW14_REGISTER, 0x2140)
581 FIELD(RB_DW14_REGISTER, DATA_BYTES59, 0, 8)
582 REG32(RB_DW15_REGISTER, 0x2144)
586 FIELD(RB_DW15_REGISTER, DATA_BYTES63, 0, 8)
587 REG32(RB_ID_REGISTER_1, 0x4100)
592 FIELD(RB_ID_REGISTER_1, RTR_RRS, 0, 1)
593 REG32(RB_DLC_REGISTER_1, 0x4104)
599 FIELD(RB_DLC_REGISTER_1, TIMESTAMP, 0, 16)
600 REG32(RB0_DW0_REGISTER_1, 0x4108)
604 FIELD(RB0_DW0_REGISTER_1, DATA_BYTES3, 0, 8)
605 REG32(RB_DW1_REGISTER_1, 0x410c)
609 FIELD(RB_DW1_REGISTER_1, DATA_BYTES7, 0, 8)
610 REG32(RB_DW2_REGISTER_1, 0x4110)
614 FIELD(RB_DW2_REGISTER_1, DATA_BYTES11, 0, 8)
615 REG32(RB_DW3_REGISTER_1, 0x4114)
619 FIELD(RB_DW3_REGISTER_1, DATA_BYTES15, 0, 8)
620 REG32(RB_DW4_REGISTER_1, 0x4118)
624 FIELD(RB_DW4_REGISTER_1, DATA_BYTES19, 0, 8)
625 REG32(RB_DW5_REGISTER_1, 0x411c)
629 FIELD(RB_DW5_REGISTER_1, DATA_BYTES23, 0, 8)
630 REG32(RB_DW6_REGISTER_1, 0x4120)
634 FIELD(RB_DW6_REGISTER_1, DATA_BYTES27, 0, 8)
635 REG32(RB_DW7_REGISTER_1, 0x4124)
639 FIELD(RB_DW7_REGISTER_1, DATA_BYTES31, 0, 8)
640 REG32(RB_DW8_REGISTER_1, 0x4128)
644 FIELD(RB_DW8_REGISTER_1, DATA_BYTES35, 0, 8)
645 REG32(RB_DW9_REGISTER_1, 0x412c)
649 FIELD(RB_DW9_REGISTER_1, DATA_BYTES39, 0, 8)
650 REG32(RB_DW10_REGISTER_1, 0x4130)
654 FIELD(RB_DW10_REGISTER_1, DATA_BYTES43, 0, 8)
655 REG32(RB_DW11_REGISTER_1, 0x4134)
659 FIELD(RB_DW11_REGISTER_1, DATA_BYTES47, 0, 8)
660 REG32(RB_DW12_REGISTER_1, 0x4138)
664 FIELD(RB_DW12_REGISTER_1, DATA_BYTES51, 0, 8)
665 REG32(RB_DW13_REGISTER_1, 0x413c)
669 FIELD(RB_DW13_REGISTER_1, DATA_BYTES55, 0, 8)
670 REG32(RB_DW14_REGISTER_1, 0x4140)
674 FIELD(RB_DW14_REGISTER_1, DATA_BYTES59, 0, 8)
675 REG32(RB_DW15_REGISTER_1, 0x4144)
679 FIELD(RB_DW15_REGISTER_1, DATA_BYTES63, 0, 8)
684 s->regs[R_INTERRUPT_ENABLE_REGISTER]) != 0; in canfd_update_irq()
729 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXBOFLW_BI, 0); in canfd_icr_pre_write()
734 return 0; in canfd_icr_pre_write()
743 for (i = 0; i < R_RX_FIFO_WATERMARK_REGISTER; ++i) { in canfd_config_reset()
758 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, WKUP, 0); in canfd_config_mode()
759 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, SLP, 0); in canfd_config_mode()
760 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, BSOFF, 0); in canfd_config_mode()
761 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, ERROR_BIT, 0); in canfd_config_mode()
762 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFOFLW, 0); in canfd_config_mode()
763 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFOFLW_1, 0); in canfd_config_mode()
764 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 0); in canfd_config_mode()
765 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXOK, 0); in canfd_config_mode()
766 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, ARBLST, 0); in canfd_config_mode()
770 ptimer_set_count(s->canfd_timer, 0); in canfd_config_mode()
786 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 0); in update_status_register_mode_bits()
787 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 0); in update_status_register_mode_bits()
788 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 0); in update_status_register_mode_bits()
789 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, NORMAL, 0); in update_status_register_mode_bits()
818 uint8_t multi_mode = 0; in canfd_msr_pre_write()
834 if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) { in canfd_msr_pre_write()
844 " without setting CEN bit as 0\n"); in canfd_msr_pre_write()
847 " without setting CEN bit as 0\n"); in canfd_msr_pre_write()
858 ARRAY_FIELD_DP32(s->regs, MODE_SELECT_REGISTER, SLEEP, 0); in canfd_exit_sleep_mode()
865 uint32_t i = 0; in regs2frame()
866 uint32_t j = 0; in regs2frame()
867 uint32_t val = 0; in regs2frame()
868 uint32_t dlc_reg_val = 0; in regs2frame()
869 uint32_t dlc_value = 0; in regs2frame()
870 uint32_t id_reg_val = 0; in regs2frame()
873 frame->flags = 0; in regs2frame()
911 for (j = 0; j < frame->can_dlc; j++) { in regs2frame()
917 if (i % 4 == 0) { in regs2frame()
918 i = 0; in regs2frame()
936 uint32_t id_reg_val = 0; in frame_to_reg_id()
941 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, ID, in frame_to_reg_id()
943 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, ID_EXT, in frame_to_reg_id()
945 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, IDE, 1); in frame_to_reg_id()
946 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, SRR_RTR_RRS, 1); in frame_to_reg_id()
948 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, RTR_RRS, 1); in frame_to_reg_id()
951 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, ID, in frame_to_reg_id()
954 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, SRR_RTR_RRS, 1); in frame_to_reg_id()
969 uint8_t rx_reg_num = 0; in store_rx_sequential()
970 uint32_t dlc_reg_val = 0; in store_rx_sequential()
971 uint32_t data_reg_val = 0; in store_rx_sequential()
981 if (rx_fifo_id == 0) { in store_rx_sequential()
990 if (rx_timestamp == 0xFFFF) { in store_rx_sequential()
997 if (rx_fifo_id == 0) { in store_rx_sequential()
1013 dlc_reg_val = FIELD_DP32(0, RB_DLC_REGISTER, DLC, can_len2dlc(dlc)); in store_rx_sequential()
1016 dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, FDF, 1); in store_rx_sequential()
1019 dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, BRS, 1); in store_rx_sequential()
1022 dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, ESI, 1); in store_rx_sequential()
1026 dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, TIMESTAMP, rx_timestamp); in store_rx_sequential()
1027 dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, MATCHED_FILTER_INDEX, in store_rx_sequential()
1031 for (i = 0; i < dlc; i++) { in store_rx_sequential()
1034 case 0: in store_rx_sequential()
1037 data_reg_val = FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES0, in store_rx_sequential()
1041 data_reg_val |= FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES1, in store_rx_sequential()
1045 data_reg_val |= FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES2, in store_rx_sequential()
1049 data_reg_val |= FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES3, in store_rx_sequential()
1077 uint8_t filter_index = 0; in update_rx_sequential()
1084 uint8_t store_index = 0; in update_rx_sequential()
1087 * If all UAF bits are set to 0, then received messages are not stored in update_rx_sequential()
1095 for (i = 0; i < 32; i++) { in update_rx_sequential()
1096 if (acceptance_filter_status & 0x1) { in update_rx_sequential()
1155 store_location, s->cfg.rx0_fifo, 0, in update_rx_sequential()
1196 if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) { in tx_ready_check()
1224 uint32_t dlc_reg_val = 0; in tx_fifo_stamp()
1264 dlc_reg_val = FIELD_DP32(0, TXE_FIFO_TB_DLC_REGISTER, DLC, dlc_val); in tx_fifo_stamp()
1265 dlc_reg_val |= FIELD_DP32(0, TXE_FIFO_TB_DLC_REGISTER, FDF, in tx_fifo_stamp()
1267 dlc_reg_val |= FIELD_DP32(0, TXE_FIFO_TB_DLC_REGISTER, BRS, in tx_fifo_stamp()
1269 dlc_reg_val |= FIELD_DP32(0, TXE_FIFO_TB_DLC_REGISTER, ET, 0x3); in tx_fifo_stamp()
1270 dlc_reg_val |= FIELD_DP32(0, TXE_FIFO_TB_DLC_REGISTER, MM, mm_val); in tx_fifo_stamp()
1271 dlc_reg_val |= FIELD_DP32(0, TXE_FIFO_TB_DLC_REGISTER, TIMESTAMP, in tx_fifo_stamp()
1307 uint8_t i = 0; in prepare_tx_data()
1309 uint32_t reg_num = 0; in prepare_tx_data()
1313 for (i = 0; i < s->cfg.tx_fifo; i++) { in prepare_tx_data()
1327 s->regs[R_TX_BUFFER_READY_REQUEST_REGISTER] = 0; in prepare_tx_data()
1328 s->regs[R_TX_BUFFER_CANCEL_REQUEST_REGISTER] = 0; in prepare_tx_data()
1399 } else if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) { in canfd_srr_pre_write()
1407 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 0); in canfd_srr_pre_write()
1410 ptimer_set_count(s->canfd_timer, 0); in canfd_srr_pre_write()
1463 uint8_t read_ind = 0; in canfd_tx_fifo_status_prew()
1472 read_ind = 0; in canfd_tx_fifo_status_prew()
1491 uint8_t read_ind = 0; in canfd_rx_fifo_status_prew()
1492 uint8_t fill_ind = 0; in canfd_rx_fifo_status_prew()
1496 if (FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, FL) != 0) { in canfd_rx_fifo_status_prew()
1500 read_ind = 0; in canfd_rx_fifo_status_prew()
1512 if (FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, FL_1) != 0) { in canfd_rx_fifo_status_prew()
1516 read_ind = 0; in canfd_rx_fifo_status_prew()
1535 ARRAY_FIELD_DP32(s->regs, TIMESTAMP_REGISTER, TIMESTAMP_CNT, 0); in canfd_tsr_pre_write()
1537 ptimer_set_count(s->canfd_timer, 0); in canfd_tsr_pre_write()
1541 return 0; in canfd_tsr_pre_write()
1553 return 0; in canfd_trr_reg_prew()
1578 if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) { in canfd_write_check_prew()
1581 return 0; in canfd_write_check_prew()
1608 .ro = 0xffffffff,
1610 .ro = 0xfe1fffff,
1612 .ro = 0xffffffff,
1614 .ro = 0xffffffff,
1616 .ro = 0xffffffff,
1618 .ro = 0xffffffff,
1620 .ro = 0xffffffff,
1622 .ro = 0xffffffff,
1624 .ro = 0xffffffff,
1626 .ro = 0xffffffff,
1628 .ro = 0xffffffff,
1630 .ro = 0xffffffff,
1632 .ro = 0xffffffff,
1634 .ro = 0xffffffff,
1636 .ro = 0xffffffff,
1638 .ro = 0xffffffff,
1640 .ro = 0xffffffff,
1642 .ro = 0xffffffff,
1648 .ro = 0xffffffff,
1650 .ro = 0xfe1fffff,
1652 .ro = 0xffffffff,
1654 .ro = 0xffffffff,
1656 .ro = 0xffffffff,
1658 .ro = 0xffffffff,
1660 .ro = 0xffffffff,
1662 .ro = 0xffffffff,
1664 .ro = 0xffffffff,
1666 .ro = 0xffffffff,
1668 .ro = 0xffffffff,
1670 .ro = 0xffffffff,
1672 .ro = 0xffffffff,
1674 .ro = 0xffffffff,
1676 .ro = 0xffffffff,
1678 .ro = 0xffffffff,
1680 .ro = 0xffffffff,
1682 .ro = 0xffffffff,
1697 .ro = 0xffffffff,
1699 .ro = 0xffffffff,
1715 .ro = 0xffff,
1717 .w1c = 0xf1f,
1719 .reset = 0x1,
1720 .ro = 0x7f17ff,
1723 .ro = 0xffffff7f,
1730 .ro = 0xffff0000,
1751 .ro = 0x3f1f, .pre_write = canfd_tx_fifo_status_prew,
1754 .reset = 0xf,
1759 .ro = 0x7f3f7f3f, .pre_write = canfd_rx_fifo_status_prew,
1762 .reset = 0x1f0f0f,
1787 for (i = 0; i < ARRAY_SIZE(s->reg_info); ++i) { in canfd_reset()
1792 ptimer_set_count(s->canfd_timer, 0); in canfd_reset()
1815 assert(buf_size > 0); in canfd_xilinx_receive()
1844 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, BBSY, 0); in canfd_xilinx_receive()
1873 for (i = 0; i < num_rae; i++) { in canfd_populate_regarray()
1899 for (reg_num = 0; reg_num < num_template_to_copy; reg_num++) { in canfd_create_rai()
1905 for (i = 0; i < template_rai_array_sz; i++) { in canfd_create_rai()
1919 int pos = 0; in canfd_create_regarray()
1997 memory_region_add_subregion(&s->iomem, 0x00, ®_array->mem); in canfd_realize()
2002 if (xlnx_canfd_connect_to_bus(s, s->canfdbus) < 0) { in canfd_realize()
2021 ptimer_run(s->canfd_timer, 0); in canfd_realize()
2046 DEFINE_PROP_UINT8("rx-fifo0", XlnxVersalCANFDState, cfg.rx0_fifo, 0x40),
2047 DEFINE_PROP_UINT8("rx-fifo1", XlnxVersalCANFDState, cfg.rx1_fifo, 0x40),
2048 DEFINE_PROP_UINT8("tx-fifo", XlnxVersalCANFDState, cfg.tx_fifo, 0x20),