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/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dsnps,dw-apb-timer.yaml64 interrupts = <0 170 4>;
65 reg = <0xffe00000 0x1000>;
72 interrupts = <0 170 4>;
73 reg = <0xffe00000 0x1000>;
80 interrupts = <0 170 4>;
81 reg = <0xffe00000 0x1000>;
/openbmc/linux/net/netfilter/ipset/
H A Dpfxlen.c12 E(0x00000000, 0x00000000, 0x00000000, 0x00000000), \
13 E(0x80000000, 0x00000000, 0x00000000, 0x00000000), \
14 E(0xC0000000, 0x00000000, 0x00000000, 0x00000000), \
15 E(0xE0000000, 0x00000000, 0x00000000, 0x00000000), \
16 E(0xF0000000, 0x00000000, 0x00000000, 0x00000000), \
17 E(0xF8000000, 0x00000000, 0x00000000, 0x00000000), \
18 E(0xFC000000, 0x00000000, 0x00000000, 0x00000000), \
19 E(0xFE000000, 0x00000000, 0x00000000, 0x00000000), \
20 E(0xFF000000, 0x00000000, 0x00000000, 0x00000000), \
21 E(0xFF800000, 0x00000000, 0x00000000, 0x00000000), \
[all …]
/openbmc/u-boot/doc/
H A DREADME.ramboot-ppc85xx75 (CCSRBAR is at 0xff700000).
76 In the 2nd case bootloader has already re-located CCSRBAR to 0xffe00000
97 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xffe00000
99 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
/openbmc/u-boot/board/cobra5272/
H A DREADME39 link address 0xffe00000
84 #if 0
94 CONFIG_SYS_TEXT_BASE = 0xffe00000
133 CONFIG_SYS_TEXT_BASE = 0x00020000
/openbmc/u-boot/board/google/chromebook_samus/
H A DKconfig16 default 0xffe00000
27 default 0xf0000000
35 default 0xff7c0000
39 default 0x40000
/openbmc/u-boot/board/intel/cherryhill/
H A DKconfig16 default 0xffe00000
/openbmc/u-boot/board/intel/cougarcanyon2/
H A DKconfig16 default 0xffe00000
/openbmc/u-boot/configs/
H A DM5249EVB_defconfig2 CONFIG_SYS_TEXT_BASE=0xFFE00000
H A Dcobra5272_defconfig2 CONFIG_SYS_TEXT_BASE=0xFFE00000
H A DM5272C3_defconfig2 CONFIG_SYS_TEXT_BASE=0xFFE00000
H A DM5282EVB_defconfig2 CONFIG_SYS_TEXT_BASE=0xFFE00000
H A DM5275EVB_defconfig2 CONFIG_SYS_TEXT_BASE=0xFFE00000
H A DM5235EVB_defconfig2 CONFIG_SYS_TEXT_BASE=0xFFE00000
H A Dcherryhill_defconfig2 CONFIG_SYS_TEXT_BASE=0xFFE00000
3 CONFIG_DEBUG_UART_BASE=0x3f8
H A Dcougarcanyon2_defconfig2 CONFIG_SYS_TEXT_BASE=0xFFE00000
H A Dchromebook_samus_defconfig2 CONFIG_SYS_TEXT_BASE=0xFFE00000
3 CONFIG_SYS_MALLOC_F_LEN=0x1c00
5 CONFIG_DEBUG_UART_BASE=0x3f8
/openbmc/linux/arch/sh/kernel/cpu/sh4a/
H A Dserial-sh7722.c6 #define PSCR 0xA405011E
12 if (port->mapbase == 0xffe00000) { in sh7722_sci_init_pins()
14 data &= ~0x03cf; in sh7722_sci_init_pins()
16 data |= 0x0340; in sh7722_sci_init_pins()
/openbmc/u-boot/arch/sh/include/asm/
H A Dcpu_sh7763.h11 #define CCR 0xFF00001C
12 #define CCR_CACHE_INIT 0x0000090b
17 #define SCSMR0 0xFFE00000
21 #define SCSMR1 0xFFE08000
25 #define SCSMR2 0xFFE10000
29 #define WDTST 0xFFCC0000
32 #define TMU_BASE 0xFFD80000
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dbase_addr_s10.h9 #define SOCFPGA_CCU_ADDRESS 0xf7000000
10 #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400
11 #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000
12 #define SOCFPGA_SDR_ADDRESS 0xf8011000
13 #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100
14 #define SOCFPGA_SMMU_ADDRESS 0xfa000000
15 #define SOCFPGA_MAILBOX_ADDRESS 0xffa30000
16 #define SOCFPGA_UART0_ADDRESS 0xffc02000
17 #define SOCFPGA_UART1_ADDRESS 0xffc02100
18 #define SOCFPGA_SPTIMER0_ADDRESS 0xffc03000
[all …]
H A Dbase_addr_ac5.h9 #define SOCFPGA_FPGA_SLAVES_ADDRESS 0xc0000000
10 #define SOCFPGA_STM_ADDRESS 0xfc000000
11 #define SOCFPGA_DAP_ADDRESS 0xff000000
12 #define SOCFPGA_EMAC0_ADDRESS 0xff700000
13 #define SOCFPGA_EMAC1_ADDRESS 0xff702000
14 #define SOCFPGA_SDMMC_ADDRESS 0xff704000
15 #define SOCFPGA_QSPI_ADDRESS 0xff705000
16 #define SOCFPGA_GPIO0_ADDRESS 0xff708000
17 #define SOCFPGA_GPIO1_ADDRESS 0xff709000
18 #define SOCFPGA_GPIO2_ADDRESS 0xff70a000
[all …]
/openbmc/u-boot/arch/arm/mach-versal/include/mach/
H A Dhardware.h6 #define VERSAL_CRL_APB_BASEADDR 0xFF5E0000
17 u32 iou_switch_ctrl; /* 0x114 */
19 u32 timestamp_ref_ctrl; /* 0x14c */
23 u32 rst_timestamp; /* 0x348 */
28 #define VERSAL_IOU_SCNTR_SECURE 0xFF140000
33 u32 counter_control_register; /* 0x0 */
35 u32 base_frequency_id_register; /* 0x20 */
40 #define VERSAL_TCM_BASE_ADDR 0xFFE00000
41 #define VERSAL_TCM_SIZE 0x40000
43 #define VERSAL_RPU_BASEADDR 0xFF9A0000
[all …]
/openbmc/qemu/tests/tcg/arm/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffe00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffe00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
/openbmc/qemu/tests/tcg/loongarch64/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffe00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffe00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
/openbmc/qemu/tests/tcg/aarch64/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffe00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffe00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dp1020rdb.dts18 reg = <0 0xffe05000 0 0x1000>;
21 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
22 0x1 0x0 0x0 0xffa00000 0x00040000
23 0x2 0x0 0x0 0xffb00000 0x00020000>;
27 ranges = <0x0 0x0 0xffe00000 0x100000>;
31 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
32 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
33 reg = <0 0xffe09000 0 0x1000>;
34 pcie@0 {
35 ranges = <0x2000000 0x0 0xa0000000
[all …]

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