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/openbmc/u-boot/include/configs/
H A Damcore.h15 #define CONFIG_SYS_UART_PORT 0
21 "protect off 0xffc00000 0xffc1ffff; " \
22 "erase 0xffc00000 0xffc1ffff; " \
23 "cp.b 0x20000 0xffc00000 ${filesize}\0" \
25 "erase 0xffc20000 0xffefffff; " \
26 "cp.b 0x20000 0xffc20000 ${filesize}\0" \
28 "erase 0xfff00000 0xffffffff; " \
29 "cp.b 0x20000 0xfff00000 ${filesize}\0"
35 #define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */
37 #define CONFIG_SYS_MEMTEST_START 0x0
[all …]
H A DP1023RDB.h17 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
46 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
47 #define CONFIG_SYS_MEMTEST_END 0x02000000
50 #define CONFIG_SYS_LBC_LBCR 0x00000000
55 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
63 #define CONFIG_SYS_SPD_BUS_NUM 0
64 #define SPD_EEPROM_ADDRESS 0x50
70 * 0x0000_0000 0x1fff_ffff DDR 512M cacheable
71 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
72 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
[all …]
/openbmc/qemu/tests/tcg/ppc64le/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffc00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffc00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
/openbmc/qemu/tests/tcg/arm/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffe00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffe00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
/openbmc/qemu/tests/tcg/loongarch64/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffe00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffe00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
/openbmc/qemu/tests/tcg/aarch64/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffe00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffe00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
/openbmc/u-boot/doc/
H A DREADME.mpc85xx100 EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000
111 EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000
/openbmc/linux/arch/sh/include/cpu-sh4/cpu/
H A Dfreq.h14 #define FRQCR 0xa4150000
15 #define VCLKCR 0xa4150004
16 #define SCLKACR 0xa4150008
17 #define SCLKBCR 0xa415000c
18 #define IrDACLKCR 0xa4150010
19 #define MSTPCR0 0xa4150030
20 #define MSTPCR1 0xa4150034
21 #define MSTPCR2 0xa4150038
23 #define FRQCR 0xffc80000
24 #define OSCCR 0xffc80018
[all …]
/openbmc/qemu/tests/tcg/hexagon/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffffffff) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffffffff) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffffffff) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffffffff) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffffffff) flags=OK (1/1)
[all …]
/openbmc/linux/net/netfilter/ipset/
H A Dpfxlen.c12 E(0x00000000, 0x00000000, 0x00000000, 0x00000000), \
13 E(0x80000000, 0x00000000, 0x00000000, 0x00000000), \
14 E(0xC0000000, 0x00000000, 0x00000000, 0x00000000), \
15 E(0xE0000000, 0x00000000, 0x00000000, 0x00000000), \
16 E(0xF0000000, 0x00000000, 0x00000000, 0x00000000), \
17 E(0xF8000000, 0x00000000, 0x00000000, 0x00000000), \
18 E(0xFC000000, 0x00000000, 0x00000000, 0x00000000), \
19 E(0xFE000000, 0x00000000, 0x00000000, 0x00000000), \
20 E(0xFF000000, 0x00000000, 0x00000000, 0x00000000), \
21 E(0xFF800000, 0x00000000, 0x00000000, 0x00000000), \
[all …]
/openbmc/linux/drivers/gpu/drm/sun4i/
H A Dsun8i_csc.c26 0x000004A8, 0x00000000, 0x00000662, 0xFFFC8451,
27 0x000004A8, 0xFFFFFE6F, 0xFFFFFCC0, 0x00021E4D,
28 0x000004A8, 0x00000811, 0x00000000, 0xFFFBACA9,
31 0x000004A8, 0x00000000, 0x0000072B, 0xFFFC1F99,
32 0x000004A8, 0xFFFFFF26, 0xFFFFFDDF, 0x00013383,
33 0x000004A8, 0x00000873, 0x00000000, 0xFFFB7BEF,
38 0x00000400, 0x00000000, 0x0000059B, 0xFFFD322E,
39 0x00000400, 0xFFFFFEA0, 0xFFFFFD25, 0x00021DD5,
40 0x00000400, 0x00000716, 0x00000000, 0xFFFC74BD,
43 0x00000400, 0x00000000, 0x0000064C, 0xFFFCD9B4,
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dar956x_initvals.h41 {0x00009800, 0xafe68e30},
42 {0x00009804, 0xfd14e000},
43 {0x00009808, 0x9c0a9f6b},
44 {0x0000980c, 0x04900000},
45 {0x00009814, 0x0280c00a},
46 {0x00009818, 0x00000000},
47 {0x0000981c, 0x00020028},
48 {0x00009834, 0x6400a190},
49 {0x00009838, 0x0108ecff},
50 {0x0000983c, 0x14000600},
[all …]
/openbmc/u-boot/configs/
H A Damcore_defconfig2 CONFIG_SYS_TEXT_BASE=0xFFC00000
3 CONFIG_SYS_MALLOC_F_LEN=0x800
H A DM5235EVB_Flash32_defconfig2 CONFIG_SYS_TEXT_BASE=0xFFC00000
/openbmc/linux/drivers/mtd/maps/
H A Damd76xrom.c62 module_param(win_size_bits, uint, 0);
63 MODULE_PARM_DESC(win_size_bits, "ROM window size bits override for 0x43 byte, normally set by BIOS.…
76 pci_read_config_byte(window->pdev, 0x40, &byte); in amd76xrom_cleanup()
77 pci_write_config_byte(window->pdev, 0x40, byte & ~1); in amd76xrom_cleanup()
97 window->phys = 0; in amd76xrom_cleanup()
98 window->size = 0; in amd76xrom_cleanup()
123 pci_read_config_byte(pdev, 0x43, &byte); in amd76xrom_init_one()
124 pci_write_config_byte(pdev, 0x43, byte | win_size_bits ); in amd76xrom_init_one()
127 pci_read_config_byte(pdev, 0x43, &byte); in amd76xrom_init_one()
129 window->phys = 0xffb00000; /* 5MiB */ in amd76xrom_init_one()
[all …]
H A Dichxrom.c30 #define BIOS_CNTL 0x4e
31 #define FWH_DEC_EN1 0xE3
32 #define FWH_DEC_EN2 0xF0
33 #define FWH_SEL1 0xE8
34 #define FWH_SEL2 0xEE
83 window->phys = 0; in ichxrom_cleanup()
84 window->size = 0; in ichxrom_cleanup()
113 window->phys = 0; in ichxrom_init_one()
115 if (byte == 0xff) { in ichxrom_init_one()
116 window->phys = 0xffc00000; in ichxrom_init_one()
[all …]
H A Dck804xrom.c68 * byte @0x88: bit 0..7
69 * byte @0x8c: bit 8..15
70 * word @0x90: bit 16..30
72 * Please set win_size_bits to 0x7fffffff if you actually want to do something
74 static uint win_size_bits = 0;
75 module_param(win_size_bits, uint, 0);
89 pci_read_config_byte(window->pdev, 0x6d, &byte); in ck804xrom_cleanup()
90 pci_write_config_byte(window->pdev, 0x6d, byte & ~1); in ck804xrom_cleanup()
109 window->phys = 0; in ck804xrom_cleanup()
110 window->size = 0; in ck804xrom_cleanup()
[all …]
H A Desb2rom.c34 #define BIOS_CNTL 0xDC
35 #define BIOS_LOCK_ENABLE 0x02
36 #define BIOS_WRITE_ENABLE 0x01
39 #define FWH_DEC_EN1 0xD8
40 #define FWH_F8_EN 0x8000
41 #define FWH_F0_EN 0x4000
42 #define FWH_E8_EN 0x2000
43 #define FWH_E0_EN 0x1000
44 #define FWH_D8_EN 0x0800
45 #define FWH_D0_EN 0x0400
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dbase_addr_ac5.h9 #define SOCFPGA_FPGA_SLAVES_ADDRESS 0xc0000000
10 #define SOCFPGA_STM_ADDRESS 0xfc000000
11 #define SOCFPGA_DAP_ADDRESS 0xff000000
12 #define SOCFPGA_EMAC0_ADDRESS 0xff700000
13 #define SOCFPGA_EMAC1_ADDRESS 0xff702000
14 #define SOCFPGA_SDMMC_ADDRESS 0xff704000
15 #define SOCFPGA_QSPI_ADDRESS 0xff705000
16 #define SOCFPGA_GPIO0_ADDRESS 0xff708000
17 #define SOCFPGA_GPIO1_ADDRESS 0xff709000
18 #define SOCFPGA_GPIO2_ADDRESS 0xff70a000
[all …]
/openbmc/qemu/hw/hppa/
H A Dhppa_hardware.h7 #define FIRMWARE_START 0xf0000000
8 #define FIRMWARE_END 0xf0800000
10 #define DEVICE_HPA_LEN 0x00100000
12 #define GSC_HPA 0xffc00000
13 #define DINO_HPA 0xfff80000
14 #define DINO_UART_HPA 0xfff83000
15 #define DINO_UART_BASE 0xfff83800
16 #define DINO_SCSI_HPA 0xfff8c000
17 #define LASI_HPA 0xffd00000
18 #define LASI_UART_HPA 0xffd05000
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dp1020rdb.dts18 reg = <0 0xffe05000 0 0x1000>;
21 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
22 0x1 0x0 0x0 0xffa00000 0x00040000
23 0x2 0x0 0x0 0xffb00000 0x00020000>;
27 ranges = <0x0 0x0 0xffe00000 0x100000>;
31 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
32 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
33 reg = <0 0xffe09000 0 0x1000>;
34 pcie@0 {
35 ranges = <0x2000000 0x0 0xa0000000
[all …]
H A Dp1020rdb_36b.dts18 reg = <0xf 0xffe05000 0 0x1000>;
21 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
22 0x1 0x0 0xf 0xffa00000 0x00040000
23 0x2 0x0 0xf 0xffb00000 0x00020000>;
27 ranges = <0x0 0xf 0xffe00000 0x100000>;
31 reg = <0xf 0xffe09000 0 0x1000>;
32 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
33 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
34 pcie@0 {
35 ranges = <0x2000000 0x0 0xc0000000
[all …]
/openbmc/linux/net/ipv6/
H A Daddrconf_core.c42 st = addr->s6_addr32[0]; in __ipv6_addr_type()
47 if ((st & htonl(0xE0000000)) != htonl(0x00000000) && in __ipv6_addr_type()
48 (st & htonl(0xE0000000)) != htonl(0xE0000000)) in __ipv6_addr_type()
52 if ((st & htonl(0xFF000000)) == htonl(0xFF000000)) { in __ipv6_addr_type()
59 if ((st & htonl(0xFFC00000)) == htonl(0xFE800000)) in __ipv6_addr_type()
62 if ((st & htonl(0xFFC00000)) == htonl(0xFEC00000)) in __ipv6_addr_type()
65 if ((st & htonl(0xFE000000)) == htonl(0xFC000000)) in __ipv6_addr_type()
69 if ((addr->s6_addr32[0] | addr->s6_addr32[1]) == 0) { in __ipv6_addr_type()
70 if (addr->s6_addr32[2] == 0) { in __ipv6_addr_type()
71 if (addr->s6_addr32[3] == 0) in __ipv6_addr_type()
[all …]
/openbmc/linux/arch/sparc/include/asm/
H A Dvaddrs.h15 #define SRMMU_MAXMEM 0x0c000000
18 /* = 0x0fc000000 */
47 /* Leave one empty page between IO pages at 0xfd000000 and
50 #define FIXADDR_TOP (0xfcfff000UL)
56 #define SUN4M_IOBASE_VADDR 0xfd000000 /* Base for mapping pages */
57 #define IOBASE_VADDR 0xfe000000
58 #define IOBASE_END 0xfe600000
60 #define KADB_DEBUGGER_BEGVM 0xffc00000 /* Where kern debugger is in virt-mem */
61 #define KADB_DEBUGGER_ENDVM 0xffd00000
65 #define LINUX_OPPROM_BEGVM 0xffd00000
[all …]
/openbmc/linux/include/linux/phy/
H A Domap_control_phy.h35 USB_MODE_UNDEFINED = 0,
41 #define OMAP_CTRL_DEV_PHY_PD BIT(0)
43 #define OMAP_CTRL_DEV_AVALID BIT(0)
49 #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
50 #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE
52 #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000
53 #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16
55 #define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3
56 #define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0
58 #define OMAP_CTRL_PCIE_PCS_MASK 0xff
[all …]

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