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/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dbase_addr_ac5.h9 #define SOCFPGA_FPGA_SLAVES_ADDRESS 0xc0000000
10 #define SOCFPGA_STM_ADDRESS 0xfc000000
11 #define SOCFPGA_DAP_ADDRESS 0xff000000
12 #define SOCFPGA_EMAC0_ADDRESS 0xff700000
13 #define SOCFPGA_EMAC1_ADDRESS 0xff702000
14 #define SOCFPGA_SDMMC_ADDRESS 0xff704000
15 #define SOCFPGA_QSPI_ADDRESS 0xff705000
16 #define SOCFPGA_GPIO0_ADDRESS 0xff708000
17 #define SOCFPGA_GPIO1_ADDRESS 0xff709000
18 #define SOCFPGA_GPIO2_ADDRESS 0xff70a000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Ddenali,nand.yaml141 reg = <0xff900000 0x20>, <0xffb80000 0x1000>;
142 interrupts = <0 144 4>;
148 #size-cells = <0>;
150 nand@0 {
151 reg = <0>;
/openbmc/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi21 service_reserved: svcbuffer@0 {
23 reg = <0x0 0x0 0x0 0x1000000>;
24 alignment = <0x1000>;
31 #size-cells = <0>;
33 cpu0: cpu@0 {
37 reg = <0x0>;
44 reg = <0x1>;
51 reg = <0x2>;
58 reg = <0x3>;
64 interrupts = <0 170 4>,
[all …]
/openbmc/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex.dtsi22 service_reserved: svcbuffer@0 {
24 reg = <0x0 0x0 0x0 0x2000000>;
25 alignment = <0x1000>;
32 #size-cells = <0>;
34 cpu0: cpu@0 {
38 reg = <0x0>;
45 reg = <0x1>;
52 reg = <0x2>;
59 reg = <0x3>;
85 reg = <0x0 0xfffc1000 0x0 0x1000>,
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsocfpga.dtsi23 #size-cells = <0>;
26 cpu0: cpu@0 {
29 reg = <0>;
43 interrupts = <0 176 4>, <0 177 4>;
45 reg = <0xff111000 0x1000>,
46 <0xff113000 0x1000>;
53 reg = <0xfffed000 0x1000>,
54 <0xfffec100 0x100>;
73 reg = <0xffe01000 0x1000>;
74 interrupts = <0 104 4>,
[all …]
H A Dsocfpga_arria10.dtsi31 #size-cells = <0>;
34 cpu@0 {
37 reg = <0>;
52 reg = <0xffffd000 0x1000>,
53 <0xffffc100 0x100>;
73 reg = <0xffda1000 0x1000>;
74 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
75 <0 84 IRQ_TYPE_LEVEL_HIGH>,
76 <0 85 IRQ_TYPE_LEVEL_HIGH>,
77 <0 86 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/openbmc/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_arria10.dtsi15 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0>;
35 interrupts = <0 124 4>, <0 125 4>;
37 reg = <0xff111000 0x1000>,
38 <0xff113000 0x1000>;
45 reg = <0xffffd000 0x1000>,
46 <0xffffc100 0x100>;
65 reg = <0xffda1000 0x1000>;
66 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dsocfpga.dtsi23 #size-cells = <0>;
26 cpu0: cpu@0 {
29 reg = <0>;
43 interrupts = <0 176 4>, <0 177 4>;
45 reg = <0xff111000 0x1000>,
46 <0xff113000 0x1000>;
53 reg = <0xfffed000 0x1000>,
54 <0xfffec100 0x100>;
73 reg = <0xffe01000 0x1000>;
74 interrupts = <0 104 4>,
[all …]