Lines Matching +full:0 +full:xffb80000
23 #size-cells = <0>;
26 cpu0: cpu@0 {
29 reg = <0>;
43 interrupts = <0 176 4>, <0 177 4>;
45 reg = <0xff111000 0x1000>,
46 <0xff113000 0x1000>;
53 reg = <0xfffed000 0x1000>,
54 <0xfffec100 0x100>;
73 reg = <0xffe01000 0x1000>;
74 interrupts = <0 104 4>,
75 <0 105 4>,
76 <0 106 4>,
77 <0 107 4>,
78 <0 108 4>,
79 <0 109 4>,
80 <0 110 4>,
81 <0 111 4>;
94 #address-cells = <0x1>;
95 #size-cells = <0x1>;
100 reg = <0xffc00000 0x1000>;
101 interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
108 reg = <0xffc01000 0x1000>;
109 interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
116 reg = <0xffd04000 0x1000>;
120 #size-cells = <0>;
123 #clock-cells = <0>;
128 #clock-cells = <0>;
133 #clock-cells = <0>;
138 #clock-cells = <0>;
144 #size-cells = <0>;
145 #clock-cells = <0>;
148 reg = <0x40>;
151 #clock-cells = <0>;
154 div-reg = <0xe0 0 9>;
155 reg = <0x48>;
159 #clock-cells = <0>;
162 div-reg = <0xe4 0 9>;
163 reg = <0x4C>;
167 #clock-cells = <0>;
170 div-reg = <0xe8 0 9>;
171 reg = <0x50>;
175 #clock-cells = <0>;
178 reg = <0x54>;
182 #clock-cells = <0>;
185 reg = <0x58>;
189 #clock-cells = <0>;
192 reg = <0x5C>;
198 #size-cells = <0>;
199 #clock-cells = <0>;
202 reg = <0x80>;
205 #clock-cells = <0>;
208 reg = <0x88>;
212 #clock-cells = <0>;
215 reg = <0x8C>;
219 #clock-cells = <0>;
222 reg = <0x90>;
226 #clock-cells = <0>;
229 reg = <0x94>;
233 #clock-cells = <0>;
236 reg = <0x98>;
240 #clock-cells = <0>;
243 reg = <0x9C>;
249 #size-cells = <0>;
250 #clock-cells = <0>;
253 reg = <0xC0>;
256 #clock-cells = <0>;
259 reg = <0xC8>;
263 #clock-cells = <0>;
266 reg = <0xCC>;
270 #clock-cells = <0>;
273 reg = <0xD0>;
277 #clock-cells = <0>;
280 reg = <0xD4>;
285 #clock-cells = <0>;
292 #clock-cells = <0>;
299 #clock-cells = <0>;
302 clk-gate = <0x60 0>;
306 #clock-cells = <0>;
313 #clock-cells = <0>;
316 div-reg = <0x64 0 2>;
317 clk-gate = <0x60 1>;
321 #clock-cells = <0>;
324 div-reg = <0x64 2 2>;
328 #clock-cells = <0>;
331 div-reg = <0x64 4 3>;
332 clk-gate = <0x60 2>;
336 #clock-cells = <0>;
339 div-reg = <0x64 7 3>;
340 clk-gate = <0x60 3>;
344 #clock-cells = <0>;
347 div-reg = <0x68 0 2>;
348 clk-gate = <0x60 4>;
352 #clock-cells = <0>;
355 div-reg = <0x68 2 2>;
356 clk-gate = <0x60 5>;
360 #clock-cells = <0>;
363 div-reg = <0x6C 0 3>;
364 clk-gate = <0x60 6>;
368 #clock-cells = <0>;
371 clk-gate = <0x60 7>;
375 #clock-cells = <0>;
378 clk-gate = <0x60 8>;
382 #clock-cells = <0>;
385 clk-gate = <0x60 9>;
389 #clock-cells = <0>;
392 clk-gate = <0xa0 0>;
396 #clock-cells = <0>;
399 clk-gate = <0xa0 1>;
403 #clock-cells = <0>;
406 clk-gate = <0xa0 2>;
407 div-reg = <0xa4 0 3>;
411 #clock-cells = <0>;
414 clk-gate = <0xa0 3>;
415 div-reg = <0xa4 3 3>;
419 #clock-cells = <0>;
422 clk-gate = <0xa0 4>;
423 div-reg = <0xa4 6 3>;
427 #clock-cells = <0>;
430 clk-gate = <0xa0 5>;
431 div-reg = <0xa4 9 3>;
435 #clock-cells = <0>;
438 clk-gate = <0xa0 6>;
439 div-reg = <0xa8 0 24>;
443 #clock-cells = <0>;
446 clk-gate = <0xa0 7>;
450 #clock-cells = <0>;
453 clk-gate = <0xa0 8>;
454 clk-phase = <0 135>;
458 #clock-cells = <0>;
461 clk-gate = <0xa0 8>;
466 #clock-cells = <0>;
469 clk-gate = <0xa0 9>;
473 #clock-cells = <0>;
476 clk-gate = <0xa0 9>;
480 #clock-cells = <0>;
483 clk-gate = <0xa0 10>;
488 #clock-cells = <0>;
491 clk-gate = <0xa0 11>;
495 #clock-cells = <0>;
498 clk-gate = <0xd8 0>;
502 #clock-cells = <0>;
505 clk-gate = <0xd8 1>;
509 #clock-cells = <0>;
512 clk-gate = <0xd8 2>;
516 #clock-cells = <0>;
519 clk-gate = <0xd8 3>;
527 reg = <0xff400000 0x100000>;
534 reg = <0xff500000 0x10000>;
541 reg = <0xff706000 0x1000
542 0xffb90000 0x4>;
543 interrupts = <0 175 4>;
548 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
549 reg = <0xff700000 0x2000>;
550 interrupts = <0 115 4>;
566 altr,sysmgr-syscon = <&sysmgr 0x60 2>;
567 reg = <0xff702000 0x2000>;
568 interrupts = <0 120 4>;
584 #size-cells = <0>;
586 reg = <0xff708000 0x1000>;
590 porta: gpio-controller@0 {
595 reg = <0>;
598 interrupts = <0 164 4>;
604 #size-cells = <0>;
606 reg = <0xff709000 0x1000>;
610 portb: gpio-controller@0 {
615 reg = <0>;
618 interrupts = <0 165 4>;
624 #size-cells = <0>;
626 reg = <0xff70a000 0x1000>;
630 portc: gpio-controller@0 {
635 reg = <0>;
638 interrupts = <0 166 4>;
644 #size-cells = <0>;
646 reg = <0xffc04000 0x1000>;
649 interrupts = <0 158 0x4>;
655 #size-cells = <0>;
657 reg = <0xffc05000 0x1000>;
660 interrupts = <0 159 0x4>;
666 #size-cells = <0>;
668 reg = <0xffc06000 0x1000>;
671 interrupts = <0 160 0x4>;
677 #size-cells = <0>;
679 reg = <0xffc07000 0x1000>;
682 interrupts = <0 161 0x4>;
694 reg = <0xffd08140 0x4>;
695 interrupts = <0 36 1>, <0 37 1>;
700 reg = <0xffd08144 0x4>;
702 interrupts = <0 178 1>, <0 179 1>;
708 reg = <0xfffef000 0x1000>;
709 interrupts = <0 38 0x04>;
718 arm,double-linefill-incr = <0>;
720 arm,prefetch-drop = <0>;
724 l3regs@0xff800000 {
726 reg = <0xff800000 0x1000>;
731 reg = <0xff704000 0x1000>;
732 interrupts = <0 139 4>;
733 fifo-depth = <0x400>;
735 #size-cells = <0>;
742 #address-cells = <0x1>;
743 #size-cells = <0x1>;
745 reg = <0xff900000 0x100000>,
746 <0xffb80000 0x10000>;
748 interrupts = <0x0 0x90 0x4>;
749 dma-mask = <0xffffffff>;
757 reg = <0xffff0000 0x10000>;
763 #size-cells = <0>;
764 reg = <0xff705000 0x1000>,
765 <0xffa00000 0x1000>;
766 interrupts = <0 151 4>;
769 cdns,trigger-address = <0x00000000>;
777 reg = <0xffd05000 0x1000>;
778 altr,modrst-offset = <0x10>;
783 reg = <0xfffec000 0x100>;
788 reg = <0xffc25000 0x1000>;
794 interrupts = <0 39 4>;
800 #size-cells = <0>;
801 reg = <0xfff00000 0x1000>;
802 interrupts = <0 154 4>;
811 #size-cells = <0>;
812 reg = <0xfff01000 0x1000>;
813 interrupts = <0 155 4>;
821 reg = <0xffd08000 0x4000>;
827 reg = <0xfffec600 0x100>;
828 interrupts = <1 13 0xf01>;
834 interrupts = <0 167 4>;
835 reg = <0xffc08000 0x1000>;
844 interrupts = <0 168 4>;
845 reg = <0xffc09000 0x1000>;
854 interrupts = <0 169 4>;
855 reg = <0xffd00000 0x1000>;
864 interrupts = <0 170 4>;
865 reg = <0xffd01000 0x1000>;
874 reg = <0xffc02000 0x1000>;
875 interrupts = <0 162 4>;
886 reg = <0xffc03000 0x1000>;
887 interrupts = <0 163 4>;
897 #phy-cells = <0>;
904 reg = <0xffb00000 0xffff>;
905 interrupts = <0 125 4>;
917 reg = <0xffb40000 0xffff>;
918 interrupts = <0 128 4>;
930 reg = <0xffd02000 0x1000>;
931 interrupts = <0 171 4>;
938 reg = <0xffd03000 0x1000>;
939 interrupts = <0 172 4>;