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/openbmc/linux/Documentation/devicetree/bindings/power/
H A Drockchip,power-controller.yaml54 const: 0
63 "^power-domain@[0-9a-f]+$":
74 const: 0
77 "^power-domain@[0-9a-f]+$":
88 const: 0
91 "^power-domain@[0-9a-f]+$":
99 const: 0
143 enum: [0, 1]
145 Must be 0 for nodes representing a single PM domain and 1 for nodes
163 reg = <0x0 0xffa90000 0x0 0x20>;
[all …]
/openbmc/qemu/hw/arm/
H A Dxlnx-zynqmp.c39 #define GEM_REVISION 0x40070106
41 #define GIC_BASE_ADDR 0xf9000000
42 #define GIC_DIST_ADDR 0xf9010000
43 #define GIC_CPU_ADDR 0xf9020000
44 #define GIC_VIFACE_ADDR 0xf9040000
45 #define GIC_VCPU_ADDR 0xf9060000
48 #define SATA_ADDR 0xFD0C0000
51 #define QSPI_ADDR 0xff0f0000
52 #define LQSPI_ADDR 0xc0000000
54 #define QSPI_DMA_ADDR 0xff0f0800
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp.dtsi22 #size-cells = <0>;
24 cpu0: cpu@0 {
29 reg = <0x0>;
37 reg = <0x1>;
46 reg = <0x2>;
55 reg = <0x3>;
63 CPU_SLEEP_0: cpu-sleep-0 {
65 arm,psci-suspend-param = <0x40000000>;
108 interrupts = <0 143 4>,
109 <0 144 4>,
[all …]
H A Drk3399.dtsi43 #size-cells = <0>;
71 cpu_l0: cpu@0 {
74 reg = <0x0 0x0>;
83 reg = <0x0 0x1>;
91 reg = <0x0 0x2>;
99 reg = <0x0 0x3>;
107 reg = <0x0 0x100>;
116 reg = <0x0 0x101>;
139 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
140 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
[all …]
/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp.dtsi29 #size-cells = <0>;
31 cpu0: cpu@0 {
36 reg = <0x0>;
45 reg = <0x1>;
55 reg = <0x2>;
65 reg = <0x3>;
80 CPU_SLEEP_0: cpu-sleep-0 {
82 arm,psci-suspend-param = <0x40000000>;
123 reg = <0x0 0x3ed00000 0x0 0x40000>;
128 reg = <0x0 0x3ef00000 0x0 0x40000>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399.dtsi41 #size-cells = <0>;
69 cpu_l0: cpu@0 {
72 reg = <0x0 0x0>;
84 reg = <0x0 0x1>;
96 reg = <0x0 0x2>;
108 reg = <0x0 0x3>;
120 reg = <0x0 0x100>;
138 reg = <0x0 0x101>;
159 arm,psci-suspend-param = <0x0010000>;
168 arm,psci-suspend-param = <0x1010000>;
[all …]