Searched +full:0 +full:xff800800 (Results 1 – 3 of 3) sorted by relevance
42 const: 077 reg = <0xff800800 0xdc>;80 #size-cells = <0>;82 led@0 {83 reg = <0x0>;90 reg = <0x3>;
14 #define RWDT_BASE 0xE602000015 #define SWDT_BASE 0xE603000016 #define LBSC_BASE 0xFEC0020017 #define DBSC3_0_BASE 0xE679000018 #define DBSC3_1_BASE 0xE67A000019 #define TMU_BASE 0xE61E000020 #define GPIO5_BASE 0xE605500021 #define SH_QSPI_BASE 0xE6B1000024 #define SCIF0_BASE 0xE6E6000025 #define SCIF1_BASE 0xE6E68000[all …]
30 * 0 = Rtt disabled35 * 0 = Rtt disabled48 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {62 rtt = 0; in fsl_ddr_get_rtt()66 rtt = 0; in fsl_ddr_get_rtt()152 unsigned int cs_n_en = 0; /* Chip Select enable */ in set_csn_config()153 unsigned int intlv_en = 0; /* Memory controller interleave enable */ in set_csn_config()154 unsigned int intlv_ctl = 0; /* Interleaving control */ in set_csn_config()155 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */ in set_csn_config()156 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */ in set_csn_config()[all …]