Lines Matching +full:0 +full:xff800800
30 * 0 = Rtt disabled
35 * 0 = Rtt disabled
48 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
62 rtt = 0; in fsl_ddr_get_rtt()
66 rtt = 0; in fsl_ddr_get_rtt()
152 unsigned int cs_n_en = 0; /* Chip Select enable */ in set_csn_config()
153 unsigned int intlv_en = 0; /* Memory controller interleave enable */ in set_csn_config()
154 unsigned int intlv_ctl = 0; /* Interleaving control */ in set_csn_config()
155 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */ in set_csn_config()
156 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */ in set_csn_config()
157 unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */ in set_csn_config()
158 unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */ in set_csn_config()
159 unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */ in set_csn_config()
160 unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */ in set_csn_config()
161 int go_config = 0; in set_csn_config()
163 unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */ in set_csn_config()
170 case 0: in set_csn_config()
171 if (dimm_params[dimm_number].n_ranks > 0) { in set_csn_config()
191 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \ in set_csn_config()
192 (dimm_number == 1 && dimm_params[1].n_ranks > 0)) in set_csn_config()
196 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \ in set_csn_config()
197 (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0)) in set_csn_config()
201 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \ in set_csn_config()
203 (dimm_number == 3 && dimm_params[3].n_ranks > 0)) in set_csn_config()
225 ddr->cs[i].config = (0 in set_csn_config()
226 | ((cs_n_en & 0x1) << 31) in set_csn_config()
227 | ((intlv_en & 0x3) << 29) in set_csn_config()
228 | ((intlv_ctl & 0xf) << 24) in set_csn_config()
229 | ((ap_n_en & 0x1) << 23) in set_csn_config()
232 | ((odt_rd_cfg & 0x7) << 20) in set_csn_config()
235 | ((odt_wr_cfg & 0x7) << 16) in set_csn_config()
237 | ((ba_bits_cs_n & 0x3) << 14) in set_csn_config()
238 | ((row_bits_cs_n & 0x7) << 8) in set_csn_config()
240 | ((bg_bits_cs_n & 0x3) << 4) in set_csn_config()
242 | ((col_bits_cs_n & 0x7) << 0) in set_csn_config()
244 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config); in set_csn_config()
251 unsigned int pasr_cfg = 0; /* Partial array self refresh config */ in set_csn_config_2()
254 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2); in set_csn_config_2()
262 * Return 1 if other two slots configuration. Return 0 if single slot.
267 if (dimm_params[0].n_ranks == 4) in avoid_odt_overlap()
272 if ((dimm_params[0].n_ranks == 2) && in avoid_odt_overlap()
277 if (dimm_params[0].n_ranks == 4) in avoid_odt_overlap()
281 if ((dimm_params[0].n_ranks != 0) && in avoid_odt_overlap()
282 (dimm_params[2].n_ranks != 0)) in avoid_odt_overlap()
285 return 0; in avoid_odt_overlap()
289 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
299 unsigned char trwt_mclk = 0; /* Read-to-write turnaround */ in set_timing_cfg_0()
300 unsigned char twrt_mclk = 0; /* Write-to-read turnaround */ in set_timing_cfg_0()
301 /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */ in set_timing_cfg_0()
302 unsigned char trrt_mclk = 0; /* Read-to-read turnaround */ in set_timing_cfg_0()
303 unsigned char twwt_mclk = 0; /* Write-to-write turnaround */ in set_timing_cfg_0()
310 unsigned char taxpd_mclk = 0; in set_timing_cfg_0()
338 trrt_mclk = 0; in set_timing_cfg_0()
366 if (ip_rev >= 0x40700) { in set_timing_cfg_0()
399 trrt_mclk = 0; in set_timing_cfg_0()
411 if (popts->dynamic_power == 0) { /* powerdown is not used */ in set_timing_cfg_0()
438 ddr->timing_cfg_0 = (0 in set_timing_cfg_0()
439 | ((trwt_mclk & 0x3) << 30) /* RWT */ in set_timing_cfg_0()
440 | ((twrt_mclk & 0x3) << 28) /* WRT */ in set_timing_cfg_0()
441 | ((trrt_mclk & 0x3) << 26) /* RRT */ in set_timing_cfg_0()
442 | ((twwt_mclk & 0x3) << 24) /* WWT */ in set_timing_cfg_0()
443 | ((act_pd_exit_mclk & 0xf) << 20) /* ACT_PD_EXIT */ in set_timing_cfg_0()
444 | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */ in set_timing_cfg_0()
445 | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */ in set_timing_cfg_0()
446 | ((tmrd_mclk & 0x1f) << 0) /* MRS_CYC */ in set_timing_cfg_0()
448 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); in set_timing_cfg_0()
461 unsigned int ext_pretoact = 0; in set_timing_cfg_3()
463 unsigned int ext_acttopre = 0; in set_timing_cfg_3()
465 unsigned int ext_acttorw = 0; in set_timing_cfg_3()
469 unsigned int ext_caslat = 0; in set_timing_cfg_3()
471 unsigned int ext_add_lat = 0; in set_timing_cfg_3()
473 unsigned int ext_wrrec = 0; in set_timing_cfg_3()
475 unsigned int cntl_adj = 0; in set_timing_cfg_3()
489 (popts->otf_burst_chop_en ? 2 : 0)) >> 4; in set_timing_cfg_3()
491 ddr->timing_cfg_3 = (0 in set_timing_cfg_3()
492 | ((ext_pretoact & 0x1) << 28) in set_timing_cfg_3()
493 | ((ext_acttopre & 0x3) << 24) in set_timing_cfg_3()
494 | ((ext_acttorw & 0x1) << 22) in set_timing_cfg_3()
495 | ((ext_refrec & 0x3F) << 16) in set_timing_cfg_3()
496 | ((ext_caslat & 0x3) << 12) in set_timing_cfg_3()
497 | ((ext_add_lat & 0x1) << 10) in set_timing_cfg_3()
498 | ((ext_wrrec & 0x1) << 8) in set_timing_cfg_3()
499 | ((cntl_adj & 0x7) << 0) in set_timing_cfg_3()
501 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3); in set_timing_cfg_3()
538 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0}; in set_timing_cfg_1()
551 * 1.0 0 0001 in set_timing_cfg_1()
562 caslat_ctrl = (cas_latency + 1) & 0x07; in set_timing_cfg_1()
571 if (fsl_ddr_get_version(ctrl_num) <= 0x40400) in set_timing_cfg_1()
619 ddr->timing_cfg_1 = (0 in set_timing_cfg_1()
620 | ((pretoact_mclk & 0x0F) << 28) in set_timing_cfg_1()
621 | ((acttopre_mclk & 0x0F) << 24) in set_timing_cfg_1()
622 | ((acttorw_mclk & 0xF) << 20) in set_timing_cfg_1()
623 | ((caslat_ctrl & 0xF) << 16) in set_timing_cfg_1()
624 | ((refrec_ctrl & 0xF) << 12) in set_timing_cfg_1()
625 | ((wrrec_mclk & 0x0F) << 8) in set_timing_cfg_1()
626 | ((acttoact_mclk & 0x0F) << 4) in set_timing_cfg_1()
627 | ((wrtord_mclk & 0x0F) << 0) in set_timing_cfg_1()
629 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1); in set_timing_cfg_1()
666 * otherwise unused ACSM field. If we leave it 0, then in set_timing_cfg_2()
669 wr_lat = 0; in set_timing_cfg_2()
696 cpo = 0; in set_timing_cfg_2()
712 ddr->timing_cfg_2 = (0 in set_timing_cfg_2()
713 | ((add_lat_mclk & 0xf) << 28) in set_timing_cfg_2()
714 | ((cpo & 0x1f) << 23) in set_timing_cfg_2()
715 | ((wr_lat & 0xf) << 19) in set_timing_cfg_2()
716 | (((wr_lat & 0x10) >> 4) << 18) in set_timing_cfg_2()
719 | ((cke_pls & 0x7) << 6) in set_timing_cfg_2()
720 | ((four_act & 0x3f) << 0) in set_timing_cfg_2()
722 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); in set_timing_cfg_2()
741 rc0a = ddr_freq > 3200 ? 0x7 : in set_ddr_sdram_rcw()
742 (ddr_freq > 2933 ? 0x6 : in set_ddr_sdram_rcw()
743 (ddr_freq > 2666 ? 0x5 : in set_ddr_sdram_rcw()
744 (ddr_freq > 2400 ? 0x4 : in set_ddr_sdram_rcw()
745 (ddr_freq > 2133 ? 0x3 : in set_ddr_sdram_rcw()
746 (ddr_freq > 1866 ? 0x2 : in set_ddr_sdram_rcw()
747 (ddr_freq > 1600 ? 1 : 0)))))); in set_ddr_sdram_rcw()
748 rc0f = ddr_freq > 3200 ? 0x3 : in set_ddr_sdram_rcw()
749 (ddr_freq > 2400 ? 0x2 : in set_ddr_sdram_rcw()
750 (ddr_freq > 2133 ? 0x1 : 0)); in set_ddr_sdram_rcw()
752 common_dimm->rcw[0] << 28 | \ in set_ddr_sdram_rcw()
772 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", in set_ddr_sdram_rcw()
774 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", in set_ddr_sdram_rcw()
776 debug("FSLDDR: ddr_sdram_rcw_3 = 0x%08x\n", in set_ddr_sdram_rcw()
793 unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */ in set_ddr_sdram_cfg()
794 unsigned int ncap = 0; /* Non-concurrent auto-precharge */ in set_ddr_sdram_cfg()
798 unsigned int x32_en = 0; /* x32 enable */ in set_ddr_sdram_cfg()
799 unsigned int pchb8 = 0; /* precharge bit 8 enable */ in set_ddr_sdram_cfg()
801 unsigned int acc_ecc_en = 0; /* Accumulated ECC enable */ in set_ddr_sdram_cfg()
802 unsigned int mem_halt = 0; /* memory controller halt */ in set_ddr_sdram_cfg()
803 unsigned int bi = 0; /* Bypass initialization */ in set_ddr_sdram_cfg()
811 ecc_en = 0; in set_ddr_sdram_cfg()
817 twot_en = 0; in set_ddr_sdram_cfg()
819 rd_en = 0; in set_ddr_sdram_cfg()
836 eight_be = 0; in set_ddr_sdram_cfg()
837 if (dbw == 0x1) in set_ddr_sdram_cfg()
846 acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0; in set_ddr_sdram_cfg()
848 ddr->ddr_sdram_cfg = (0 in set_ddr_sdram_cfg()
849 | ((mem_en & 0x1) << 31) in set_ddr_sdram_cfg()
850 | ((sren & 0x1) << 30) in set_ddr_sdram_cfg()
851 | ((ecc_en & 0x1) << 29) in set_ddr_sdram_cfg()
852 | ((rd_en & 0x1) << 28) in set_ddr_sdram_cfg()
853 | ((sdram_type & 0x7) << 24) in set_ddr_sdram_cfg()
854 | ((dyn_pwr & 0x1) << 21) in set_ddr_sdram_cfg()
855 | ((dbw & 0x3) << 19) in set_ddr_sdram_cfg()
856 | ((eight_be & 0x1) << 18) in set_ddr_sdram_cfg()
857 | ((ncap & 0x1) << 17) in set_ddr_sdram_cfg()
858 | ((threet_en & 0x1) << 16) in set_ddr_sdram_cfg()
859 | ((twot_en & 0x1) << 15) in set_ddr_sdram_cfg()
860 | ((ba_intlv_ctl & 0x7F) << 8) in set_ddr_sdram_cfg()
861 | ((x32_en & 0x1) << 5) in set_ddr_sdram_cfg()
862 | ((pchb8 & 0x1) << 4) in set_ddr_sdram_cfg()
863 | ((hse & 0x1) << 3) in set_ddr_sdram_cfg()
864 | ((acc_ecc_en & 0x1) << 2) in set_ddr_sdram_cfg()
865 | ((mem_halt & 0x1) << 1) in set_ddr_sdram_cfg()
866 | ((bi & 0x1) << 0) in set_ddr_sdram_cfg()
868 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg); in set_ddr_sdram_cfg()
877 unsigned int frc_sr = 0; /* Force self refresh */ in set_ddr_sdram_cfg_2()
878 unsigned int sr_ie = 0; /* Self-refresh interrupt enable */ in set_ddr_sdram_cfg_2()
879 unsigned int odt_cfg = 0; /* ODT configuration */ in set_ddr_sdram_cfg_2()
881 unsigned int slow = 0; /* DDR will be run less than 1250 */ in set_ddr_sdram_cfg_2()
882 unsigned int x4_en = 0; /* x4 DRAM enable */ in set_ddr_sdram_cfg_2()
886 unsigned int rcw_en = 0; /* Register Control Word Enable */ in set_ddr_sdram_cfg_2()
887 unsigned int md_en = 0; /* Mirrored DIMM Enable */ in set_ddr_sdram_cfg_2()
888 unsigned int qd_en = 0; /* quad-rank DIMM Enable */ in set_ddr_sdram_cfg_2()
896 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { in set_ddr_sdram_cfg_2()
916 obc_cfg = 0; in set_ddr_sdram_cfg_2()
929 ap_en = 0; in set_ddr_sdram_cfg_2()
934 x4_en = popts->x4_en ? 1 : 0; in set_ddr_sdram_cfg_2()
940 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init); in set_ddr_sdram_cfg_2()
943 d_init = 0; in set_ddr_sdram_cfg_2()
949 qd_en = popts->quad_rank_present ? 1 : 0; in set_ddr_sdram_cfg_2()
950 ddr->ddr_sdram_cfg_2 = (0 in set_ddr_sdram_cfg_2()
951 | ((frc_sr & 0x1) << 31) in set_ddr_sdram_cfg_2()
952 | ((sr_ie & 0x1) << 30) in set_ddr_sdram_cfg_2()
954 | ((dll_rst_dis & 0x1) << 29) in set_ddr_sdram_cfg_2()
955 | ((dqs_cfg & 0x3) << 26) in set_ddr_sdram_cfg_2()
957 | ((odt_cfg & 0x3) << 21) in set_ddr_sdram_cfg_2()
958 | ((num_pr & 0xf) << 12) in set_ddr_sdram_cfg_2()
963 | ((obc_cfg & 0x1) << 6) in set_ddr_sdram_cfg_2()
964 | ((ap_en & 0x1) << 5) in set_ddr_sdram_cfg_2()
965 | ((d_init & 0x1) << 4) in set_ddr_sdram_cfg_2()
966 | ((rcw_en & 0x1) << 2) in set_ddr_sdram_cfg_2()
967 | ((md_en & 0x1) << 0) in set_ddr_sdram_cfg_2()
969 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2); in set_ddr_sdram_cfg_2()
980 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ in set_ddr_sdram_mode_2()
981 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ in set_ddr_sdram_mode_2()
983 unsigned int wr_crc = 0; /* Disable */ in set_ddr_sdram_mode_2()
984 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ in set_ddr_sdram_mode_2()
985 unsigned int srt = 0; /* self-refresh temerature, normal range */ in set_ddr_sdram_mode_2()
987 unsigned int mpr = 0; /* serial */ in set_ddr_sdram_mode_2()
994 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr; in set_ddr_sdram_mode_2()
999 esdmode2 = (0 in set_ddr_sdram_mode_2()
1000 | ((wr_crc & 0x1) << 12) in set_ddr_sdram_mode_2()
1001 | ((rtt_wr & 0x3) << 9) in set_ddr_sdram_mode_2()
1002 | ((srt & 0x3) << 6) in set_ddr_sdram_mode_2()
1003 | ((cwl & 0x7) << 3)); in set_ddr_sdram_mode_2()
1006 wc_lat = 0; in set_ddr_sdram_mode_2()
1012 esdmode3 = (0 in set_ddr_sdram_mode_2()
1013 | ((mpr & 0x3) << 11) in set_ddr_sdram_mode_2()
1014 | ((wc_lat & 0x3) << 9)); in set_ddr_sdram_mode_2()
1016 ddr->ddr_sdram_mode_2 = (0 in set_ddr_sdram_mode_2()
1017 | ((esdmode2 & 0xFFFF) << 16) in set_ddr_sdram_mode_2()
1018 | ((esdmode3 & 0xFFFF) << 0) in set_ddr_sdram_mode_2()
1020 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); in set_ddr_sdram_mode_2()
1029 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */ in set_ddr_sdram_mode_2()
1030 esdmode2 |= (rtt_wr & 0x3) << 9; in set_ddr_sdram_mode_2()
1033 ddr->ddr_sdram_mode_4 = (0 in set_ddr_sdram_mode_2()
1034 | ((esdmode2 & 0xFFFF) << 16) in set_ddr_sdram_mode_2()
1035 | ((esdmode3 & 0xFFFF) << 0) in set_ddr_sdram_mode_2()
1039 ddr->ddr_sdram_mode_6 = (0 in set_ddr_sdram_mode_2()
1040 | ((esdmode2 & 0xFFFF) << 16) in set_ddr_sdram_mode_2()
1041 | ((esdmode3 & 0xFFFF) << 0) in set_ddr_sdram_mode_2()
1045 ddr->ddr_sdram_mode_8 = (0 in set_ddr_sdram_mode_2()
1046 | ((esdmode2 & 0xFFFF) << 16) in set_ddr_sdram_mode_2()
1047 | ((esdmode3 & 0xFFFF) << 0) in set_ddr_sdram_mode_2()
1052 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n", in set_ddr_sdram_mode_2()
1054 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n", in set_ddr_sdram_mode_2()
1056 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n", in set_ddr_sdram_mode_2()
1068 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ in set_ddr_sdram_mode_2()
1069 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ in set_ddr_sdram_mode_2()
1071 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ in set_ddr_sdram_mode_2()
1072 unsigned int srt = 0; /* self-refresh temerature, normal range */ in set_ddr_sdram_mode_2()
1073 unsigned int asr = 0; /* auto self-refresh disable */ in set_ddr_sdram_mode_2()
1075 unsigned int pasr = 0; /* partial array self refresh disable */ in set_ddr_sdram_mode_2()
1080 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr; in set_ddr_sdram_mode_2()
1085 esdmode2 = (0 in set_ddr_sdram_mode_2()
1086 | ((rtt_wr & 0x3) << 9) in set_ddr_sdram_mode_2()
1087 | ((srt & 0x1) << 7) in set_ddr_sdram_mode_2()
1088 | ((asr & 0x1) << 6) in set_ddr_sdram_mode_2()
1089 | ((cwl & 0x7) << 3) in set_ddr_sdram_mode_2()
1090 | ((pasr & 0x7) << 0)); in set_ddr_sdram_mode_2()
1091 ddr->ddr_sdram_mode_2 = (0 in set_ddr_sdram_mode_2()
1092 | ((esdmode2 & 0xFFFF) << 16) in set_ddr_sdram_mode_2()
1093 | ((esdmode3 & 0xFFFF) << 0) in set_ddr_sdram_mode_2()
1095 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); in set_ddr_sdram_mode_2()
1104 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */ in set_ddr_sdram_mode_2()
1105 esdmode2 |= (rtt_wr & 0x3) << 9; in set_ddr_sdram_mode_2()
1108 ddr->ddr_sdram_mode_4 = (0 in set_ddr_sdram_mode_2()
1109 | ((esdmode2 & 0xFFFF) << 16) in set_ddr_sdram_mode_2()
1110 | ((esdmode3 & 0xFFFF) << 0) in set_ddr_sdram_mode_2()
1114 ddr->ddr_sdram_mode_6 = (0 in set_ddr_sdram_mode_2()
1115 | ((esdmode2 & 0xFFFF) << 16) in set_ddr_sdram_mode_2()
1116 | ((esdmode3 & 0xFFFF) << 0) in set_ddr_sdram_mode_2()
1120 ddr->ddr_sdram_mode_8 = (0 in set_ddr_sdram_mode_2()
1121 | ((esdmode2 & 0xFFFF) << 16) in set_ddr_sdram_mode_2()
1122 | ((esdmode3 & 0xFFFF) << 0) in set_ddr_sdram_mode_2()
1127 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n", in set_ddr_sdram_mode_2()
1129 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n", in set_ddr_sdram_mode_2()
1131 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n", in set_ddr_sdram_mode_2()
1144 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ in set_ddr_sdram_mode_2()
1145 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ in set_ddr_sdram_mode_2()
1147 ddr->ddr_sdram_mode_2 = (0 in set_ddr_sdram_mode_2()
1148 | ((esdmode2 & 0xFFFF) << 16) in set_ddr_sdram_mode_2()
1149 | ((esdmode3 & 0xFFFF) << 0) in set_ddr_sdram_mode_2()
1151 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); in set_ddr_sdram_mode_2()
1163 unsigned short esdmode4 = 0; /* Extended SDRAM mode 4 */ in set_ddr_sdram_mode_9()
1165 int rtt_park = 0; in set_ddr_sdram_mode_9()
1167 const unsigned int mclk_ps = get_memory_clk_period_ps(0); in set_ddr_sdram_mode_9()
1170 if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) && in set_ddr_sdram_mode_9()
1176 if (ddr->cs[0].config & SDRAM_CS_CONFIG_EN) { in set_ddr_sdram_mode_9()
1177 esdmode5 = 0x00000500; /* Data mask enable, RTT_PARK CS0 */ in set_ddr_sdram_mode_9()
1178 rtt_park = four_cs ? 0 : 1; in set_ddr_sdram_mode_9()
1180 esdmode5 = 0x00000400; /* Data mask enabled */ in set_ddr_sdram_mode_9()
1202 ddr->ddr_sdram_mode_9 = (0 in set_ddr_sdram_mode_9()
1203 | ((esdmode4 & 0xffff) << 16) in set_ddr_sdram_mode_9()
1204 | ((esdmode5 & 0xffff) << 0) in set_ddr_sdram_mode_9()
1207 /* Normally only the first enabled CS use 0x500, others use 0x400 in set_ddr_sdram_mode_9()
1209 * need 0x500 to park. in set_ddr_sdram_mode_9()
1212 debug("FSLDDR: ddr_sdram_mode_9 = 0x%08x\n", ddr->ddr_sdram_mode_9); in set_ddr_sdram_mode_9()
1217 esdmode5 |= 0x00000500; /* RTT_PARK */ in set_ddr_sdram_mode_9()
1218 rtt_park = four_cs ? 0 : 1; in set_ddr_sdram_mode_9()
1220 esdmode5 = 0x00000400; in set_ddr_sdram_mode_9()
1240 ddr->ddr_sdram_mode_11 = (0 in set_ddr_sdram_mode_9()
1241 | ((esdmode4 & 0xFFFF) << 16) in set_ddr_sdram_mode_9()
1242 | ((esdmode5 & 0xFFFF) << 0) in set_ddr_sdram_mode_9()
1246 ddr->ddr_sdram_mode_13 = (0 in set_ddr_sdram_mode_9()
1247 | ((esdmode4 & 0xFFFF) << 16) in set_ddr_sdram_mode_9()
1248 | ((esdmode5 & 0xFFFF) << 0) in set_ddr_sdram_mode_9()
1252 ddr->ddr_sdram_mode_15 = (0 in set_ddr_sdram_mode_9()
1253 | ((esdmode4 & 0xFFFF) << 16) in set_ddr_sdram_mode_9()
1254 | ((esdmode5 & 0xFFFF) << 0) in set_ddr_sdram_mode_9()
1259 debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n", in set_ddr_sdram_mode_9()
1261 debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n", in set_ddr_sdram_mode_9()
1263 debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n", in set_ddr_sdram_mode_9()
1276 unsigned short esdmode6 = 0; /* Extended SDRAM mode 6 */ in set_ddr_sdram_mode_10()
1277 unsigned short esdmode7 = 0; /* Extended SDRAM mode 7 */ in set_ddr_sdram_mode_10()
1280 esdmode6 = ((tccdl_min - 4) & 0x7) << 10; in set_ddr_sdram_mode_10()
1285 ddr->ddr_sdram_mode_10 = (0 in set_ddr_sdram_mode_10()
1286 | ((esdmode6 & 0xffff) << 16) in set_ddr_sdram_mode_10()
1287 | ((esdmode7 & 0xffff) << 0) in set_ddr_sdram_mode_10()
1289 debug("FSLDDR: ddr_sdram_mode_10 = 0x%08x\n", ddr->ddr_sdram_mode_10); in set_ddr_sdram_mode_10()
1294 ddr->ddr_sdram_mode_12 = (0 in set_ddr_sdram_mode_10()
1295 | ((esdmode6 & 0xFFFF) << 16) in set_ddr_sdram_mode_10()
1296 | ((esdmode7 & 0xFFFF) << 0) in set_ddr_sdram_mode_10()
1300 ddr->ddr_sdram_mode_14 = (0 in set_ddr_sdram_mode_10()
1301 | ((esdmode6 & 0xFFFF) << 16) in set_ddr_sdram_mode_10()
1302 | ((esdmode7 & 0xFFFF) << 0) in set_ddr_sdram_mode_10()
1306 ddr->ddr_sdram_mode_16 = (0 in set_ddr_sdram_mode_10()
1307 | ((esdmode6 & 0xFFFF) << 16) in set_ddr_sdram_mode_10()
1308 | ((esdmode7 & 0xFFFF) << 0) in set_ddr_sdram_mode_10()
1313 debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n", in set_ddr_sdram_mode_10()
1315 debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n", in set_ddr_sdram_mode_10()
1317 debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n", in set_ddr_sdram_mode_10()
1337 /* refint field used 0x3FFF in earlier controllers */ in set_ddr_sdram_interval()
1338 ddr->ddr_sdram_interval = (0 in set_ddr_sdram_interval()
1339 | ((refint & 0xFFFF) << 16) in set_ddr_sdram_interval()
1340 | ((bstopre & 0x3FFF) << 0) in set_ddr_sdram_interval()
1342 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval); in set_ddr_sdram_interval()
1360 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */ in set_ddr_sdram_mode()
1361 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */ in set_ddr_sdram_mode()
1363 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */ in set_ddr_sdram_mode()
1364 unsigned int al = 0; /* Posted CAS# additive latency (AL) */ in set_ddr_sdram_mode()
1365 unsigned int dic = 0; /* Output driver impedance, 40ohm */ in set_ddr_sdram_mode()
1367 0=Disable (Test/Debug) */ in set_ddr_sdram_mode()
1370 unsigned int wr = 0; /* Write Recovery */ in set_ddr_sdram_mode()
1372 unsigned int mode; /* Normal=0 or Test=1 */ in set_ddr_sdram_mode()
1374 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */ in set_ddr_sdram_mode()
1381 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6}; in set_ddr_sdram_mode()
1384 0, 1, 2, 3, 4, 5, 6, 7, 8, 8, in set_ddr_sdram_mode()
1390 rtt = popts->cs_local_opts[0].odt_rtt_norm; in set_ddr_sdram_mode()
1405 * controller. so we set the wrlvl_en = 0 here. in set_ddr_sdram_mode()
1407 esdmode = (0 in set_ddr_sdram_mode()
1408 | ((qoff & 0x1) << 12) in set_ddr_sdram_mode()
1409 | ((tdqs_en & 0x1) << 11) in set_ddr_sdram_mode()
1410 | ((rtt & 0x7) << 8) in set_ddr_sdram_mode()
1411 | ((wrlvl_en & 0x1) << 7) in set_ddr_sdram_mode()
1412 | ((al & 0x3) << 3) in set_ddr_sdram_mode()
1413 | ((dic & 0x3) << 1) /* DIC field is split */ in set_ddr_sdram_mode()
1414 | ((dll_en & 0x1) << 0) in set_ddr_sdram_mode()
1419 * 0=slow exit DLL off (tXPDLL) in set_ddr_sdram_mode()
1431 dll_rst = 0; /* dll no reset */ in set_ddr_sdram_mode()
1432 mode = 0; /* normal mode */ in set_ddr_sdram_mode()
1440 bt = 0; /* Nibble sequential */ in set_ddr_sdram_mode()
1444 bl = 0; in set_ddr_sdram_mode()
1460 sdmode = (0 in set_ddr_sdram_mode()
1461 | ((wr & 0x7) << 9) in set_ddr_sdram_mode()
1462 | ((dll_rst & 0x1) << 8) in set_ddr_sdram_mode()
1463 | ((mode & 0x1) << 7) in set_ddr_sdram_mode()
1464 | (((caslat >> 1) & 0x7) << 4) in set_ddr_sdram_mode()
1465 | ((bt & 0x1) << 3) in set_ddr_sdram_mode()
1467 | ((bl & 0x3) << 0) in set_ddr_sdram_mode()
1470 ddr->ddr_sdram_mode = (0 in set_ddr_sdram_mode()
1471 | ((esdmode & 0xFFFF) << 16) in set_ddr_sdram_mode()
1472 | ((sdmode & 0xFFFF) << 0) in set_ddr_sdram_mode()
1475 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); in set_ddr_sdram_mode()
1484 esdmode &= 0xF8FF; /* clear bit 10,9,8 for rtt */ in set_ddr_sdram_mode()
1485 esdmode |= (rtt & 0x7) << 8; in set_ddr_sdram_mode()
1488 ddr->ddr_sdram_mode_3 = (0 in set_ddr_sdram_mode()
1489 | ((esdmode & 0xFFFF) << 16) in set_ddr_sdram_mode()
1490 | ((sdmode & 0xFFFF) << 0) in set_ddr_sdram_mode()
1494 ddr->ddr_sdram_mode_5 = (0 in set_ddr_sdram_mode()
1495 | ((esdmode & 0xFFFF) << 16) in set_ddr_sdram_mode()
1496 | ((sdmode & 0xFFFF) << 0) in set_ddr_sdram_mode()
1500 ddr->ddr_sdram_mode_7 = (0 in set_ddr_sdram_mode()
1501 | ((esdmode & 0xFFFF) << 16) in set_ddr_sdram_mode()
1502 | ((sdmode & 0xFFFF) << 0) in set_ddr_sdram_mode()
1507 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n", in set_ddr_sdram_mode()
1509 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", in set_ddr_sdram_mode()
1511 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", in set_ddr_sdram_mode()
1531 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */ in set_ddr_sdram_mode()
1532 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */ in set_ddr_sdram_mode()
1534 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */ in set_ddr_sdram_mode()
1535 unsigned int al = 0; /* Posted CAS# additive latency (AL) */ in set_ddr_sdram_mode()
1536 unsigned int dic = 0; /* Output driver impedance, 40ohm */ in set_ddr_sdram_mode()
1537 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal), in set_ddr_sdram_mode()
1541 unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */ in set_ddr_sdram_mode()
1542 unsigned int wr = 0; /* Write Recovery */ in set_ddr_sdram_mode()
1544 unsigned int mode; /* Normal=0 or Test=1 */ in set_ddr_sdram_mode()
1546 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */ in set_ddr_sdram_mode()
1556 static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0}; in set_ddr_sdram_mode()
1561 rtt = popts->cs_local_opts[0].odt_rtt_norm; in set_ddr_sdram_mode()
1576 * controller. so we set the wrlvl_en = 0 here. in set_ddr_sdram_mode()
1578 esdmode = (0 in set_ddr_sdram_mode()
1579 | ((qoff & 0x1) << 12) in set_ddr_sdram_mode()
1580 | ((tdqs_en & 0x1) << 11) in set_ddr_sdram_mode()
1581 | ((rtt & 0x4) << 7) /* rtt field is split */ in set_ddr_sdram_mode()
1582 | ((wrlvl_en & 0x1) << 7) in set_ddr_sdram_mode()
1583 | ((rtt & 0x2) << 5) /* rtt field is split */ in set_ddr_sdram_mode()
1584 | ((dic & 0x2) << 4) /* DIC field is split */ in set_ddr_sdram_mode()
1585 | ((al & 0x3) << 3) in set_ddr_sdram_mode()
1586 | ((rtt & 0x1) << 2) /* rtt field is split */ in set_ddr_sdram_mode()
1587 | ((dic & 0x1) << 1) /* DIC field is split */ in set_ddr_sdram_mode()
1588 | ((dll_en & 0x1) << 0) in set_ddr_sdram_mode()
1593 * 0=slow exit DLL off (tXPDLL) in set_ddr_sdram_mode()
1606 dll_rst = 0; /* dll no reset */ in set_ddr_sdram_mode()
1607 mode = 0; /* normal mode */ in set_ddr_sdram_mode()
1612 0x2, /* 5 clocks */ in set_ddr_sdram_mode()
1613 0x4, /* 6 clocks */ in set_ddr_sdram_mode()
1614 0x6, /* 7 clocks */ in set_ddr_sdram_mode()
1615 0x8, /* 8 clocks */ in set_ddr_sdram_mode()
1616 0xa, /* 9 clocks */ in set_ddr_sdram_mode()
1617 0xc, /* 10 clocks */ in set_ddr_sdram_mode()
1618 0xe, /* 11 clocks */ in set_ddr_sdram_mode()
1619 0x1, /* 12 clocks */ in set_ddr_sdram_mode()
1620 0x3, /* 13 clocks */ in set_ddr_sdram_mode()
1621 0x5, /* 14 clocks */ in set_ddr_sdram_mode()
1622 0x7, /* 15 clocks */ in set_ddr_sdram_mode()
1623 0x9, /* 16 clocks */ in set_ddr_sdram_mode()
1630 bt = 0; /* Nibble sequential */ in set_ddr_sdram_mode()
1634 bl = 0; in set_ddr_sdram_mode()
1650 sdmode = (0 in set_ddr_sdram_mode()
1651 | ((dll_on & 0x1) << 12) in set_ddr_sdram_mode()
1652 | ((wr & 0x7) << 9) in set_ddr_sdram_mode()
1653 | ((dll_rst & 0x1) << 8) in set_ddr_sdram_mode()
1654 | ((mode & 0x1) << 7) in set_ddr_sdram_mode()
1655 | (((caslat >> 1) & 0x7) << 4) in set_ddr_sdram_mode()
1656 | ((bt & 0x1) << 3) in set_ddr_sdram_mode()
1658 | ((bl & 0x3) << 0) in set_ddr_sdram_mode()
1661 ddr->ddr_sdram_mode = (0 in set_ddr_sdram_mode()
1662 | ((esdmode & 0xFFFF) << 16) in set_ddr_sdram_mode()
1663 | ((sdmode & 0xFFFF) << 0) in set_ddr_sdram_mode()
1666 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); in set_ddr_sdram_mode()
1675 esdmode &= 0xFDBB; /* clear bit 9,6,2 */ in set_ddr_sdram_mode()
1676 esdmode |= (0 in set_ddr_sdram_mode()
1677 | ((rtt & 0x4) << 7) /* rtt field is split */ in set_ddr_sdram_mode()
1678 | ((rtt & 0x2) << 5) /* rtt field is split */ in set_ddr_sdram_mode()
1679 | ((rtt & 0x1) << 2) /* rtt field is split */ in set_ddr_sdram_mode()
1683 ddr->ddr_sdram_mode_3 = (0 in set_ddr_sdram_mode()
1684 | ((esdmode & 0xFFFF) << 16) in set_ddr_sdram_mode()
1685 | ((sdmode & 0xFFFF) << 0) in set_ddr_sdram_mode()
1689 ddr->ddr_sdram_mode_5 = (0 in set_ddr_sdram_mode()
1690 | ((esdmode & 0xFFFF) << 16) in set_ddr_sdram_mode()
1691 | ((sdmode & 0xFFFF) << 0) in set_ddr_sdram_mode()
1695 ddr->ddr_sdram_mode_7 = (0 in set_ddr_sdram_mode()
1696 | ((esdmode & 0xFFFF) << 16) in set_ddr_sdram_mode()
1697 | ((sdmode & 0xFFFF) << 0) in set_ddr_sdram_mode()
1702 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n", in set_ddr_sdram_mode()
1704 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", in set_ddr_sdram_mode()
1706 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", in set_ddr_sdram_mode()
1733 unsigned int mrs = 0; /* Mode Register Set */ in set_ddr_sdram_mode()
1734 unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */ in set_ddr_sdram_mode()
1735 unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */ in set_ddr_sdram_mode()
1736 unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */ in set_ddr_sdram_mode()
1737 unsigned int ocd = 0; /* 0x0=OCD not supported, in set_ddr_sdram_mode()
1738 0x7=OCD default state */ in set_ddr_sdram_mode()
1741 unsigned int ods = 0; /* Output Drive Strength: in set_ddr_sdram_mode()
1742 0 = Full strength (18ohm) in set_ddr_sdram_mode()
1744 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal), in set_ddr_sdram_mode()
1752 unsigned int mode; /* Normal=0 or Test=1 */ in set_ddr_sdram_mode()
1753 unsigned int caslat = 0;/* CAS# latency */ in set_ddr_sdram_mode()
1754 /* BT: Burst Type (0=Sequential, 1=Interleaved) */ in set_ddr_sdram_mode()
1763 esdmode = (0 in set_ddr_sdram_mode()
1764 | ((mrs & 0x3) << 14) in set_ddr_sdram_mode()
1765 | ((outputs & 0x1) << 12) in set_ddr_sdram_mode()
1766 | ((rdqs_en & 0x1) << 11) in set_ddr_sdram_mode()
1767 | ((dqs_en & 0x1) << 10) in set_ddr_sdram_mode()
1768 | ((ocd & 0x7) << 7) in set_ddr_sdram_mode()
1769 | ((rtt & 0x2) << 5) /* rtt field is split */ in set_ddr_sdram_mode()
1770 | ((al & 0x7) << 3) in set_ddr_sdram_mode()
1771 | ((rtt & 0x1) << 2) /* rtt field is split */ in set_ddr_sdram_mode()
1772 | ((ods & 0x1) << 1) in set_ddr_sdram_mode()
1773 | ((dll_en & 0x1) << 0) in set_ddr_sdram_mode()
1776 mr = 0; /* FIXME: CHECKME */ in set_ddr_sdram_mode()
1779 * 0 = Fast Exit (Normal) in set_ddr_sdram_mode()
1782 pd = 0; in set_ddr_sdram_mode()
1785 wr = 0; /* Historical */ in set_ddr_sdram_mode()
1789 dll_res = 0; in set_ddr_sdram_mode()
1790 mode = 0; in set_ddr_sdram_mode()
1795 0x5, /* 1.5 clocks */ in set_ddr_sdram_mode()
1796 0x2, /* 2.0 clocks */ in set_ddr_sdram_mode()
1797 0x6, /* 2.5 clocks */ in set_ddr_sdram_mode()
1798 0x3 /* 3.0 clocks */ in set_ddr_sdram_mode()
1807 bt = 0; in set_ddr_sdram_mode()
1824 sdmode = (0 in set_ddr_sdram_mode()
1825 | ((mr & 0x3) << 14) in set_ddr_sdram_mode()
1826 | ((pd & 0x1) << 12) in set_ddr_sdram_mode()
1827 | ((wr & 0x7) << 9) in set_ddr_sdram_mode()
1828 | ((dll_res & 0x1) << 8) in set_ddr_sdram_mode()
1829 | ((mode & 0x1) << 7) in set_ddr_sdram_mode()
1830 | ((caslat & 0x7) << 4) in set_ddr_sdram_mode()
1831 | ((bt & 0x1) << 3) in set_ddr_sdram_mode()
1832 | ((bl & 0x7) << 0) in set_ddr_sdram_mode()
1835 ddr->ddr_sdram_mode = (0 in set_ddr_sdram_mode()
1836 | ((esdmode & 0xFFFF) << 16) in set_ddr_sdram_mode()
1837 | ((sdmode & 0xFFFF) << 0) in set_ddr_sdram_mode()
1839 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); in set_ddr_sdram_mode()
1851 init_value = 0xDEADBEEF; in set_ddr_data_init()
1859 * Hope it's OK to set it (to 0) anyway.
1865 unsigned int ss_en = 0; /* Source synchronous enable */ in set_ddr_sdram_clk_cntl()
1871 if (fsl_ddr_get_version(0) >= 0x40701) { in set_ddr_sdram_clk_cntl()
1873 clk_adjust = (popts->clk_adjust & 0x1F) << 22; in set_ddr_sdram_clk_cntl()
1876 clk_adjust = (popts->clk_adjust & 0xF) << 23; in set_ddr_sdram_clk_cntl()
1879 ddr->ddr_sdram_clk_cntl = (0 in set_ddr_sdram_clk_cntl()
1880 | ((ss_en & 0x1) << 31) in set_ddr_sdram_clk_cntl()
1883 debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl); in set_ddr_sdram_clk_cntl()
1889 unsigned int init_addr = 0; /* Initialization address */ in set_ddr_init_addr()
1897 unsigned int uia = 0; /* Use initialization address */ in set_ddr_init_ext_addr()
1898 unsigned int init_ext_addr = 0; /* Initialization address */ in set_ddr_init_ext_addr()
1900 ddr->ddr_init_ext_addr = (0 in set_ddr_init_ext_addr()
1901 | ((uia & 0x1) << 31) in set_ddr_init_ext_addr()
1902 | (init_ext_addr & 0xF) in set_ddr_init_ext_addr()
1910 unsigned int rwt = 0; /* Read-to-write turnaround for same CS */ in set_timing_cfg_4()
1911 unsigned int wrt = 0; /* Write-to-read turnaround for same CS */ in set_timing_cfg_4()
1912 unsigned int rrt = 0; /* Read-to-read turnaround for same CS */ in set_timing_cfg_4()
1913 unsigned int wwt = 0; /* Write-to-write turnaround for same CS */ in set_timing_cfg_4()
1914 unsigned int trwt_mclk = 0; /* ext_rwt */ in set_timing_cfg_4()
1915 unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */ in set_timing_cfg_4()
1920 rrt = 0; /* BL/2 clocks */ in set_timing_cfg_4()
1921 wwt = 0; /* BL/2 clocks */ in set_timing_cfg_4()
1937 ddr->timing_cfg_4 = (0 in set_timing_cfg_4()
1938 | ((rwt & 0xf) << 28) in set_timing_cfg_4()
1939 | ((wrt & 0xf) << 24) in set_timing_cfg_4()
1940 | ((rrt & 0xf) << 20) in set_timing_cfg_4()
1941 | ((wwt & 0xf) << 16) in set_timing_cfg_4()
1942 | ((trwt_mclk & 0xc) << 12) in set_timing_cfg_4()
1943 | (dll_lock & 0x3) in set_timing_cfg_4()
1945 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4); in set_timing_cfg_4()
1951 unsigned int rodt_on = 0; /* Read to ODT on */ in set_timing_cfg_5()
1952 unsigned int rodt_off = 0; /* Read to ODT off */ in set_timing_cfg_5()
1953 unsigned int wodt_on = 0; /* Write to ODT on */ in set_timing_cfg_5()
1954 unsigned int wodt_off = 0; /* Write to ODT off */ in set_timing_cfg_5()
1957 unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) + in set_timing_cfg_5()
1958 ((ddr->timing_cfg_2 & 0x00040000) >> 14); in set_timing_cfg_5()
1967 ddr->timing_cfg_5 = (0 in set_timing_cfg_5()
1968 | ((rodt_on & 0x1f) << 24) in set_timing_cfg_5()
1969 | ((rodt_off & 0x7) << 20) in set_timing_cfg_5()
1970 | ((wodt_on & 0x1f) << 12) in set_timing_cfg_5()
1971 | ((wodt_off & 0x7) << 8) in set_timing_cfg_5()
1973 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5); in set_timing_cfg_5()
1979 unsigned int hs_caslat = 0; in set_timing_cfg_6()
1980 unsigned int hs_wrlat = 0; in set_timing_cfg_6()
1981 unsigned int hs_wrrec = 0; in set_timing_cfg_6()
1982 unsigned int hs_clkadj = 0; in set_timing_cfg_6()
1983 unsigned int hs_wrlvl_start = 0; in set_timing_cfg_6()
1985 ddr->timing_cfg_6 = (0 in set_timing_cfg_6()
1986 | ((hs_caslat & 0x1f) << 24) in set_timing_cfg_6()
1987 | ((hs_wrlat & 0x1f) << 19) in set_timing_cfg_6()
1988 | ((hs_wrrec & 0x1f) << 12) in set_timing_cfg_6()
1989 | ((hs_clkadj & 0x1f) << 6) in set_timing_cfg_6()
1990 | ((hs_wrlvl_start & 0x1f) << 0) in set_timing_cfg_6()
1992 debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6); in set_timing_cfg_6()
2001 unsigned int cke_rst, cksre, cksrx, par_lat = 0, cs_to_cmd; in set_timing_cfg_7()
2011 par_lat = (ddr->ddr_sdram_rcw_2 & 0xf) + 1; in set_timing_cfg_7()
2015 cs_to_cmd = 0; in set_timing_cfg_7()
2018 cke_rst = 0; in set_timing_cfg_7()
2036 ddr->timing_cfg_7 = (0 in set_timing_cfg_7()
2037 | ((cke_rst & 0x3) << 28) in set_timing_cfg_7()
2038 | ((cksre & 0xf) << 24) in set_timing_cfg_7()
2039 | ((cksrx & 0xf) << 20) in set_timing_cfg_7()
2040 | ((par_lat & 0xf) << 16) in set_timing_cfg_7()
2041 | ((cs_to_cmd & 0xf) << 4) in set_timing_cfg_7()
2043 debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7); in set_timing_cfg_7()
2055 int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) + in set_timing_cfg_8()
2056 ((ddr->timing_cfg_2 & 0x00040000) >> 14); in set_timing_cfg_8()
2062 rwt_bg = 0; in set_timing_cfg_8()
2068 wrt_bg = 0; in set_timing_cfg_8()
2083 pre_all_rec = 0; in set_timing_cfg_8()
2085 ddr->timing_cfg_8 = (0 in set_timing_cfg_8()
2086 | ((rwt_bg & 0xf) << 28) in set_timing_cfg_8()
2087 | ((wrt_bg & 0xf) << 24) in set_timing_cfg_8()
2088 | ((rrt_bg & 0xf) << 20) in set_timing_cfg_8()
2089 | ((wwt_bg & 0xf) << 16) in set_timing_cfg_8()
2090 | ((acttoact_bg & 0xf) << 12) in set_timing_cfg_8()
2091 | ((wrtord_bg & 0xf) << 8) in set_timing_cfg_8()
2092 | ((pre_all_rec & 0x1f) << 0) in set_timing_cfg_8()
2095 debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8); in set_timing_cfg_8()
2103 unsigned int refrec_cid_mclk = 0; in set_timing_cfg_9()
2104 unsigned int acttoact_cid_mclk = 0; in set_timing_cfg_9()
2112 ddr->timing_cfg_9 = (refrec_cid_mclk & 0x3ff) << 16 | in set_timing_cfg_9()
2113 (acttoact_cid_mclk & 0xf) << 8; in set_timing_cfg_9()
2115 debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9); in set_timing_cfg_9()
2122 unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1; in set_ddr_dq_mapping()
2125 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { in set_ddr_dq_mapping()
2134 ddr->dq_map_0 = ((dimm_params[i].dq_mapping[0] & 0x3F) << 26) | in set_ddr_dq_mapping()
2135 ((dimm_params[i].dq_mapping[1] & 0x3F) << 20) | in set_ddr_dq_mapping()
2136 ((dimm_params[i].dq_mapping[2] & 0x3F) << 14) | in set_ddr_dq_mapping()
2137 ((dimm_params[i].dq_mapping[3] & 0x3F) << 8) | in set_ddr_dq_mapping()
2138 ((dimm_params[i].dq_mapping[4] & 0x3F) << 2); in set_ddr_dq_mapping()
2140 ddr->dq_map_1 = ((dimm_params[i].dq_mapping[5] & 0x3F) << 26) | in set_ddr_dq_mapping()
2141 ((dimm_params[i].dq_mapping[6] & 0x3F) << 20) | in set_ddr_dq_mapping()
2142 ((dimm_params[i].dq_mapping[7] & 0x3F) << 14) | in set_ddr_dq_mapping()
2143 ((dimm_params[i].dq_mapping[10] & 0x3F) << 8) | in set_ddr_dq_mapping()
2144 ((dimm_params[i].dq_mapping[11] & 0x3F) << 2); in set_ddr_dq_mapping()
2146 ddr->dq_map_2 = ((dimm_params[i].dq_mapping[12] & 0x3F) << 26) | in set_ddr_dq_mapping()
2147 ((dimm_params[i].dq_mapping[13] & 0x3F) << 20) | in set_ddr_dq_mapping()
2148 ((dimm_params[i].dq_mapping[14] & 0x3F) << 14) | in set_ddr_dq_mapping()
2149 ((dimm_params[i].dq_mapping[15] & 0x3F) << 8) | in set_ddr_dq_mapping()
2150 ((dimm_params[i].dq_mapping[16] & 0x3F) << 2); in set_ddr_dq_mapping()
2152 /* dq_map for ECC[4:7] is set to 0 if accumulated ECC is enabled */ in set_ddr_dq_mapping()
2153 ddr->dq_map_3 = ((dimm_params[i].dq_mapping[17] & 0x3F) << 26) | in set_ddr_dq_mapping()
2154 ((dimm_params[i].dq_mapping[8] & 0x3F) << 20) | in set_ddr_dq_mapping()
2155 (acc_ecc_en ? 0 : in set_ddr_dq_mapping()
2156 (dimm_params[i].dq_mapping[9] & 0x3F) << 14) | in set_ddr_dq_mapping()
2159 debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0); in set_ddr_dq_mapping()
2160 debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1); in set_ddr_dq_mapping()
2161 debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2); in set_ddr_dq_mapping()
2162 debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3); in set_ddr_dq_mapping()
2169 rd_pre = popts->quad_rank_present ? 1 : 0; in set_ddr_sdram_cfg_3()
2171 ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16; in set_ddr_sdram_cfg_3()
2173 ddr->ddr_sdram_cfg_3 |= popts->registered_dimm_en ? 1 : 0; in set_ddr_sdram_cfg_3()
2176 if ((popts->package_3ds + 1) & 0x1) { in set_ddr_sdram_cfg_3()
2185 debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3); in set_ddr_sdram_cfg_3()
2192 unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */ in set_ddr_zq_cntl()
2194 unsigned int zqoper = 0; in set_ddr_zq_cntl()
2196 unsigned int zqcs = 0; in set_ddr_zq_cntl()
2214 ddr->ddr_zq_cntl = (0 in set_ddr_zq_cntl()
2215 | ((zq_en & 0x1) << 31) in set_ddr_zq_cntl()
2216 | ((zqinit & 0xF) << 24) in set_ddr_zq_cntl()
2217 | ((zqoper & 0xF) << 16) in set_ddr_zq_cntl()
2218 | ((zqcs & 0xF) << 8) in set_ddr_zq_cntl()
2220 | ((zqcs_init & 0xF) << 0) in set_ddr_zq_cntl()
2223 debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl); in set_ddr_zq_cntl()
2234 unsigned int wrlvl_mrd = 0; in set_ddr_wrlvl_cntl()
2236 unsigned int wrlvl_odten = 0; in set_ddr_wrlvl_cntl()
2238 unsigned int wrlvl_dqsen = 0; in set_ddr_wrlvl_cntl()
2240 unsigned int wrlvl_smpl = 0; in set_ddr_wrlvl_cntl()
2242 unsigned int wrlvl_wlr = 0; in set_ddr_wrlvl_cntl()
2244 unsigned int wrlvl_start = 0; in set_ddr_wrlvl_cntl()
2249 wrlvl_mrd = 0x6; in set_ddr_wrlvl_cntl()
2251 wrlvl_odten = 0x7; in set_ddr_wrlvl_cntl()
2253 wrlvl_dqsen = 0x5; in set_ddr_wrlvl_cntl()
2259 wrlvl_smpl = 0xf; in set_ddr_wrlvl_cntl()
2265 wrlvl_wlr = 0x6; in set_ddr_wrlvl_cntl()
2272 wrlvl_start = 0x8; in set_ddr_wrlvl_cntl()
2283 ddr->ddr_wrlvl_cntl = (0 in set_ddr_wrlvl_cntl()
2284 | ((wrlvl_en & 0x1) << 31) in set_ddr_wrlvl_cntl()
2285 | ((wrlvl_mrd & 0x7) << 24) in set_ddr_wrlvl_cntl()
2286 | ((wrlvl_odten & 0x7) << 20) in set_ddr_wrlvl_cntl()
2287 | ((wrlvl_dqsen & 0x7) << 16) in set_ddr_wrlvl_cntl()
2288 | ((wrlvl_smpl & 0xf) << 12) in set_ddr_wrlvl_cntl()
2289 | ((wrlvl_wlr & 0x7) << 8) in set_ddr_wrlvl_cntl()
2290 | ((wrlvl_start & 0x1F) << 0) in set_ddr_wrlvl_cntl()
2292 debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl); in set_ddr_wrlvl_cntl()
2294 debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2); in set_ddr_wrlvl_cntl()
2296 debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3); in set_ddr_wrlvl_cntl()
2304 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16; in set_ddr_sr_cntr()
2310 ddr->ddr_eor = 0x40000000; /* address hash enable */ in set_ddr_eor()
2318 debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1); in set_ddr_cdr1()
2324 debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2); in set_ddr_cdr2()
2330 unsigned int res = 0; in check_fsl_memctl_config_regs()
2336 if (ddr->ddr_sdram_cfg & 0x10000000 in check_fsl_memctl_config_regs()
2337 && ddr->ddr_sdram_cfg & 0x00008000) { in check_fsl_memctl_config_regs()
2361 unsigned int ip_rev = 0; in compute_fsl_memctl_config_regs()
2362 unsigned int unq_mrs_en = 0; in compute_fsl_memctl_config_regs()
2373 case 0: in compute_fsl_memctl_config_regs()
2397 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t)); in compute_fsl_memctl_config_regs()
2419 : 0; in compute_fsl_memctl_config_regs()
2421 zq_en = (popts->zq_en) ? 1 : 0; in compute_fsl_memctl_config_regs()
2423 wrlvl_en = (popts->wrlvl_en) ? 1 : 0; in compute_fsl_memctl_config_regs()
2426 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { in compute_fsl_memctl_config_regs()
2435 if (dimm_params[dimm_number].n_ranks == 0) { in compute_fsl_memctl_config_regs()
2437 "because n_ranks on DIMM %u is 0\n", i, dimm_number); in compute_fsl_memctl_config_regs()
2447 cs_en = 0; in compute_fsl_memctl_config_regs()
2451 if (i > 0) in compute_fsl_memctl_config_regs()
2452 cs_en = 0; in compute_fsl_memctl_config_regs()
2473 if ((i >= 2) && (dimm_number == 0)) { in compute_fsl_memctl_config_regs()
2490 sa = 0; in compute_fsl_memctl_config_regs()
2491 ea = 0; in compute_fsl_memctl_config_regs()
2493 if (i == 0) in compute_fsl_memctl_config_regs()
2504 sa = 0; in compute_fsl_memctl_config_regs()
2505 ea = 0; in compute_fsl_memctl_config_regs()
2517 sa = 0; in compute_fsl_memctl_config_regs()
2518 ea = 0; in compute_fsl_memctl_config_regs()
2528 ddr->cs[i].bnds = (0 in compute_fsl_memctl_config_regs()
2529 | ((sa & 0xffff) << 16) /* starting address */ in compute_fsl_memctl_config_regs()
2530 | ((ea & 0xffff) << 0) /* ending address */ in compute_fsl_memctl_config_regs()
2533 /* setting bnds to 0xffffffff for inactive CS */ in compute_fsl_memctl_config_regs()
2534 ddr->cs[i].bnds = 0xffffffff; in compute_fsl_memctl_config_regs()
2537 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds); in compute_fsl_memctl_config_regs()
2547 return 0; in compute_fsl_memctl_config_regs()
2565 if (ip_rev > 0x40400) in compute_fsl_memctl_config_regs()
2568 if ((ip_rev > 0x40700) && (popts->cswl_override != 0)) in compute_fsl_memctl_config_regs()
2604 ddr->debug[2] = 0x00000400; in compute_fsl_memctl_config_regs()
2605 ddr->debug[4] = 0xff800800; in compute_fsl_memctl_config_regs()
2606 ddr->debug[5] = 0x08000800; in compute_fsl_memctl_config_regs()
2607 ddr->debug[6] = 0x08000800; in compute_fsl_memctl_config_regs()
2608 ddr->debug[7] = 0x08000800; in compute_fsl_memctl_config_regs()
2609 ddr->debug[8] = 0x08000800; in compute_fsl_memctl_config_regs()
2612 if ((ip_rev >= 0x40000) && (ip_rev < 0x40400)) in compute_fsl_memctl_config_regs()
2613 ddr->debug[2] |= 0x00000200; /* set bit 22 */ in compute_fsl_memctl_config_regs()
2618 #define IS_ACC_ECC_EN(v) ((v) & 0x4) in compute_fsl_memctl_config_regs()
2619 #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2) in compute_fsl_memctl_config_regs()
2624 ddr->debug[28] |= (0x9 << 20); in compute_fsl_memctl_config_regs()
2632 ddr->debug[28] &= 0xff0fff00; in compute_fsl_memctl_config_regs()
2634 ddr->debug[28] |= 0x0080006a; in compute_fsl_memctl_config_regs()
2636 ddr->debug[28] |= 0x0070006f; in compute_fsl_memctl_config_regs()
2638 ddr->debug[28] |= 0x00700076; in compute_fsl_memctl_config_regs()
2640 ddr->debug[28] |= 0x0060007b; in compute_fsl_memctl_config_regs()
2642 ddr->debug[28] = (ddr->debug[28] & 0xffffff00) | in compute_fsl_memctl_config_regs()
2681 cpo_o = (cpo >> 8) & 0xff; in erratum_a009942_check_cpo()
2699 cpo_target = ddr_in32(&ddr->debug[28]) & 0xff; in erratum_a009942_check_cpo()
2700 cpo_optimal = ((cpo_max + cpo_min) >> 1) + 0x27; in erratum_a009942_check_cpo()
2701 debug("cpo_optimal = 0x%x, cpo_target = 0x%x\n", cpo_optimal, in erratum_a009942_check_cpo()
2703 debug("cpo_max = 0x%x, cpo_min = 0x%x\n", cpo_max, cpo_min); in erratum_a009942_check_cpo()
2708 update_cpo = (cpo_min + 0x3b) < cpo_target ? true : false; in erratum_a009942_check_cpo()
2710 update_cpo = (cpo_min + 0x3f) < cpo_target ? true : false; in erratum_a009942_check_cpo()
2713 printf("WARN: pls set popts->cpo_sample = 0x%x ", cpo_optimal); in erratum_a009942_check_cpo()