Home
last modified time | relevance | path

Searched +full:0 +full:xff400000 (Results 1 – 21 of 21) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/fpga/
H A Daltera-hps2fpga-bridge.txt17 reg = <0xff400000 0x100000>;
20 bridge-enable = <0>;
25 reg = <0xff500000 0x10000>;
33 reg = <0xff600000 0x100000>;
H A Dfpga-region.txt210 bridge's region (0xff200000) and the hps bridge's region (0xc0000000) for use by
218 reg = <0xff706000 0x1000
219 0xffb90000 0x20>;
220 interrupts = <0 175 4>;
225 reg = <0xff400000 0x100000>;
241 reg = <0xff500000 0x10000>;
257 ranges = <0x20000 0xff200000 0x100000>,
258 <0x0 0xc0000000 0x20000000>;
262 reg = <0x10040 0x20>;
272 reg = <0x0 0x10000>;
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dbase_addr_ac5.h9 #define SOCFPGA_FPGA_SLAVES_ADDRESS 0xc0000000
10 #define SOCFPGA_STM_ADDRESS 0xfc000000
11 #define SOCFPGA_DAP_ADDRESS 0xff000000
12 #define SOCFPGA_EMAC0_ADDRESS 0xff700000
13 #define SOCFPGA_EMAC1_ADDRESS 0xff702000
14 #define SOCFPGA_SDMMC_ADDRESS 0xff704000
15 #define SOCFPGA_QSPI_ADDRESS 0xff705000
16 #define SOCFPGA_GPIO0_ADDRESS 0xff708000
17 #define SOCFPGA_GPIO1_ADDRESS 0xff709000
18 #define SOCFPGA_GPIO2_ADDRESS 0xff70a000
[all …]
/openbmc/u-boot/include/configs/
H A DTQM834x.h21 /* IMMR Base Address Register, use Freescale default: 0xff400000 */
22 #define CONFIG_SYS_IMMR 0xff400000
47 #define CONFIG_SYS_DDR_BASE 0x00000000
55 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
56 #define CONFIG_SYS_MEMTEST_END 0x00100000
62 #define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */
84 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
90 /* FLASH timing (0x0000_0c54) */
107 #define CONFIG_SYS_BR1_PRELIM 0x00000000
108 #define CONFIG_SYS_OR1_PRELIM 0x00000000
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dctxnv40.h45 ctx->ctxprog_reg = (reg - 0x00400000) >> 2; in cp_ctx()
52 length = 0; in cp_ctx()
68 for (i = 0; i < ctx->ctxprog_len; i++) { in cp_name()
69 if ((ctxprog[i] & 0xfff00000) != 0xff400000) in cp_name()
73 ctxprog[i] = (ctxprog[i] & 0x00ff00ff) | in cp_name()
81 int ip = 0; in _cp_bra()
85 if (ip == 0) in _cp_bra()
86 ip = 0xff000000 | (name << CP_BRA_IP_SHIFT); in _cp_bra()
90 (state ? 0 : CP_BRA_IF_CLEAR)); in _cp_bra()
92 #define cp_bra(c, f, s, n) _cp_bra((c), 0, CP_FLAG_##f, CP_FLAG_##f##_##s, n)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Damlogic,meson-g12a-usb-ctrl.yaml81 "^usb@[0-9a-f]+$":
202 reg = <0xffe09000 0xa0>;
218 reg = <0xff400000 0x40000>;
231 reg = <0xff500000 0x100000>;
235 snps,quirk-frame-length-adjustment = <0x20>;
/openbmc/linux/arch/mips/kernel/
H A Dbmips_vec.S35 * it to resume execution at 0x8000_0200 (!BEV IV vector) when it is
37 * it to a more convenient place: BMIPS_WARM_RESTART_VEC @ 0x8000_0380.
54 /* set up CPU1 CBR; move BASE to 0xa000_0000 */
55 li k0, 0xff400000
60 andi k1, 0x8000
63 li k1, 0xa0080000
64 sw k1, 0(k0)
78 * entire function gets copied to 0x8000_0000.
100 /* if we're not on core 0, this must be the SMP boot signal */
134 andi k0, 0xff00
[all …]
/openbmc/linux/drivers/mtd/maps/
H A Dichxrom.c30 #define BIOS_CNTL 0x4e
31 #define FWH_DEC_EN1 0xE3
32 #define FWH_DEC_EN2 0xF0
33 #define FWH_SEL1 0xE8
34 #define FWH_SEL2 0xEE
83 window->phys = 0; in ichxrom_cleanup()
84 window->size = 0; in ichxrom_cleanup()
113 window->phys = 0; in ichxrom_init_one()
115 if (byte == 0xff) { in ichxrom_init_one()
116 window->phys = 0xffc00000; in ichxrom_init_one()
[all …]
H A Desb2rom.c34 #define BIOS_CNTL 0xDC
35 #define BIOS_LOCK_ENABLE 0x02
36 #define BIOS_WRITE_ENABLE 0x01
39 #define FWH_DEC_EN1 0xD8
40 #define FWH_F8_EN 0x8000
41 #define FWH_F0_EN 0x4000
42 #define FWH_E8_EN 0x2000
43 #define FWH_E0_EN 0x1000
44 #define FWH_D8_EN 0x0800
45 #define FWH_D0_EN 0x0400
[all …]
/openbmc/linux/arch/powerpc/platforms/83xx/
H A Dsuspend-asm.S14 #define SS_MEMSAVE 0x00 /* First 8 bytes of RAM */
15 #define SS_HID 0x08 /* 3 HIDs */
16 #define SS_IABR 0x14 /* 2 IABRs */
17 #define SS_IBCR 0x1c
18 #define SS_DABR 0x20 /* 2 DABRs */
19 #define SS_DBCR 0x28
20 #define SS_SP 0x2c
21 #define SS_SR 0x30 /* 16 segment registers */
22 #define SS_R2 0x70
23 #define SS_MSR 0x74
[all …]
/openbmc/linux/arch/m68k/include/asm/
H A Dio_mm.h45 #define q40_isa_io_base 0xff400000
46 #define q40_isa_mem_base 0xff800000
53 #define MULTI_ISA 0
63 #define MULTI_ISA 0
72 #define enec_isa_read_base 0xfffa0000
73 #define enec_isa_write_base 0xfffb0000
75 #define ENEC_ISA_IO_B(ioaddr) (enec_isa_read_base+((((unsigned long)(ioaddr))&0x7F)<<9))
76 #define ENEC_ISA_IO_W(ioaddr) (enec_isa_read_base+((((unsigned long)(ioaddr))&0x7F)<<9))
77 #define ENEC_ISA_MEM_B(madr) (enec_isa_read_base+((((unsigned long)(madr))&0x7F)<<9))
78 #define ENEC_ISA_MEM_W(madr) (enec_isa_read_base+((((unsigned long)(madr))&0x7F)<<9))
[all …]
/openbmc/linux/drivers/staging/wlan-ng/
H A Dprism2fw.c44 #define S3ADDR_PLUG (0xff000000UL)
45 #define S3ADDR_CRC (0xff100000UL)
46 #define S3ADDR_INFO (0xff200000UL)
47 #define S3ADDR_START (0xff400000UL)
183 * 0 - success
184 * ~0 - failure
194 PRISM2_USB_FWFILE, &udev->dev) != 0) { in prism2_fwtry()
208 return 0; in prism2_fwtry()
221 * 0 - success
222 * ~0 - failure
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsocfpga.dtsi23 #size-cells = <0>;
26 cpu0: cpu@0 {
29 reg = <0>;
43 interrupts = <0 176 4>, <0 177 4>;
45 reg = <0xff111000 0x1000>,
46 <0xff113000 0x1000>;
53 reg = <0xfffed000 0x1000>,
54 <0xfffec100 0x100>;
73 reg = <0xffe01000 0x1000>;
74 interrupts = <0 104 4>,
[all …]
H A Drk3328.dtsi34 #size-cells = <0>;
36 cpu0: cpu@0 {
39 reg = <0x0 0x0>;
47 reg = <0x0 0x1>;
53 reg = <0x0 0x2>;
59 reg = <0x0 0x3>;
125 #clock-cells = <0>;
132 reg = <0x0 0xff000000 0x0 0x1000>;
144 reg = <0x0 0xff010000 0x0 0x1000>;
156 reg = <0x0 0xff020000 0x0 0x1000>;
[all …]
/openbmc/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga.dtsi23 #size-cells = <0>;
26 cpu0: cpu@0 {
29 reg = <0>;
43 interrupts = <0 176 4>, <0 177 4>;
45 reg = <0xff111000 0x1000>,
46 <0xff113000 0x1000>;
53 reg = <0xfffed000 0x1000>,
54 <0xfffec100 0x100>;
73 reg = <0xffe01000 0x1000>;
74 interrupts = <0 104 4>,
[all …]
/openbmc/linux/arch/arm/probes/
H A Ddecode-thumb.c20 DECODE_REJECT (0xfe4f0000, 0xe80f0000),
24 DECODE_REJECT (0xffc00000, 0xe8000000),
27 DECODE_REJECT (0xffc00000, 0xe9800000),
30 DECODE_REJECT (0xfe508000, 0xe8008000),
32 DECODE_REJECT (0xfe50c000, 0xe810c000),
34 DECODE_REJECT (0xfe402000, 0xe8002000),
40 DECODE_CUSTOM (0xfe400000, 0xe8000000, PROBES_T32_LDMSTM),
50 DECODE_OR (0xff600000, 0xe8600000),
53 DECODE_EMULATEX (0xff400000, 0xe9400000, PROBES_T32_LDRDSTRD,
54 REGS(NOPCWB, NOSPPC, NOSPPC, 0, 0)),
[all …]
/openbmc/u-boot/include/
H A Dmpc83xx.h23 #define EXC_OFF_SYS_RESET 0x0100
31 #define CONFIG_DEFAULT_IMMR 0xFF400000
34 #define IMMRBAR 0x0000
35 #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base addr. mask */
42 #define LBLAWBAR0 0x0020
43 #define LBLAWAR0 0x0024
44 #define LBLAWBAR1 0x0028
45 #define LBLAWAR1 0x002C
46 #define LBLAWBAR2 0x0030
47 #define LBLAWAR2 0x0034
[all …]
/openbmc/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-axg.dtsi24 tdmif_a: audio-controller-0 {
26 #sound-dai-cells = <0>;
37 #sound-dai-cells = <0>;
48 #sound-dai-cells = <0>;
67 #address-cells = <0x2>;
68 #size-cells = <0x0>;
70 cpu0: cpu@0 {
73 reg = <0x0 0x0>;
76 clocks = <&scpi_dvfs 0>;
82 reg = <0x0 0x1>;
[all …]
H A Dmeson-g12-common.dtsi107 reg = <0x0 0x05000000 0x0 0x300000>;
113 reg = <0x0 0x05300000 0x0 0x2000000>;
120 size = <0x0 0x10000000>;
121 alignment = <0x0 0x400000>;
138 reg = <0x0 0xfc000000 0x0 0x400000>,
139 <0x0 0xff648000 0x0 0x2000>,
140 <0x0 0xfc400000 0x0 0x200000>;
144 interrupt-map-mask = <0 0 0 0>;
145 interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
146 bus-range = <0x0 0xff>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3308.dtsi39 #size-cells = <0>;
41 cpu0: cpu@0 {
44 reg = <0x0 0x0>;
57 reg = <0x0 0x1>;
67 reg = <0x0 0x2>;
77 reg = <0x0 0x3>;
90 arm,psci-suspend-param = <0x0010000>;
104 cpu0_opp_table: opp-table-0 {
144 #clock-cells = <0>;
162 #clock-cells = <0>;
[all …]
H A Dpx30.dtsi40 #size-cells = <0>;
42 cpu0: cpu@0 {
45 reg = <0x0 0x0>;
57 reg = <0x0 0x1>;
69 reg = <0x0 0x2>;
81 reg = <0x0 0x3>;
96 arm,psci-suspend-param = <0x0010000>;
105 arm,psci-suspend-param = <0x1010000>;
113 cpu0_opp_table: opp-table-0 {
164 #clock-cells = <0>;
[all …]