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/openbmc/qemu/tests/tcg/mips/user/ase/dsp/
H A Dtest_dsp_r1_maq_sa_w_phl.c13 achi = 0x00000000; in main()
14 acli = 0x0000B4CB; in main()
15 rs = 0xFF060000; in main()
16 rt = 0xCB000000; in main()
17 resulth = 0x00000000; in main()
18 resultl = 0x006838CB; in main()
24 "mfhi %0, $ac1\n\t" in main()
32 achi = 0x00000000; in main()
33 acli = 0x0000B4CB; in main()
34 rs = 0x80000000; in main()
[all …]
H A Dtest_dsp_r1_maq_s_w_phl.c13 achi = 0x00000005; in main()
14 acli = 0x0000B4CB; in main()
15 rs = 0xFF060000; in main()
16 rt = 0xCB000000; in main()
17 resulth = 0x00000005; in main()
18 resultl = 0x006838CB; in main()
24 "mfhi %0, $ac1\n\t" in main()
32 achi = 0x00000006; in main()
33 acli = 0x0000B4CB; in main()
34 rs = 0x80000000; in main()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/can/
H A Dxilinx,can.yaml121 reg = <0xe0008000 0x1000>;
126 tx-fifo-depth = <0x40>;
127 rx-fifo-depth = <0x40>;
133 reg = <0x40000000 0x10000>;
134 clocks = <&clkc 0>, <&clkc 1>;
138 tx-fifo-depth = <0x40>;
139 rx-fifo-depth = <0x40>;
145 reg = <0x40000000 0x2000>;
146 clocks = <&clkc 0>, <&clkc 1>;
150 tx-mailbox-count = <0x20>;
[all …]
/openbmc/qemu/tests/qtest/
H A Dxlnx-can-test.c31 #define CAN0_BASE_ADDR 0xFF060000
32 #define CAN1_BASE_ADDR 0xFF070000
35 #define R_SRR_OFFSET 0x00
36 #define R_MSR_OFFSET 0x04
37 #define R_SR_OFFSET 0x18
38 #define R_ISR_OFFSET 0x1C
39 #define R_ICR_OFFSET 0x24
40 #define R_TXID_OFFSET 0x30
41 #define R_TXDLC_OFFSET 0x34
42 #define R_TXDATA1_OFFSET 0x38
[all …]
H A Dxlnx-canfd-test.c33 #define CANFD0_BASE_ADDR 0xff060000
34 #define CANFD1_BASE_ADDR 0xff070000
37 #define R_SRR_OFFSET 0x00
38 #define R_MSR_OFFSET 0x04
39 #define R_FILTER_CONTROL_REGISTER 0xe0
40 #define R_SR_OFFSET 0x18
41 #define R_ISR_OFFSET 0x1c
42 #define R_IER_OFFSET 0x20
43 #define R_ICR_OFFSET 0x24
44 #define R_TX_READY_REQ_REGISTER 0x90
[all …]
/openbmc/qemu/hw/arm/
H A Dxlnx-zynqmp.c39 #define GEM_REVISION 0x40070106
41 #define GIC_BASE_ADDR 0xf9000000
42 #define GIC_DIST_ADDR 0xf9010000
43 #define GIC_CPU_ADDR 0xf9020000
44 #define GIC_VIFACE_ADDR 0xf9040000
45 #define GIC_VCPU_ADDR 0xf9060000
48 #define SATA_ADDR 0xFD0C0000
51 #define QSPI_ADDR 0xff0f0000
52 #define LQSPI_ADDR 0xc0000000
54 #define QSPI_DMA_ADDR 0xff0f0800
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp.dtsi22 #size-cells = <0>;
24 cpu0: cpu@0 {
29 reg = <0x0>;
37 reg = <0x1>;
46 reg = <0x2>;
55 reg = <0x3>;
63 CPU_SLEEP_0: cpu-sleep-0 {
65 arm,psci-suspend-param = <0x40000000>;
108 interrupts = <0 143 4>,
109 <0 144 4>,
[all …]
/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp.dtsi29 #size-cells = <0>;
31 cpu0: cpu@0 {
36 reg = <0x0>;
45 reg = <0x1>;
55 reg = <0x2>;
65 reg = <0x3>;
80 CPU_SLEEP_0: cpu-sleep-0 {
82 arm,psci-suspend-param = <0x40000000>;
123 reg = <0x0 0x3ed00000 0x0 0x40000>;
128 reg = <0x0 0x3ef00000 0x0 0x40000>;
[all …]
/openbmc/linux/sound/soc/rockchip/
H A Drockchip_i2s_tdm.c30 #define TRCM_TXRX 0
106 * Returns success (0) or negative errno.
110 int ret = 0; in i2s_tdm_prepare_enable_mclk()
119 return 0; in i2s_tdm_prepare_enable_mclk()
136 return 0; in i2s_tdm_runtime_suspend()
159 return 0; in i2s_tdm_runtime_resume()
176 * when clk_trcm > 0.
217 unsigned int xfer_mask = 0; in rockchip_snd_xfer_clear()
218 unsigned int xfer_val = 0; in rockchip_snd_xfer_clear()
284 /* only used when clk_trcm > 0 */
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3308.dtsi39 #size-cells = <0>;
41 cpu0: cpu@0 {
44 reg = <0x0 0x0>;
57 reg = <0x0 0x1>;
67 reg = <0x0 0x2>;
77 reg = <0x0 0x3>;
90 arm,psci-suspend-param = <0x0010000>;
104 cpu0_opp_table: opp-table-0 {
144 #clock-cells = <0>;
162 #clock-cells = <0>;
[all …]
H A Drk3328.dtsi36 #size-cells = <0>;
38 cpu0: cpu@0 {
41 reg = <0x0 0x0>;
54 reg = <0x0 0x1>;
67 reg = <0x0 0x2>;
80 reg = <0x0 0x3>;
96 arm,psci-suspend-param = <0x0010000>;
110 cpu0_opp_table: opp-table-0 {
208 #clock-cells = <0>;
215 reg = <0x0 0xff000000 0x0 0x1000>;
[all …]
H A Dpx30.dtsi40 #size-cells = <0>;
42 cpu0: cpu@0 {
45 reg = <0x0 0x0>;
57 reg = <0x0 0x1>;
69 reg = <0x0 0x2>;
81 reg = <0x0 0x3>;
96 arm,psci-suspend-param = <0x0010000>;
105 arm,psci-suspend-param = <0x1010000>;
113 cpu0_opp_table: opp-table-0 {
164 #clock-cells = <0>;
[all …]