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/openbmc/u-boot/arch/arm/mach-rmobile/
H A Dcpu_info-rcar.c10 #define PRR_MASK 0x7fff
11 #define R8A7796_REV_1_0 0x5200
12 #define R8A7796_REV_1_1 0x5210
17 return readl(0xFFF00044); in rmobile_get_prr()
19 return readl(0xFF000044); in rmobile_get_prr()
25 return (rmobile_get_prr() & 0x00007F00) >> 8; in rmobile_get_cpu_type()
35 return ((prr & 0x000000F0) >> 4) + 1; in rmobile_get_cpu_rev_integer()
45 return prr & 0x0000000F; in rmobile_get_cpu_rev_fraction()
H A Dlowlevel_init_ca15.S14 mrc p15, 0, r4, c0, c0, 5 /* mpidr */
16 and r4, r4, #7 /* id 0-3 = ca15.0,1,2,3 */
27 ldr r1, =0xe6180000 /* sysc */
28 1: ldr r0, [r1, #0x20] /* sbar */
34 * Only CPU ID #0 comes here
38 ldr r2, =0xFF000044 /* PRR */
40 and r1, r1, #0x7F00
42 cmp r1, #0x4C /* 0x4C is ID of r8a7794 */
47 mrceq p15, 0, r0, c1, c0, 1 /* actlr */
49 mcreq p15, 0, r0, c1, c0, 1
[all …]
/openbmc/linux/Documentation/devicetree/bindings/hwinfo/
H A Drenesas,prr.yaml36 reg = <0xff000044 4>;
/openbmc/linux/drivers/soc/renesas/
H A Drenesas-soc.c23 .reg = 0xff000044, /* PRR (Product Register) */
28 .reg = 0xff000044, /* PRR (Product Register) */
33 .reg = 0xfff00044, /* PRR (Product Register) */
42 .reg = 0xe600101c, /* CCCR (Common Chip Code Register) */
59 .reg = 0xff000044, /* PRR (Product Register) */
64 .reg = 0xfff00044, /* PRR (Product Register) */
85 .reg = 0xe600101c, /* CCCR (Common Chip Code Register) */
100 .id = 0x3b,
105 .id = 0x3f,
110 .id = 0x40,
[all …]
/openbmc/u-boot/arch/sh/include/asm/
H A Dcpu_sh7757.h9 #define CCR 0xFF00001C
10 #define WTCNT 0xFFCC0000
11 #define CCR_CACHE_INIT 0x0000090b
20 #define MMU_BASE ((struct mmu_regs *)0xff000000)
23 #define WTCSR0 0xffcc0002
24 #define WRSTCSR_R 0xffcc0003
25 #define WRSTCSR_W 0xffcc0002
26 #define WTCSR_PREFIX 0xa500
27 #define WRSTCSR_PREFIX 0x6900
28 #define WRSTCSR_WOVF_PREFIX 0x9600
[all …]
/openbmc/linux/arch/sh/include/asm/
H A Dprocessor_32.h19 #define CCN_PVR 0xff000030
20 #define CCN_CVR 0xff000040
21 #define CCN_PRR 0xff000044
26 * Since SH7709 and SH7750 have "area 7", we can't use 0x7c000000--0x7fffffff
28 #define TASK_SIZE 0x7c000000UL
48 #define SR_DSP 0x00001000
49 #define SR_IMASK 0x000000f0
50 #define SR_FD 0x00008000
51 #define SR_MD 0x40000000
53 #define SR_USER_MASK 0x00000303 // M, Q, S, T bits
[all …]
/openbmc/u-boot/board/renesas/stout/
H A Dstout_spl.c26 #define SD2CKCR 0xE615026C
27 #define SD_97500KHZ 0x7
37 static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000; in dbsc_wait()
39 while (!(readl(dbsc3_0_base + reg) & BIT(0))) in dbsc_wait()
42 while (!(readl(dbsc3_1_base + reg) & BIT(0))) in dbsc_wait()
48 u32 r0 = 0; in spl_init_sys()
50 writel(0xa5a5a500, 0xe6020004); in spl_init_sys()
51 writel(0xa5a5a500, 0xe6030004); in spl_init_sys()
55 "mcr 15, 0, %0, cr7, cr5, 0 \n" in spl_init_sys()
57 "mcr 15, 0, %0, cr7, cr5, 6 \n" in spl_init_sys()
[all …]
/openbmc/u-boot/board/renesas/porter/
H A Dporter_spl.c26 #define SD2CKCR 0xE615026C
27 #define SD_97500KHZ 0x7
37 static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000; in dbsc_wait()
39 while (!(readl(dbsc3_0_base + reg) & BIT(0))) in dbsc_wait()
42 while (!(readl(dbsc3_1_base + reg) & BIT(0))) in dbsc_wait()
48 u32 r0 = 0; in spl_init_sys()
50 writel(0xa5a5a500, 0xe6020004); in spl_init_sys()
51 writel(0xa5a5a500, 0xe6030004); in spl_init_sys()
55 "mcr 15, 0, %0, cr7, cr5, 0 \n" in spl_init_sys()
57 "mcr 15, 0, %0, cr7, cr5, 6 \n" in spl_init_sys()
[all …]
/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dr8a7779.dtsi22 #size-cells = <0>;
24 cpu@0 {
27 reg = <0>;
67 reg = <0xf0001000 0x1000>,
68 <0xf0000100 0x100>;
73 reg = <0xf0000200 0x100>;
81 reg = <0xf0000600 0x20>;
89 reg = <0xffc40000 0x2c>;
93 gpio-ranges = <&pfc 0 0 32>;
100 reg = <0xffc41000 0x2c>;
[all …]
H A Dr8a73a4.dtsi21 #size-cells = <0>;
23 cpu0: cpu@0 {
26 reg = <0>;
33 L2_CA15: cache-controller-0 {
65 reg = <0 0xe6790000 0 0x10000>;
71 reg = <0 0xe67a0000 0 0x10000>;
77 #size-cells = <0>;
79 reg = <0 0xe60b0000 0 0x428>;
89 reg = <0 0xe6130000 0 0x1004>;
108 reg = <0 0xe61c0000 0 0x200>;
[all …]
H A Dr8a7792.dtsi40 #clock-cells = <0>;
42 clock-frequency = <0>;
47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
71 L2_CA15: cache-controller-0 {
82 #clock-cells = <0>;
84 clock-frequency = <0>;
97 #clock-cells = <0>;
99 clock-frequency = <0>;
[all …]
H A Dr8a77470.dtsi27 #size-cells = <0>;
29 cpu0: cpu@0 {
32 reg = <0>;
51 L2_CA7: cache-controller-0 {
62 #clock-cells = <0>;
64 clock-frequency = <0>;
77 #clock-cells = <0>;
79 clock-frequency = <0>;
93 reg = <0 0xe6020000 0 0x0c>;
104 reg = <0 0xe6050000 0 0x50>;
[all …]
H A Dr8a7794.dtsi34 * The external audio clocks are configured as 0 Hz fixed frequency
40 #clock-cells = <0>;
41 clock-frequency = <0>;
45 #clock-cells = <0>;
46 clock-frequency = <0>;
50 #clock-cells = <0>;
51 clock-frequency = <0>;
57 #clock-cells = <0>;
59 clock-frequency = <0>;
64 #size-cells = <0>;
[all …]
H A Dr8a7793.dtsi32 * The external audio clocks are configured as 0 Hz fixed frequency
38 #clock-cells = <0>;
39 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
48 #clock-cells = <0>;
49 clock-frequency = <0>;
55 #clock-cells = <0>;
57 clock-frequency = <0>;
62 #size-cells = <0>;
[all …]
H A Dr8a7745.dtsi36 * The external audio clocks are configured as 0 Hz fixed
42 #clock-cells = <0>;
43 clock-frequency = <0>;
47 #clock-cells = <0>;
48 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
59 #clock-cells = <0>;
61 clock-frequency = <0>;
66 #size-cells = <0>;
[all …]
H A Dr8a7742.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
35 #clock-cells = <0>;
36 clock-frequency = <0>;
42 #clock-cells = <0>;
44 clock-frequency = <0>;
49 #size-cells = <0>;
[all …]
H A Dr8a7791.dtsi40 * The external audio clocks are configured as 0 Hz fixed frequency
46 #clock-cells = <0>;
47 clock-frequency = <0>;
51 #clock-cells = <0>;
52 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
63 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #size-cells = <0>;
[all …]
H A Dr8a7743.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
46 clock-frequency = <0>;
51 #size-cells = <0>;
[all …]
H A Dr8a7744.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
46 clock-frequency = <0>;
51 #size-cells = <0>;
[all …]
H A Dr8a7790.dtsi41 * The external audio clocks are configured as 0 Hz fixed frequency
47 #clock-cells = <0>;
48 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
57 #clock-cells = <0>;
58 clock-frequency = <0>;
64 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #size-cells = <0>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dr8a7792.dtsi39 #clock-cells = <0>;
41 clock-frequency = <0>;
46 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
69 L2_CA15: cache-controller-0 {
80 #clock-cells = <0>;
82 clock-frequency = <0>;
95 #clock-cells = <0>;
97 clock-frequency = <0>;
[all …]
H A Dr8a7794.dtsi34 * The external audio clocks are configured as 0 Hz fixed frequency
40 #clock-cells = <0>;
41 clock-frequency = <0>;
45 #clock-cells = <0>;
46 clock-frequency = <0>;
50 #clock-cells = <0>;
51 clock-frequency = <0>;
57 #clock-cells = <0>;
59 clock-frequency = <0>;
64 #size-cells = <0>;
[all …]
H A Dr8a7793.dtsi32 * The external audio clocks are configured as 0 Hz fixed frequency
38 #clock-cells = <0>;
39 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
48 #clock-cells = <0>;
49 clock-frequency = <0>;
55 #clock-cells = <0>;
57 clock-frequency = <0>;
62 #size-cells = <0>;
[all …]
H A Dr8a7791.dtsi40 * The external audio clocks are configured as 0 Hz fixed frequency
46 #clock-cells = <0>;
47 clock-frequency = <0>;
51 #clock-cells = <0>;
52 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
63 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #size-cells = <0>;
[all …]
H A Dr8a7790.dtsi41 * The external audio clocks are configured as 0 Hz fixed frequency
47 #clock-cells = <0>;
48 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
57 #clock-cells = <0>;
58 clock-frequency = <0>;
64 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #size-cells = <0>;
[all …]