/openbmc/linux/Documentation/devicetree/bindings/pci/ |
H A D | rcar-pci-host.yaml | 115 reg = <0 0xfe000000 0 0x80000>; 118 bus-range = <0x00 0xff>; 120 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 121 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 122 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 123 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 124 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>, 125 <0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>; 130 interrupt-map-mask = <0 0 0 0>; 131 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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H A D | rcar-pci-ep.yaml | 79 reg = <0xfe000000 0x80000>, 80 <0xfe100000 0x100000>, 81 <0xfe200000 0x200000>, 82 <0x30000000 0x8000000>, 83 <0x38000000 0x8000000>;
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/openbmc/linux/arch/arm/mach-mmp/ |
H A D | addr-map.h | 15 #define APB_PHYS_BASE 0xd4000000 16 #define APB_VIRT_BASE IOMEM(0xfe000000) 17 #define APB_PHYS_SIZE 0x00200000 19 #define AXI_PHYS_BASE 0xd4200000 20 #define AXI_VIRT_BASE IOMEM(0xfe200000) 21 #define AXI_PHYS_SIZE 0x00200000 23 #define PGU_PHYS_BASE 0xe0000000 24 #define PGU_VIRT_BASE IOMEM(0xfe400000) 25 #define PGU_PHYS_SIZE 0x00100000 27 /* Static Memory Controller - Chip Select 0 and 1 */ [all …]
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/openbmc/linux/arch/arm/mach-tegra/ |
H A D | iomap.h | 16 #define TEGRA_IRAM_BASE 0x40000000 19 #define TEGRA_ARM_PERIF_BASE 0x50040000 22 #define TEGRA_ARM_INT_DIST_BASE 0x50041000 25 #define TEGRA_TMR1_BASE 0x60005000 28 #define TEGRA_TMR2_BASE 0x60005008 31 #define TEGRA_TMRUS_BASE 0x60005010 34 #define TEGRA_TMR3_BASE 0x60005050 37 #define TEGRA_TMR4_BASE 0x60005058 40 #define TEGRA_CLK_RESET_BASE 0x60006000 43 #define TEGRA_FLOW_CTRL_BASE 0x60007000 [all …]
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/openbmc/u-boot/include/configs/ |
H A D | sh7785lcr.h | 14 "bootdevice=0:1\0" \ 15 "usbload=usb reset;usbboot;usb stop;bootm\0" 22 /* 0x40000000 - 0x47FFFFFF does not use */ 23 #define CONFIG_SH_SDRAM_OFFSET (0x8000000) 24 #define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET) 25 #define SH7785LCR_SDRAM_BASE (0x80000000 + CONFIG_SH_SDRAM_OFFSET) 27 #define SH7785LCR_FLASH_BASE_1 (0xa0000000) 29 #define SH7785LCR_USB_BASE (0xa6000000) 31 #define SH7785LCR_SDRAM_BASE (0x08000000) 33 #define SH7785LCR_FLASH_BASE_1 (0xa0000000) [all …]
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H A D | r7780mp.h | 23 #define CONFIG_SYS_SDRAM_BASE (0x08000000) 29 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) 32 #define CONFIG_SYS_FLASH_BASE (0xA0000000) 39 CONFIG_SYS_FLASH_BASE + 0x100000,\ 40 CONFIG_SYS_FLASH_BASE + 0x400000,\ 41 CONFIG_SYS_FLASH_BASE + 0x700000, } 78 #define CONFIG_SH7780_PCI_LSR 0x07f00001 84 #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ 86 #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ 88 #define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */ [all …]
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/openbmc/linux/Documentation/devicetree/bindings/usb/ |
H A D | dwc3-xilinx.yaml | 81 "^usb@[0-9a-f]+$": 110 usb@0 { 111 #address-cells = <0x2>; 112 #size-cells = <0x2>; 114 reg = <0x0 0xff9d0000 0x0 0x100>; 122 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; 128 reg = <0x0 0xfe200000 0x0 0x40000>; 130 interrupts = <0 65 4>, <0 69 4>;
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/openbmc/linux/arch/powerpc/boot/dts/fsl/ |
H A D | cyrus_p5020.dts | 30 size = <0 0x1000000>; 31 alignment = <0 0x1000000>; 34 size = <0 0x400000>; 35 alignment = <0 0x400000>; 38 size = <0 0x2000000>; 39 alignment = <0 0x2000000>; 44 ranges = <0x00000000 0xf 0x00000000 0x01008000>; 48 ranges = <0x0 0xf 0xf4000000 0x200000>; 52 ranges = <0x0 0xf 0xf4200000 0x200000>; 56 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; [all …]
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H A D | kmcoge4.dts | 30 size = <0 0x1000000>; 31 alignment = <0 0x1000000>; 34 size = <0 0x400000>; 35 alignment = <0 0x400000>; 38 size = <0 0x2000000>; 39 alignment = <0 0x2000000>; 44 ranges = <0x00000000 0xf 0x00000000 0x01008000>; 48 ranges = <0x0 0xf 0xf4000000 0x200000>; 52 ranges = <0x0 0xf 0xf4200000 0x200000>; 56 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; [all …]
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H A D | b4qds.dtsi | 51 reg = <0xf 0xfe124000 0 0x2000>; 52 ranges = <0 0 0xf 0xe8000000 0x08000000 53 2 0 0xf 0xff800000 0x00010000 54 3 0 0xf 0xffdf0000 0x00008000>; 56 nor@0,0 { 60 reg = <0x0 0x0 0x8000000>; 65 nand@2,0 { 69 reg = <0x2 0x0 0x10000>; 71 partition@0 { 74 reg = <0x0 0x00100000>; [all …]
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H A D | p2041rdb.dts | 67 size = <0 0x1000000>; 68 alignment = <0 0x1000000>; 71 size = <0 0x400000>; 72 alignment = <0 0x400000>; 75 size = <0 0x2000000>; 76 alignment = <0 0x2000000>; 81 ranges = <0x00000000 0xf 0x00000000 0x01008000>; 85 ranges = <0x0 0xf 0xf4000000 0x200000>; 89 ranges = <0x0 0xf 0xf4200000 0x200000>; 93 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; [all …]
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H A D | p5020ds.dts | 68 size = <0 0x1000000>; 69 alignment = <0 0x1000000>; 72 size = <0 0x400000>; 73 alignment = <0 0x400000>; 76 size = <0 0x2000000>; 77 alignment = <0 0x2000000>; 82 ranges = <0x00000000 0xf 0x00000000 0x01008000>; 86 ranges = <0x0 0xf 0xf4000000 0x200000>; 90 ranges = <0x0 0xf 0xf4200000 0x200000>; 94 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; [all …]
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H A D | p3041ds.dts | 68 size = <0 0x1000000>; 69 alignment = <0 0x1000000>; 72 size = <0 0x400000>; 73 alignment = <0 0x400000>; 76 size = <0 0x2000000>; 77 alignment = <0 0x2000000>; 82 ranges = <0x00000000 0xf 0x00000000 0x01008000>; 86 ranges = <0x0 0xf 0xf4000000 0x200000>; 90 ranges = <0x0 0xf 0xf4200000 0x200000>; 94 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; [all …]
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H A D | p4080ds.dts | 68 size = <0 0x1000000>; 69 alignment = <0 0x1000000>; 72 size = <0 0x400000>; 73 alignment = <0 0x400000>; 76 size = <0 0x2000000>; 77 alignment = <0 0x2000000>; 82 ranges = <0x00000000 0xf 0x00000000 0x01008000>; 86 ranges = <0x0 0xf 0xf4000000 0x200000>; 90 ranges = <0x0 0xf 0xf4200000 0x200000>; 94 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; [all …]
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H A D | p5040ds.dts | 80 size = <0 0x1000000>; 81 alignment = <0 0x1000000>; 84 size = <0 0x400000>; 85 alignment = <0 0x400000>; 88 size = <0 0x2000000>; 89 alignment = <0 0x2000000>; 94 ranges = <0x00000000 0xf 0x00000000 0x01008000>; 98 ranges = <0x0 0xf 0xf4000000 0x200000>; 102 ranges = <0x0 0xf 0xf4200000 0x200000>; 106 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; [all …]
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/openbmc/linux/arch/sh/drivers/pci/ |
H A D | pci-sh7751.h | 13 #define SH7751_VENDOR_ID 0x1054 14 #define SH7751_DEVICE_ID 0x3505 15 #define SH7751R_DEVICE_ID 0x350e 18 #define SH7751_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */ 19 #define SH7751_PCI_CONFIG_SIZE 0x1000000 /* Config space size */ 20 #define SH7751_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */ 21 #define SH7751_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ 22 #define SH7751_PCI_IO_BASE 0xFE240000 /* IO space base address */ 23 #define SH7751_PCI_IO_SIZE 0x40000 /* Size of IO window */ 25 #define SH7751_PCIREG_BASE 0xFE200000 /* PCI regs base address */ [all …]
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H A D | pci-sh7751.c | 26 if (((word >> area) & 1) == 0) { in __area_sdram_check() 27 printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%lx\n", in __area_sdram_check() 29 return 0; in __area_sdram_check() 35 if (((word >> (area << 1)) & 0x3) != 0x3) { in __area_sdram_check() 36 printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%lx\n", in __area_sdram_check() 38 return 0; in __area_sdram_check() 48 .start = 0x1000, 63 .mem_offset = 0x00000000, 64 .io_offset = 0x00000000, 71 .size = 0x04000000, [all …]
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H A D | pci-sh7780.c | 24 # define PCICR_ENDIANNESS 0 31 .start = 0x1000, 35 .name = "PCI MEM 0", 36 .start = 0xfd000000, 37 .end = 0xfd000000 + SZ_16M - 1, 41 .start = 0x10000000, 42 .end = 0x10000000 + SZ_64M - 1, 49 .start = 0xc0000000, 50 .end = 0xc0000000 + SZ_512M - 1, 59 .io_offset = 0, [all …]
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H A D | pcie-sh7786.c | 44 .name = "PCIe0 MEM 0", 45 .start = 0xfd000000, 46 .end = 0xfd000000 + SZ_8M - 1, 50 .start = 0xc0000000, 51 .end = 0xc0000000 + SZ_512M - 1, 55 .start = 0x10000000, 56 .end = 0x10000000 + SZ_64M - 1, 60 .start = 0xfe100000, 61 .end = 0xfe100000 + SZ_1M - 1, 68 .name = "PCIe1 MEM 0", [all …]
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/openbmc/u-boot/drivers/pci/ |
H A D | pci_sh7751.c | 15 #define SH7751_BCR1 (vu_long *)0xFF800000 16 #define SH7751_BCR2 (vu_short *)0xFF800004 17 #define SH7751_WCR1 (vu_long *)0xFF800008 18 #define SH7751_WCR2 (vu_long *)0xFF80000C 19 #define SH7751_WCR3 (vu_long *)0xFF800010 20 #define SH7751_MCR (vu_long *)0xFF800014 21 #define SH7751_BCR3 (vu_short *)0xFF800050 22 #define SH7751_PCICONF0 (vu_long *)0xFE200000 23 #define SH7751_PCICONF1 (vu_long *)0xFE200004 24 #define SH7751_PCICONF2 (vu_long *)0xFE200008 [all …]
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/openbmc/qemu/include/hw/arm/ |
H A D | xlnx-versal.h | 174 #define MM_TOP_RSVD 0xa0000000U 175 #define MM_TOP_RSVD_SIZE 0x4000000 176 #define MM_GIC_APU_DIST_MAIN 0xf9000000U 177 #define MM_GIC_APU_DIST_MAIN_SIZE 0x10000 178 #define MM_GIC_APU_REDIST_0 0xf9080000U 179 #define MM_GIC_APU_REDIST_0_SIZE 0x80000 181 #define MM_UART0 0xff000000U 182 #define MM_UART0_SIZE 0x10000 183 #define MM_UART1 0xff010000U 184 #define MM_UART1_SIZE 0x10000 [all …]
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/openbmc/linux/arch/arm64/boot/dts/lg/ |
H A D | lg1312.dtsi | 20 #size-cells = <0>; 22 cpu0: cpu@0 { 25 reg = <0x0 0x0>; 31 reg = <0x0 0x1>; 38 reg = <0x0 0x2>; 45 reg = <0x0 0x3>; 59 cpu_suspend = <0x84000001>; 60 cpu_off = <0x84000002>; 61 cpu_on = <0x84000003>; 68 reg = <0x0 0xc0001000 0x1000>, [all …]
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H A D | lg1313.dtsi | 20 #size-cells = <0>; 22 cpu0: cpu@0 { 25 reg = <0x0 0x0>; 31 reg = <0x0 0x1>; 38 reg = <0x0 0x2>; 45 reg = <0x0 0x3>; 59 cpu_suspend = <0x84000001>; 60 cpu_off = <0x84000002>; 61 cpu_on = <0x84000003>; 68 reg = <0x0 0xc0001000 0x1000>, [all …]
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/openbmc/linux/drivers/char/agp/ |
H A D | i460-agp.c | 20 #define INTEL_I460_BAPBASE 0x98 21 #define INTEL_I460_GXBCTL 0xa0 22 #define INTEL_I460_AGPSIZ 0xa2 23 #define INTEL_I460_ATTBASE 0xfe200000 32 #define I460_LARGE_IO_PAGES 0 44 #define I460_AGPSIZ_MASK 0x7 48 #define I460_GXBCTL_OOG (1UL << 0) 91 {32768, 0, 0, 4}, 92 {1024, 0, 0, 2}, 93 {256, 0, 0, 1} [all …]
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/openbmc/linux/arch/arm64/boot/dts/renesas/ |
H A D | r8a774c0.dtsi | 18 * The external audio clocks are configured as 0 Hz fixed frequency 24 #clock-cells = <0>; 25 clock-frequency = <0>; 30 #clock-cells = <0>; 31 clock-frequency = <0>; 36 #clock-cells = <0>; 37 clock-frequency = <0>; 43 #clock-cells = <0>; 44 clock-frequency = <0>; 67 #size-cells = <0>; [all …]
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