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/openbmc/linux/Documentation/devicetree/bindings/display/bridge/
H A Dcdns,dsi.yaml58 port@0:
113 reg = <0x0 0xfd0c0000 0x0 0x1000>;
121 #size-cells = <0>;
125 #size-cells = <0>;
135 panel@0 {
137 reg = <0>;
150 reg = <0x0 0xfd0c0000 0x0 0x1000>;
159 #size-cells = <0>;
161 port@0 {
162 reg = <0>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/ata/
H A Dceva,ahci-1v84.yaml43 OOB timing value for COMINIT parameter for port 0.
55 OOB timing value for COMWAKE parameter for port 0.
67 Burst timing value for COM parameter for port 0.
79 Retry interval timing value for port 0.
174 reg = <0xfd0c0000 0x200>;
176 interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
178 ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
179 ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
180 ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
181 ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
[all …]
/openbmc/qemu/hw/arm/
H A Dxlnx-zynqmp.c39 #define GEM_REVISION 0x40070106
41 #define GIC_BASE_ADDR 0xf9000000
42 #define GIC_DIST_ADDR 0xf9010000
43 #define GIC_CPU_ADDR 0xf9020000
44 #define GIC_VIFACE_ADDR 0xf9040000
45 #define GIC_VCPU_ADDR 0xf9060000
48 #define SATA_ADDR 0xFD0C0000
51 #define QSPI_ADDR 0xff0f0000
52 #define LQSPI_ADDR 0xc0000000
54 #define QSPI_DMA_ADDR 0xff0f0800
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp.dtsi22 #size-cells = <0>;
24 cpu0: cpu@0 {
29 reg = <0x0>;
37 reg = <0x1>;
46 reg = <0x2>;
55 reg = <0x3>;
63 CPU_SLEEP_0: cpu-sleep-0 {
65 arm,psci-suspend-param = <0x40000000>;
108 interrupts = <0 143 4>,
109 <0 144 4>,
[all …]
/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp.dtsi29 #size-cells = <0>;
31 cpu0: cpu@0 {
36 reg = <0x0>;
45 reg = <0x1>;
55 reg = <0x2>;
65 reg = <0x3>;
80 CPU_SLEEP_0: cpu-sleep-0 {
82 arm,psci-suspend-param = <0x40000000>;
123 reg = <0x0 0x3ed00000 0x0 0x40000>;
128 reg = <0x0 0x3ef00000 0x0 0x40000>;
[all …]