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/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Drenesas,mtu2.yaml18 independent. The MTU2 hardware supports five channels indexed from 0 to 4.
70 reg = <0xfcff0000 0x400>;
/openbmc/linux/drivers/net/ethernet/ti/icssg/
H A Dicssg_config.c21 #define MII_RT_TX_IPG_100M 0x17
22 #define MII_RT_TX_IPG_1G 0xb
25 #define ICSSG_QUEUE_OFFSET 0xd00
26 #define ICSSG_QUEUE_PEEK_OFFSET 0xe00
27 #define ICSSG_QUEUE_CNT_OFFSET 0xe40
28 #define ICSSG_QUEUE_RESET_OFFSET 0xf40
64 #define FDB_GEN_CFG1 0x60
68 #define FDB_GEN_CFG2 0x64
72 #define FDB_PRU0_EN BIT(0)
93 { PORT_HI_Q_SLICE0, PORT_DESC0_HI, 0x200000, 0 },
[all …]
/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dr7s72100.dtsi32 #clock-cells = <0>;
41 #size-cells = <0>;
43 cpu@0 {
46 reg = <0>;
55 #clock-cells = <0>;
58 clock-frequency = <0>;
62 #clock-cells = <0>;
70 #clock-cells = <0>;
79 interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
83 #clock-cells = <0>;
[all …]
/openbmc/linux/arch/parisc/kernel/
H A Dperf_images.h27 0x4c00c000, 0x00000000, 0x00060000, 0x00000000,
28 0xe0e0e0e0, 0x004e0004, 0x07ffffff, 0xffc01380,
29 0x0101ffff, 0xfffff104, 0xe000c07f, 0xfffffffc,
30 0x01380010, 0x1fffffff, 0xff000000, 0x00000000,
31 0x00000fff, 0xff00000f, 0xffff0000, 0x0fffff00,
32 0x000fffff, 0x00000000, 0x00000000, 0x00ffffff,
33 0xfffff000, 0x0000000f, 0xffffffff, 0xff000000,
34 0x0000ffff, 0xfffffff0, 0x00000000, 0x0fffffff,
35 0xffff0000, 0x00000000, 0x6fffffff, 0xffffffff,
36 0xfff55fff, 0xffffffff, 0xffffffff, 0xf0000000,
[all …]