21 #define MII_RT_TX_IPG_100M	0x17
22 #define MII_RT_TX_IPG_1G	0xb
25 #define	ICSSG_QUEUE_OFFSET		0xd00
26 #define	ICSSG_QUEUE_PEEK_OFFSET		0xe00
27 #define	ICSSG_QUEUE_CNT_OFFSET		0xe40
28 #define	ICSSG_QUEUE_RESET_OFFSET	0xf40
64 #define FDB_GEN_CFG1		0x60
68 #define FDB_GEN_CFG2		0x64
72 #define FDB_PRU0_EN		BIT(0)
93 		{ PORT_HI_Q_SLICE0, PORT_DESC0_HI, 0x200000, 0 },
94 		{ PORT_LO_Q_SLICE0, PORT_DESC0_LO, 0, 0 },
95 		{ HOST_HI_Q_SLICE0, HOST_DESC0_HI, 0x200000, 0 },
96 		{ HOST_LO_Q_SLICE0, HOST_DESC0_LO, 0, 0 },
97 		{ HOST_SPL_Q_SLICE0, HOST_SPPD0, 0x400000, 1 },
100 		{ PORT_HI_Q_SLICE1, PORT_DESC1_HI, 0xa00000, 0 },
101 		{ PORT_LO_Q_SLICE1, PORT_DESC1_LO, 0x800000, 0 },
102 		{ HOST_HI_Q_SLICE1, HOST_DESC1_HI, 0xa00000, 0 },
103 		{ HOST_LO_Q_SLICE1, HOST_DESC1_LO, 0x800000, 0 },
104 		{ HOST_SPL_Q_SLICE1, HOST_SPPD1, 0xc00000, 1 },
140 	regmap_write(mii_rt, pcnt_reg, 0x1);  in icssg_config_mii_init()
148 	int queue = 0, i, j;  in icssg_miig_queues_init()
155 	for (i = 0; i < ICSSG_NUM_TX_QUEUES; i++) {  in icssg_miig_queues_init()
163 	for (i = 0; i < ICSSG_NUM_OTHER_QUEUES; i++) {  in icssg_miig_queues_init()
172 	for (j = 0; j < ICSSG_NUM_OTHER_QUEUES; j++) {  in icssg_miig_queues_init()
186 		for (i = 0; i < num_pds; i++) {  in icssg_miig_queues_init()
187 			memset(pd, 0, pd_size);  in icssg_miig_queues_init()
189 			pdword[0] &= ICSSG_FLAG_MASK;  in icssg_miig_queues_init()
190 			pdword[0] |= mp->flags;  in icssg_miig_queues_init()
231 	for (i = 0; i < 4; i++)  in emac_r30_cmd_init()
243 	for (i = 0; i < 4; i++) {  in emac_r30_is_done()
246 			return 0;  in emac_r30_is_done()
275 	/* workaround for f/w bug. bpool 0 needs to be initilalized */  in prueth_emac_buffer_setup()
276 	writel(addr, &bpool_cfg[0].addr);  in prueth_emac_buffer_setup()
277 	writel(0, &bpool_cfg[0].len);  in prueth_emac_buffer_setup()
294 	for (i = 0; i < 3; i++)  in prueth_emac_buffer_setup()
302 	for (i = 0; i < 3; i++)  in prueth_emac_buffer_setup()
308 	return 0;  in prueth_emac_buffer_setup()
314 	 * back to the emac mode, the host mac address has to be set as 0.  in icssg_init_emac_mode()
316 	u8 mac[ETH_ALEN] = { 0 };  in icssg_init_emac_mode()
322 			   SMEM_VLAN_OFFSET_MASK, 0);  in icssg_init_emac_mode()
323 	regmap_write(prueth->miig_rt, FDB_GEN_CFG2, 0);  in icssg_init_emac_mode()
336 	memset_io(config, 0, TAS_GATE_MASK_LIST0);  in icssg_config()
360 	/* set C28 to 0x100 */  in icssg_config()
361 	pru_rproc_set_ctable(prueth->pru[slice], PRU_C28, 0x100 << 8);  in icssg_config()
362 	pru_rproc_set_ctable(prueth->rtu[slice], PRU_C28, 0x100 << 8);  in icssg_config()
363 	pru_rproc_set_ctable(prueth->txpru[slice], PRU_C28, 0x100 << 8);  in icssg_config()
367 	writew(0, &flow_cfg->mgm_base_flow);  in icssg_config()
368 	writeb(0, config + SPL_PKT_DEFAULT_PRIORITY);  in icssg_config()
369 	writeb(0, config + QUEUE_NUM_UNTAGGED);  in icssg_config()
377 	return 0;  in icssg_config()
382 	{{0xffff0004, 0xffff0100, 0xffff0004, EMAC_NONE}},	/* EMAC_PORT_DISABLE */
383 	{{0xfffb0040, 0xfeff0200, 0xfeff0200, EMAC_NONE}},	/* EMAC_PORT_BLOCK */
384 	{{0xffbb0000, 0xfcff0000, 0xdcfb0000, EMAC_NONE}},	/* EMAC_PORT_FORWARD */
385 	{{0xffbb0000, 0xfcff0000, 0xfcff2000, EMAC_NONE}},	/* EMAC_PORT_FORWARD_WO_LEARNING */
386 	{{0xffff0001, EMAC_NONE,  EMAC_NONE, EMAC_NONE}},	/* ACCEPT ALL */
387 	{{0xfffe0002, EMAC_NONE,  EMAC_NONE, EMAC_NONE}},	/* ACCEPT TAGGED */
388 	{{0xfffc0000, EMAC_NONE,  EMAC_NONE, EMAC_NONE}},	/* ACCEPT UNTAGGED and PRIO */
389 	{{EMAC_NONE,  0xffff0020, EMAC_NONE, EMAC_NONE}},	/* TAS Trigger List change */
390 	{{EMAC_NONE,  0xdfff1000, EMAC_NONE, EMAC_NONE}},	/* TAS set state ENABLE*/
391 	{{EMAC_NONE,  0xefff2000, EMAC_NONE, EMAC_NONE}},	/* TAS set state RESET*/
392 	{{EMAC_NONE,  0xcfff0000, EMAC_NONE, EMAC_NONE}},	/* TAS set state DISABLE*/
393 	{{EMAC_NONE,  EMAC_NONE,  0xffff0400, EMAC_NONE}},	/* UC flooding ENABLE*/
394 	{{EMAC_NONE,  EMAC_NONE,  0xfbff0000, EMAC_NONE}},	/* UC flooding DISABLE*/
395 	{{EMAC_NONE,  EMAC_NONE,  0xffff0800, EMAC_NONE}},	/* MC flooding ENABLE*/
396 	{{EMAC_NONE,  EMAC_NONE,  0xf7ff0000, EMAC_NONE}},	/* MC flooding DISABLE*/
397 	{{EMAC_NONE,  0xffff4000, EMAC_NONE, EMAC_NONE}},	/* Preemption on Tx ENABLE*/
398 	{{EMAC_NONE,  0xbfff0000, EMAC_NONE, EMAC_NONE}},	/* Preemption on Tx DISABLE*/
399 	{{0xffff0010,  EMAC_NONE, 0xffff0010, EMAC_NONE}},	/* VLAN AWARE*/
400 	{{0xffef0000,  EMAC_NONE, 0xffef0000, EMAC_NONE}}	/* VLAN UNWARE*/
408 	int done = 0;  in emac_set_port_state()
421 	for (i = 0; i < 4; i++)  in emac_set_port_state()