Searched +full:0 +full:xfc030000 (Results 1 – 10 of 10) sorted by relevance
85 reg = <0xfc030000 0x100>;95 … dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>;
39 #define ROM_SIZE 0x20000041 #define PCSR_EN 0x000142 #define PCSR_RLD 0x000243 #define PCSR_PIF 0x000444 #define PCSR_PIE 0x000845 #define PCSR_OVW 0x001046 #define PCSR_DBG 0x002047 #define PCSR_DOZE 0x004049 #define PCSR_PRE_MASK 0x0f0051 #define RCR_SOFTRST 0x80[all …]
24 #define MCFICM_INTC0 0xFC048000 /* Base for Interrupt Ctrl 0 */25 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */26 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */27 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */28 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */29 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */30 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */31 #define MCFINTC_SIMR 0x1c /* Set interrupt mask 0-63 */32 #define MCFINTC_CIMR 0x1d /* Clear interrupt mask 0-63 */33 #define MCFINTC_ICR0 0x40 /* Base ICR register */[all …]
40 #define MCF_WTM_WCR 0xFC09800045 #define MCFSIM_IPRL 0xFC04800446 #define MCFSIM_IPRH 0xFC04800048 #define MCFSIM_IMRL 0xFC04800C49 #define MCFSIM_IMRH 0xFC04800851 #define MCFSIM_ICR0 0xFC048040 52 #define MCFSIM_ICR1 0xFC048041 53 #define MCFSIM_ICR2 0xFC048042 54 #define MCFSIM_ICR3 0xFC048043 55 #define MCFSIM_ICR4 0xFC048044 [all …]
15 #define ATMEL_ID_FIQ 0 /* FIQ Interrupt */21 #define ATMEL_ID_USART0 6 /* USART 0 */23 #define ATMEL_ID_DMA0 8 /* DMA Controller 0 */40 #define ATMEL_ID_UART0 27 /* UART 0 */45 #define ATMEL_ID_TWI0 32 /* Two-Wire Interface 0 */48 #define ATMEL_ID_MCI0 35 /* High Speed Multimedia Card Interface 0 */50 #define ATMEL_ID_SPI0 37 /* Serial Peripheral Interface 0 */53 #define ATMEL_ID_TC0 40 /* Timer Counter 0 (ch. 0, 1, 2) */61 #define ATMEL_ID_SSC0 48 /* Synchronous Serial Controller 0 */67 #define ATMEL_ID_GMAC0 54 /* Ethernet MAC 0 */[all …]
12 #define MMAP_SCM1 0xEC00000013 #define MMAP_MDHA 0xEC08000014 #define MMAP_SKHA 0xEC08400015 #define MMAP_RNG 0xEC08800016 #define MMAP_SCM2 0xFC00000017 #define MMAP_XBS 0xFC00400018 #define MMAP_FBCS 0xFC00800019 #define MMAP_CAN 0xFC02000020 #define MMAP_FEC 0xFC03000021 #define MMAP_SCM3 0xFC040000[all …]
13 #define MMAP_SCM1 0xFC00000014 #define MMAP_XBS 0xFC00400015 #define MMAP_FBCS 0xFC00800016 #define MMAP_FEC0 0xFC03000017 #define MMAP_FEC1 0xFC03400018 #define MMAP_RTC 0xFC03C00019 #define MMAP_SCM2 0xFC04000020 #define MMAP_EDMA 0xFC04400021 #define MMAP_INTC0 0xFC04800022 #define MMAP_INTC1 0xFC04C000[all …]
29 #size-cells = <0>;31 cpu@0 {34 reg = <0>;41 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;46 reg = <0x740000 0x1000>;62 reg = <0x73c000 0x1000>;78 reg = <0x20000000 0x20000000>;84 #clock-cells = <0>;85 clock-frequency = <0>;90 #clock-cells = <0>;[all …]
47 #size-cells = <0>;49 cpu@0 {52 reg = <0>;59 reg = <0x20000000 0x20000000>;65 #clock-cells = <0>;66 clock-frequency = <0>;71 #clock-cells = <0>;72 clock-frequency = <0>;77 #clock-cells = <0>;84 reg = <0x00210000 0x10000>;[all …]
82 #size-cells = <0>;84 cpu@0 {87 reg = <0>;93 reg = <0x20000000 0x20000000>;99 #clock-cells = <0>;100 clock-frequency = <0>;105 #clock-cells = <0>;106 clock-frequency = <0>;111 #clock-cells = <0>;118 reg = <0x00210000 0x10000>;[all …]