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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Datmel-hsmci.txt26 reg = <0xf0008000 0x600>;
29 #size-cells = <0>;
49 slot@0 {
50 reg = <0>;
52 cd-gpios = <&pioD 15 0>
59 reg = <0xf0008000 0x600>;
62 #size-cells = <0>;
63 slot@0 {
64 reg = <0>;
66 cd-gpios = <&pioD 15 0>
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dnuvoton,npcm7xx-timer.yaml25 - description: The timer interrupt of timer 0
29 - description: The reference clock for timer 0
52 reg = <0xf0008000 0x50>;
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Datmel,isc.yaml41 const: 0
64 enum: [0, 1]
68 enum: [0, 1]
72 enum: [0, 1]
97 reg = <0xf0008000 0x4000>;
101 #clock-cells = <0>;
108 vsync-active = <0>;
/openbmc/u-boot/arch/arc/dts/
H A Dhsdk.dts23 #clock-cells = <0>;
61 reg = <0xf0000000 0x10>, <0xf00014B8 0x4>;
67 reg = <0xf0005000 0x1000>;
75 reg = <0xf0008000 0x2000>;
79 ehci@0xf0040000 {
81 reg = <0xf0040000 0x100>;
84 ohci@0xf0060000 {
86 reg = <0xf0060000 0x100>;
91 reg = <0xf0020000 0x1000>;
93 #size-cells = <0>;
[all …]
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91sam9x5.h17 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
23 #define ATMEL_ID_USART0 5 /* USART 0 */
27 #define ATMEL_ID_TWI0 9 /* Two-Wire Interface 0 */
30 #define ATMEL_ID_HSMCI0 12 /* High Speed Multimedia Card Interface 0 */
31 #define ATMEL_ID_SPI0 13 /* Serial Peripheral Interface 0 */
33 #define ATMEL_ID_UART0 15 /* UART 0 */
35 #define ATMEL_ID_TC01 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
38 #define ATMEL_ID_DMAC0 20 /* DMA Controller 0 */
53 #define ATMEL_BASE_SPI0 0xf0000000
54 #define ATMEL_BASE_SPI1 0xf0004000
[all …]
H A Dsama5d4.h15 #define ATMEL_ID_FIQ 0 /* FIQ Interrupt */
21 #define ATMEL_ID_USART0 6 /* USART 0 */
23 #define ATMEL_ID_DMA0 8 /* DMA Controller 0 */
40 #define ATMEL_ID_UART0 27 /* UART 0 */
45 #define ATMEL_ID_TWI0 32 /* Two-Wire Interface 0 */
48 #define ATMEL_ID_MCI0 35 /* High Speed Multimedia Card Interface 0 */
50 #define ATMEL_ID_SPI0 37 /* Serial Peripheral Interface 0 */
53 #define ATMEL_ID_TC0 40 /* Timer Counter 0 (ch. 0, 1, 2) */
61 #define ATMEL_ID_SSC0 48 /* Synchronous Serial Controller 0 */
67 #define ATMEL_ID_GMAC0 54 /* Ethernet MAC 0 */
[all …]
/openbmc/qemu/tests/qtest/
H A Dnpcm7xx_watchdog_timer-test.c23 #define WTCR_OFFSET 0x1c
34 #define WTR BIT(0)
44 .base_addr = 0xf0008000
48 .base_addr = 0xf0009000
52 .base_addr = 0xf000a000
60 g_assert(diff >= 0 && diff < ARRAY_SIZE(watchdog_list)); in watchdog_index()
79 case 0: in watchdog_prescaler()
145 WTCLK(0) | WTE | WTRF | WTRE | WTIF | WTIE | WTR); in test_reset_action()
147 WTCLK(0) | WTE | WTRE | WTIE); in test_reset_action()
152 WTCLK(0) | WTE | WTIF | WTIE | WTRE); in test_reset_action()
[all …]
H A Dnpcm7xx_timer-test.c26 #define MODE_ONESHOT (0 << 27)
33 #define TISR 0x18
34 #define WTCR 0x1c
62 .base_addr = 0xf0008000,
66 .base_addr = 0xf0009000,
70 .base_addr = 0xf000a000,
76 .tcsr_offset = 0x00,
77 .ticr_offset = 0x08,
78 .tdr_offset = 0x10,
80 .tcsr_offset = 0x04,
[all …]
/openbmc/linux/arch/arm/probes/
H A Ddecode-thumb.c20 DECODE_REJECT (0xfe4f0000, 0xe80f0000),
24 DECODE_REJECT (0xffc00000, 0xe8000000),
27 DECODE_REJECT (0xffc00000, 0xe9800000),
30 DECODE_REJECT (0xfe508000, 0xe8008000),
32 DECODE_REJECT (0xfe50c000, 0xe810c000),
34 DECODE_REJECT (0xfe402000, 0xe8002000),
40 DECODE_CUSTOM (0xfe400000, 0xe8000000, PROBES_T32_LDMSTM),
50 DECODE_OR (0xff600000, 0xe8600000),
53 DECODE_EMULATEX (0xff400000, 0xe9400000, PROBES_T32_LDRDSTRD,
54 REGS(NOPCWB, NOSPPC, NOSPPC, 0, 0)),
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9n12.dtsi42 #size-cells = <0>;
44 cpu@0 {
47 reg = <0>;
53 reg = <0x20000000 0x10000000>;
59 #clock-cells = <0>;
60 clock-frequency = <0>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
72 reg = <0x00300000 0x8000>;
75 ranges = <0 0x00300000 0x8000>;
[all …]
H A Dat91sam9x5.dtsi44 #size-cells = <0>;
46 cpu@0 {
49 reg = <0>;
55 reg = <0x20000000 0x10000000>;
61 #clock-cells = <0>;
62 clock-frequency = <0>;
67 #clock-cells = <0>;
68 clock-frequency = <0>;
73 #clock-cells = <0>;
80 reg = <0x00300000 0x8000>;
[all …]
H A Dsama5d2.dtsi29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
41 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
46 reg = <0x740000 0x1000>;
62 reg = <0x73c000 0x1000>;
78 reg = <0x20000000 0x20000000>;
84 #clock-cells = <0>;
85 clock-frequency = <0>;
90 #clock-cells = <0>;
[all …]
H A Dsama5d3.dtsi46 #size-cells = <0>;
47 cpu@0 {
50 reg = <0x0>;
56 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
61 reg = <0x20000000 0x8000000>;
67 #clock-cells = <0>;
68 clock-frequency = <0>;
73 #clock-cells = <0>;
74 clock-frequency = <0>;
79 #clock-cells = <0>;
[all …]
H A Dsam9x60.dtsi37 #size-cells = <0>;
39 cpu@0 {
42 reg = <0>;
48 reg = <0x20000000 0x10000000>;
54 #clock-cells = <0>;
59 #clock-cells = <0>;
65 reg = <0x00300000 0x100000>;
68 ranges = <0 0x00300000 0x100000>;
79 #size-cells = <0>;
81 reg = <0x00500000 0x100000
[all …]
H A Dsama5d4.dtsi47 #size-cells = <0>;
49 cpu@0 {
52 reg = <0>;
59 reg = <0x20000000 0x20000000>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #clock-cells = <0>;
72 clock-frequency = <0>;
77 #clock-cells = <0>;
84 reg = <0x00210000 0x10000>;
[all …]
/openbmc/u-boot/cmd/aspeed/nettest/
H A Dncsi.c35 …PRINTF( FP_LOG, "[NCSI-Request] DA : %02x %02x %02x %02x %02x %02x\n", in->DA[ 0 ], in… in ncsi_reqdump()
36 …PRINTF( FP_LOG, "[NCSI-Request] SA : %02x %02x %02x %02x %02x %02x\n", in->SA[ 0 ], in… in ncsi_reqdump()
38 …, in->MC_ID );//Management Controller should set this field to 0x00 in ncsi_reqdump()
39 …2x\n", in->Header_Revision );//For NC-SI 1.0 spec, this field has to set 0x01 in ncsi_reqdump()
40 …eserved_1 : %02x\n", in->Reserved_1 ); //Reserved has to set to 0x00 in ncsi_reqdump()
51 for ( i = 0; i < SWAP_2B_BEDN( in->Payload_Length ); i++ ) { in ncsi_reqdump()
53 case 0 : PRINTF( FP_LOG, "[NCSI-Request] Payload_Data : %02x", in->Payload_Data[ i ]); break; in ncsi_reqdump()
63 …x %02x %02x %02x\n", in->DA[ 5 ], in->DA[ 4 ], in->DA[ 3 ], in->DA[ 2 ], in->DA[ 1] , in->DA[ 0 ]); in ncsi_respdump()
64 …x %02x %02x %02x\n", in->SA[ 5 ], in->SA[ 4 ], in->SA[ 3 ], in->SA[ 2 ], in->SA[ 1] , in->SA[ 0 ]); in ncsi_respdump()
65 …PRINTF( FP_LOG, "[NCSI-Respond] DA : %02x %02x %02x %02x %02x %02x\n", in->DA[ 0 ], in… in ncsi_respdump()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dat91sam9n12.dtsi48 reg = <0x20000000 0x10000000>;
54 #clock-cells = <0>;
55 clock-frequency = <0>;
60 #clock-cells = <0>;
61 clock-frequency = <0>;
67 reg = <0x00300000 0x8000>;
88 reg = <0xfffff000 0x200>;
94 reg = <0xffffe800 0x200>;
101 reg = <0xfffffc00 0x200>;
105 #size-cells = <0>;
[all …]
H A Dat91sam9x5.dtsi51 reg = <0x20000000 0x10000000>;
57 #clock-cells = <0>;
58 clock-frequency = <0>;
63 #clock-cells = <0>;
64 clock-frequency = <0>;
69 #clock-cells = <0>;
76 reg = <0x00300000 0x8000>;
97 reg = <0xfffff000 0x200>;
103 reg = <0xffffe800 0x200>;
110 reg = <0xfffffc00 0x200>;
[all …]
H A Dsama5d3.dtsi45 #size-cells = <0>;
46 cpu@0 {
49 reg = <0x0>;
55 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
59 reg = <0x20000000 0x8000000>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #clock-cells = <0>;
72 clock-frequency = <0>;
77 #clock-cells = <0>;
[all …]
H A Dsama5d4.dtsi82 #size-cells = <0>;
84 cpu@0 {
87 reg = <0>;
93 reg = <0x20000000 0x20000000>;
99 #clock-cells = <0>;
100 clock-frequency = <0>;
105 #clock-cells = <0>;
106 clock-frequency = <0>;
111 #clock-cells = <0>;
118 reg = <0x00210000 0x10000>;
[all …]
/openbmc/qemu/hw/arm/
H A Dnpcm7xx.c36 #define NPCM7XX_MMIO_BA (0x80000000)
37 #define NPCM7XX_MMIO_SZ (0x7ffd0000)
40 #define NPCM7XX_OTP1_BA (0xf0189000)
41 #define NPCM7XX_OTP2_BA (0xf018a000)
44 #define NPCM7XX_L2C_BA (0xf03fc000)
45 #define NPCM7XX_CPUP_BA (0xf03fe000)
46 #define NPCM7XX_GCR_BA (0xf0800000)
47 #define NPCM7XX_CLK_BA (0xf0801000)
48 #define NPCM7XX_MC_BA (0xf0824000)
49 #define NPCM7XX_RNG_BA (0xf000b000)
[all …]
/openbmc/linux/arch/arm/
H A DKconfig.debug149 0x80000000 | 0xf0000000 | UART0
150 0x80004000 | 0xf0004000 | UART1
151 0x80008000 | 0xf0008000 | UART2
152 0x8000c000 | 0xf000c000 | UART3
153 0x80010000 | 0xf0010000 | UART4
154 0x80014000 | 0xf0014000 | UART5
155 0x80018000 | 0xf0018000 | UART6
156 0x8001c000 | 0xf001c000 | UART7
157 0x80020000 | 0xf0020000 | UART8
158 0x80024000 | 0xf0024000 | UART9
[all …]