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/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dx-powers,ac100.yaml24 const: 0
91 #size-cells = <0>;
95 reg = <0xe89>;
100 interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */
101 #clock-cells = <0>;
108 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
/openbmc/u-boot/arch/arm/dts/
H A Dsun8i-a83t-allwinner-h8homlet-v2.dts50 model = "Allwinner A83T H8Homlet Proto Dev Board v2.0";
68 gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
78 gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
88 pinctrl-0 = <&mmc0_pins>;
97 pinctrl-0 = <&mmc2_8bit_emmc_pins>;
115 reg = <0x3a3>;
117 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
124 reg = <0xe89>;
129 interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */
130 #clock-cells = <0>;
[all …]
H A Dsun8i-a83t-bananapi-m3.dts84 gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>;
106 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
123 pinctrl-0 = <&emac_rgmii_pins>;
151 pinctrl-0 = <&mmc0_pins>;
170 interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>;
177 pinctrl-0 = <&mmc2_8bit_emmc_pins>;
191 reg = <0x3a3>;
193 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
202 reg = <0xe89>;
207 interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */
[all …]
H A Dsun9i-a80-cx-a99.dts93 reset-gpios = <&r_pio 1 0 GPIO_ACTIVE_LOW>; /* PM0 */
103 gpio = <&r_pio 0 7 /* no flag support */ 0>; /* PL7 */
113 gpio = <&r_pio 0 8 /* no flag support */ 0>; /* PL8 */
131 enable-gpio = <&r_pio 0 2 /* flags n/a */ 0>; /* PL2 */
133 gpios = <&r_pio 0 3 /* no flag support */ 0>, /* PL3 */
134 <&r_pio 0 4 /* no flag support */ 0>, /* PL4 */
135 <&r_pio 0 5 /* no flag support */ 0>; /* PL5 */
137 gpios-states = <1 0 0>;
138 states = < 750000 0x7
139 800000 0x3
[all …]
H A Dsun8i-a83t-tbs-a711.dts65 pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
68 brightness-levels = <0 1 2 4 8 16 32 64 128 255>;
113 gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>;
120 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
162 pinctrl-0 = <&mmc0_pins>;
180 interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 WL_WAKE_UP */
186 pinctrl-0 = <&mmc2_8bit_emmc_pins>;
198 pinctrl-0 = <&pwm_pin>;
207 reg = <0x3a3>;
209 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
[all …]
H A Dsun8i-a83t-cubietruck-plus.dts115 gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
132 #sound-dai-cells = <0>;
144 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
160 pinctrl-0 = <&emac_rgmii_pins>;
176 pinctrl-0 = <&mmc0_pins>;
194 pinctrl-0 = <&mmc2_8bit_emmc_pins>;
207 reg = <0x3a3>;
209 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
217 reg = <0xe89>;
222 interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */
[all …]
H A Dsun9i-a80-cubieboard4.dts93 #size-cells = <0>;
97 #size-cells = <0>;
99 port@0 {
101 #size-cells = <0>;
102 reg = <0>;
104 vga_dac_in: endpoint@0 {
105 reg = <0>;
112 #size-cells = <0>;
115 vga_dac_out: endpoint@0 {
116 reg = <0>;
[all …]
H A Dsun9i-a80-optimus.dts79 gpios = <&pio 7 0 GPIO_ACTIVE_HIGH>;
106 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
125 pinctrl-0 = <&mmc0_pins>;
134 pinctrl-0 = <&mmc1_pins>;
149 pinctrl-0 = <&mmc2_8bit_pins>;
172 clocks = <&ac100_rtc 0>;
183 reg = <0x3a3>;
185 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
313 reg = <0x745>;
315 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
[all …]
/openbmc/linux/arch/arm/boot/dts/allwinner/
H A Dsun8i-a83t-allwinner-h8homlet-v2.dts50 model = "Allwinner A83T H8Homlet Proto Dev Board v2.0";
68 gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
78 gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
96 pinctrl-0 = <&mmc0_pins>;
105 pinctrl-0 = <&mmc2_8bit_emmc_pins>;
123 reg = <0x3a3>;
132 reg = <0xe89>;
137 interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */
138 #clock-cells = <0>;
268 pinctrl-0 = <&uart0_pb_pins>;
H A Dsun8i-a83t-bananapi-m3.dts77 led-0 {
84 gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>;
106 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
146 pinctrl-0 = <&emac_rgmii_pins>;
174 pinctrl-0 = <&mmc0_pins>;
193 interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>;
200 pinctrl-0 = <&mmc2_8bit_emmc_pins>;
219 reg = <0x3a3>;
230 reg = <0xe89>;
235 interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */
[all …]
H A Dsun9i-a80-cubieboard4.dts66 led-0 {
95 #size-cells = <0>;
97 port@0 {
98 reg = <0>;
120 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
130 pinctrl-0 = <&gmac_rgmii_pins>;
139 pinctrl-0 = <&i2c3_pins>;
151 pinctrl-0 = <&mmc0_pins>;
160 pinctrl-0 = <&mmc1_pins>;
175 pinctrl-0 = <&mmc2_8bit_pins>;
[all …]
H A Dsun8i-a83t-cubietruck-plus.dts77 led-0 {
126 gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
143 #sound-dai-cells = <0>;
155 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
183 pinctrl-0 = <&emac_rgmii_pins>;
209 pinctrl-0 = <&mmc0_pins>;
227 pinctrl-0 = <&mmc2_8bit_emmc_pins>;
240 reg = <0x3a3>;
250 reg = <0xe89>;
255 interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */
[all …]
H A Dsun8i-a83t-tbs-a711.dts66 pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
69 brightness-levels = <0 1 2 4 8 16 32 64 128 255>;
121 gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>;
128 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
173 reg = <0x38>;
175 interrupts = <0 7 IRQ_TYPE_EDGE_FALLING>; /* PL7 */
189 reg = <0x18>;
198 pinctrl-0 = <&mmc0_pins>;
218 interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 WL_WAKE_UP */
224 pinctrl-0 = <&mmc2_8bit_emmc_pins>;
[all …]
H A Dsun9i-a80-optimus.dts79 gpios = <&pio 7 0 GPIO_ACTIVE_HIGH>;
106 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
125 pinctrl-0 = <&gmac_rgmii_pins>;
140 pinctrl-0 = <&mmc0_pins>;
149 pinctrl-0 = <&mmc1_pins>;
164 pinctrl-0 = <&mmc2_8bit_pins>;
187 clocks = <&ac100_rtc 0>;
214 reg = <0x3a3>;
216 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
345 reg = <0x745>;
[all …]
/openbmc/linux/drivers/bus/
H A Dsunxi-rsb.c53 #define RSB_CTRL 0x0 /* Global control */
54 #define RSB_CCR 0x4 /* Clock control */
55 #define RSB_INTE 0x8 /* Interrupt controls */
56 #define RSB_INTS 0xc /* Interrupt status */
57 #define RSB_ADDR 0x10 /* Address to send with read/write command */
58 #define RSB_DATA 0x1c /* Data to read/write */
59 #define RSB_LCR 0x24 /* Line control */
60 #define RSB_DMCR 0x28 /* Device mode (init) control */
61 #define RSB_CMD 0x2c /* RSB Command */
62 #define RSB_DAR 0x30 /* Device address / runtime address */
[all …]
/openbmc/linux/include/linux/mfd/madera/
H A Dregisters.h14 #define MADERA_SOFTWARE_RESET 0x00
15 #define MADERA_HARDWARE_REVISION 0x01
16 #define MADERA_CTRL_IF_CFG_1 0x08
17 #define MADERA_CTRL_IF_CFG_2 0x09
18 #define MADERA_CTRL_IF_CFG_3 0x0A
19 #define MADERA_WRITE_SEQUENCER_CTRL_0 0x16
20 #define MADERA_WRITE_SEQUENCER_CTRL_1 0x17
21 #define MADERA_WRITE_SEQUENCER_CTRL_2 0x18
22 #define MADERA_TONE_GENERATOR_1 0x20
23 #define MADERA_TONE_GENERATOR_2 0x21
[all …]
/openbmc/linux/drivers/mfd/
H A Dcs47l15-tables.c19 { 0x8C, 0x5555 },
20 { 0x8C, 0xAAAA },
21 { 0x314, 0x0080 },
22 { 0x4A8, 0x6023 },
23 { 0x4A9, 0x6023 },
24 { 0x4D4, 0x0008 },
25 { 0x4CF, 0x0F00 },
26 { 0x4D7, 0x1B2B },
27 { 0x8C, 0xCCCC },
28 { 0x8C, 0x3333 },
[all …]
H A Dcs47l35-tables.c18 { 0x460, 0x0c40 },
19 { 0x461, 0xcd1a },
20 { 0x462, 0x0c40 },
21 { 0x463, 0xb53b },
22 { 0x464, 0x0c40 },
23 { 0x465, 0x7503 },
24 { 0x466, 0x0c40 },
25 { 0x467, 0x4a41 },
26 { 0x468, 0x0041 },
27 { 0x469, 0x3491 },
[all …]
H A Dcs47l92-tables.c21 { 0x3A2, 0x2C29 },
22 { 0x3A3, 0x0E00 },
23 { 0x281, 0x0000 },
24 { 0x282, 0x0000 },
25 { 0x4EA, 0x0100 },
26 { 0x22B, 0x0000 },
27 { 0x4A0, 0x0080 },
28 { 0x4A1, 0x0000 },
29 { 0x4A2, 0x0000 },
30 { 0x180B, 0x033F },
[all …]
H A Dcs47l90-tables.c18 { 0x8A, 0x5555 },
19 { 0x8A, 0xAAAA },
20 { 0x4CF, 0x0700 },
21 { 0x171, 0x0003 },
22 { 0x101, 0x0444 },
23 { 0x159, 0x0002 },
24 { 0x120, 0x0444 },
25 { 0x1D1, 0x0004 },
26 { 0x1E0, 0xC084 },
27 { 0x159, 0x0000 },
[all …]
H A Dcs47l85-tables.c18 { 0x80, 0x0003 },
19 { 0x213, 0x03E4 },
20 { 0x177, 0x0281 },
21 { 0x197, 0x0281 },
22 { 0x1B7, 0x0281 },
23 { 0x4B1, 0x010A },
24 { 0x4CF, 0x0933 },
25 { 0x36C, 0x011B },
26 { 0x4B8, 0x1120 },
27 { 0x4A0, 0x3280 },
[all …]
/openbmc/linux/include/linux/mfd/arizona/
H A Dregisters.h16 #define ARIZONA_SOFTWARE_RESET 0x00
17 #define ARIZONA_DEVICE_REVISION 0x01
18 #define ARIZONA_CTRL_IF_SPI_CFG_1 0x08
19 #define ARIZONA_CTRL_IF_I2C1_CFG_1 0x09
20 #define ARIZONA_CTRL_IF_I2C2_CFG_1 0x0A
21 #define ARIZONA_CTRL_IF_I2C1_CFG_2 0x0B
22 #define ARIZONA_CTRL_IF_I2C2_CFG_2 0x0C
23 #define ARIZONA_CTRL_IF_STATUS_1 0x0D
24 #define ARIZONA_WRITE_SEQUENCER_CTRL_0 0x16
25 #define ARIZONA_WRITE_SEQUENCER_CTRL_1 0x17
[all …]