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12

/openbmc/u-boot/include/configs/
H A Darmadillo-800eva.h22 #define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
27 #define CONFIG_SYS_INIT_SP_ADDR 0xE8083000
28 #define STACK_AREA_SIZE 0xC000
33 #define ARMADILLO_800EVA_SDRAM_BASE 0x40000000
41 #define SCIF0_BASE 0xe6c40000
42 #define SCIF1_BASE 0xe6c50000
43 #define SCIF2_BASE 0xe6c60000
44 #define SCIF4_BASE 0xe6c80000
58 #define CONFIG_SYS_MONITOR_BASE 0x00000000
65 #define CONFIG_SYS_FLASH_BASE 0x00000000
[all …]
/openbmc/u-boot/arch/arm/mach-rmobile/include/mach/
H A Drcar-gen3-base.h14 #define RWDT_BASE 0xE6020000
15 #define SWDT_BASE 0xE6030000
16 #define LBSC_BASE 0xEE220200
17 #define TMU_BASE 0xE61E0000
18 #define GPIO5_BASE 0xE6055000
21 #define SCIF0_BASE 0xE6E60000
22 #define SCIF1_BASE 0xE6E68000
23 #define SCIF2_BASE 0xE6E88000
24 #define SCIF3_BASE 0xE6C50000
25 #define SCIF4_BASE 0xE6C40000
[all …]
H A Dsh73a0.h5 #define GLOBAL_TIMER_BASE_ADDR (0xF0000200)
6 #define MERAM_BASE (0xE5580000)
9 #define GIC_BASE (0xF0000100)
13 #define LIFEC_SEC_SRC (0xE6110008)
16 #define RWDT_BASE (0xE6020000)
19 #define HPB_BASE (0xE6001010)
22 #define HPBSCR_BASE (0xE6001600)
25 #define SBSC1_BASE (0xFE400000)
26 #define SDMRA1A (SBSC1_BASE + 0x100000)
27 #define SDMRA2A (SBSC1_BASE + 0x1C0000)
[all …]
H A Drcar-base.h14 #define RWDT_BASE 0xE6020000
15 #define SWDT_BASE 0xE6030000
16 #define LBSC_BASE 0xFEC00200
17 #define DBSC3_0_BASE 0xE6790000
18 #define DBSC3_1_BASE 0xE67A0000
19 #define TMU_BASE 0xE61E0000
20 #define GPIO5_BASE 0xE6055000
21 #define SH_QSPI_BASE 0xE6B10000
24 #define SCIF0_BASE 0xE6E60000
25 #define SCIF1_BASE 0xE6E68000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Drenesas,scifa.yaml104 reg = <0xe6c40000 64>;
110 dmas = <&dmac0 0x21>, <&dmac0 0x22>, <&dmac1 0x21>, <&dmac1 0x22>;
/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dr8a7740.dtsi20 #size-cells = <0>;
21 cpu@0 {
24 reg = <0x0>;
35 reg = <0xc2800000 0x1000>,
36 <0xc2000000 0x1000>;
41 reg = <0xf0100000 0x1000>;
53 reg = <0xfe400000 0x400>;
68 reg = <0xfe910000 0x3000>;
77 reg = <0xfe914000 0x3000>;
87 reg = <0xe6138000 0x170>;
[all …]
H A Dr8a73a4.dtsi21 #size-cells = <0>;
23 cpu0: cpu@0 {
26 reg = <0>;
33 L2_CA15: cache-controller-0 {
65 reg = <0 0xe6790000 0 0x10000>;
71 reg = <0 0xe67a0000 0 0x10000>;
77 #size-cells = <0>;
79 reg = <0 0xe60b0000 0 0x428>;
89 reg = <0 0xe6130000 0 0x1004>;
108 reg = <0 0xe61c0000 0 0x200>;
[all …]
H A Dsh73a0.dtsi20 #size-cells = <0>;
22 cpu0: cpu@0 {
25 reg = <0>;
44 reg = <0xf0000200 0x100>;
51 reg = <0xf0000600 0x20>;
60 reg = <0xf0001000 0x1000>,
61 <0xf0000100 0x100>;
66 reg = <0xf0100000 0x1000>;
78 reg = <0xfb400000 0x400>;
87 reg = <0xfe400000 0x400>;
[all …]
H A Dr8a7794.dtsi34 * The external audio clocks are configured as 0 Hz fixed frequency
40 #clock-cells = <0>;
41 clock-frequency = <0>;
45 #clock-cells = <0>;
46 clock-frequency = <0>;
50 #clock-cells = <0>;
51 clock-frequency = <0>;
57 #clock-cells = <0>;
59 clock-frequency = <0>;
64 #size-cells = <0>;
[all …]
H A Dr8a7793.dtsi32 * The external audio clocks are configured as 0 Hz fixed frequency
38 #clock-cells = <0>;
39 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
48 #clock-cells = <0>;
49 clock-frequency = <0>;
55 #clock-cells = <0>;
57 clock-frequency = <0>;
62 #size-cells = <0>;
[all …]
H A Dr8a7745.dtsi36 * The external audio clocks are configured as 0 Hz fixed
42 #clock-cells = <0>;
43 clock-frequency = <0>;
47 #clock-cells = <0>;
48 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
59 #clock-cells = <0>;
61 clock-frequency = <0>;
66 #size-cells = <0>;
[all …]
H A Dr8a7742.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
35 #clock-cells = <0>;
36 clock-frequency = <0>;
42 #clock-cells = <0>;
44 clock-frequency = <0>;
49 #size-cells = <0>;
[all …]
H A Dr8a7791.dtsi40 * The external audio clocks are configured as 0 Hz fixed frequency
46 #clock-cells = <0>;
47 clock-frequency = <0>;
51 #clock-cells = <0>;
52 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
63 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #size-cells = <0>;
[all …]
H A Dr8a7743.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
46 clock-frequency = <0>;
51 #size-cells = <0>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dr8a77970.dtsi29 #size-cells = <0>;
31 a53_0: cpu@0 {
34 reg = <0>;
61 #clock-cells = <0>;
63 clock-frequency = <0>;
68 #clock-cells = <0>;
70 clock-frequency = <0>;
88 #clock-cells = <0>;
89 clock-frequency = <0>;
95 #clock-cells = <0>;
[all …]
H A Dr8a77995.dtsi21 #clock-cells = <0>;
22 clock-frequency = <0>;
27 #size-cells = <0>;
29 a53_0: cpu@0 {
31 reg = <0x0>;
48 #clock-cells = <0>;
50 clock-frequency = <0>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
79 reg = <0 0xe6020000 0 0x0c>;
[all …]
H A Dr8a7794.dtsi34 * The external audio clocks are configured as 0 Hz fixed frequency
40 #clock-cells = <0>;
41 clock-frequency = <0>;
45 #clock-cells = <0>;
46 clock-frequency = <0>;
50 #clock-cells = <0>;
51 clock-frequency = <0>;
57 #clock-cells = <0>;
59 clock-frequency = <0>;
64 #size-cells = <0>;
[all …]
H A Dr8a7793.dtsi32 * The external audio clocks are configured as 0 Hz fixed frequency
38 #clock-cells = <0>;
39 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
48 #clock-cells = <0>;
49 clock-frequency = <0>;
55 #clock-cells = <0>;
57 clock-frequency = <0>;
62 #size-cells = <0>;
[all …]
H A Dr8a7791.dtsi40 * The external audio clocks are configured as 0 Hz fixed frequency
46 #clock-cells = <0>;
47 clock-frequency = <0>;
51 #clock-cells = <0>;
52 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
63 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #size-cells = <0>;
[all …]
H A Dr8a77965.dtsi34 * The external audio clocks are configured as 0 Hz fixed frequency
40 #clock-cells = <0>;
41 clock-frequency = <0>;
46 #clock-cells = <0>;
47 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
59 #clock-cells = <0>;
60 clock-frequency = <0>;
65 #size-cells = <0>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/renesas/
H A Dr8a77970.dtsi22 #clock-cells = <0>;
23 clock-frequency = <0>;
28 #size-cells = <0>;
30 a53_0: cpu@0 {
33 reg = <0>;
60 #clock-cells = <0>;
62 clock-frequency = <0>;
67 #clock-cells = <0>;
69 clock-frequency = <0>;
87 #clock-cells = <0>;
[all …]
H A Dr8a779f0.dtsi17 cluster01_opp: opp-table-0 {
73 #size-cells = <0>;
113 a55_0: cpu@0 {
115 reg = <0>;
127 reg = <0x100>;
139 reg = <0x10000>;
151 reg = <0x10100>;
163 reg = <0x20000>;
175 reg = <0x20100>;
187 reg = <0x30000>;
[all …]
H A Dr8a77980.dtsi22 #clock-cells = <0>;
23 clock-frequency = <0>;
28 #size-cells = <0>;
30 a53_0: cpu@0 {
33 reg = <0>;
80 #clock-cells = <0>;
82 clock-frequency = <0>;
87 #clock-cells = <0>;
89 clock-frequency = <0>;
95 #clock-cells = <0>;
[all …]
H A Dr8a77995.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
38 #clock-cells = <0>;
39 clock-frequency = <0>;
44 #size-cells = <0>;
46 a53_0: cpu@0 {
48 reg = <0x0>;
[all …]
/openbmc/linux/arch/arm/
H A DKconfig.debug149 0x80000000 | 0xf0000000 | UART0
150 0x80004000 | 0xf0004000 | UART1
151 0x80008000 | 0xf0008000 | UART2
152 0x8000c000 | 0xf000c000 | UART3
153 0x80010000 | 0xf0010000 | UART4
154 0x80014000 | 0xf0014000 | UART5
155 0x80018000 | 0xf0018000 | UART6
156 0x8001c000 | 0xf001c000 | UART7
157 0x80020000 | 0xf0020000 | UART8
158 0x80024000 | 0xf0024000 | UART9
[all …]

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