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12

/openbmc/u-boot/board/samsung/smdkc100/
H A Dlowlevel_init.S23 mov r5, #0
28 ldr r0, =S5PC100_WATCHDOG_BASE @0xEA200000
29 orr r0, r0, #0x0
34 ldr r1, =0x9
38 ldr r0, =S5PC100_VIC0_BASE @0xE4000000
39 ldr r1, =S5PC100_VIC1_BASE @0xE4000000
40 ldr r2, =S5PC100_VIC2_BASE @0xE4000000
43 mvn r3, #0x0
44 str r3, [r0, #0x14] @INTENCLEAR
45 str r3, [r1, #0x14] @INTENCLEAR
[all …]
/openbmc/linux/arch/mips/jazz/
H A Dirq.c62 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0); in init_r4030_ints()
69 * driver compatibility reasons interrupts 0 - 15 to be the i8259
79 /* Map 0xe0000000 -> 0x0:800005C0, 0xe0010000 -> 0x1:30000580 */ in arch_init_irq()
80 add_wired_entry(0x02000017, 0x03c00017, 0xe0000000, PM_64K); in arch_init_irq()
81 /* Map 0xe2000000 -> 0x0:900005C0, 0xe3010000 -> 0x0:910005C0 */ in arch_init_irq()
82 add_wired_entry(0x02400017, 0x02440017, 0xe2000000, PM_16M); in arch_init_irq()
83 /* Map 0xe4000000 -> 0x0:600005C0, 0xe4100000 -> 400005C0 */ in arch_init_irq()
84 add_wired_entry(0x01800017, 0x01000017, 0xe4000000, PM_4M); in arch_init_irq()
106 if (likely(irq > 0)) in plat_irq_dispatch()
H A Dsetup.c33 .start = 0x00,
34 .end = 0x1f,
38 .start = 0x40,
39 .end = 0x5f,
43 .start = 0x80,
44 .end = 0x8f,
48 .start = 0xc0,
49 .end = 0xdf,
59 /* Map 0xe0000000 -> 0x0:800005C0, 0xe0010000 -> 0x1:30000580 */ in plat_mem_setup()
60 add_wired_entry(0x02000017, 0x03c00017, 0xe0000000, PM_64K); in plat_mem_setup()
[all …]
/openbmc/linux/drivers/video/fbdev/
H A Dg364fb.c34 #define G364_MEM_BASE 0xe4400000
35 #define G364_PORT_BASE 0xe4000000
36 #define ID_REG 0xe4000000 /* Read only */
37 #define BOOT_REG 0xe4080000
38 #define TIMING_REG 0xe4080108 /* to 0x080170 - DON'T TOUCH! */
39 #define DISPLAY_REG 0xe4080118
40 #define VDISPLAY_REG 0xe4080150
41 #define MASK_REG 0xe4080200
42 #define CTLA_REG 0xe4080300
43 #define CURS_TOGGLE 0x800000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Darm,pl353-nand-r2p1.yaml37 reg = <0xe000e000 0x0001000>;
40 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
41 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
42 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
46 nfc0: nand-controller@0,0 {
48 reg = <0 0 0x1000000>;
50 #size-cells = <0>;
/openbmc/u-boot/arch/arm/mach-s5pc1xx/include/mach/
H A Dcpu.h12 #define S5PC1XX_ADDR_BASE 0xE0000000
15 #define S5PC100_PRO_ID 0xE0000000
16 #define S5PC100_CLOCK_BASE 0xE0100000
17 #define S5PC100_GPIO_BASE 0xE0300000
18 #define S5PC100_VIC0_BASE 0xE4000000
19 #define S5PC100_VIC1_BASE 0xE4100000
20 #define S5PC100_VIC2_BASE 0xE4200000
21 #define S5PC100_DMC_BASE 0xE6000000
22 #define S5PC100_SROMC_BASE 0xE7000000
23 #define S5PC100_ONENAND_BASE 0xE7100000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Darm,pl35x-smc.yaml33 pattern: "^memory-controller@[0-9a-f]+$"
69 - description: Combined or Memory interface 0 IRQ
73 "@[0-7],[a-f0-9]+$":
91 minimum: 0
141 reg = <0xe000e000 0x0001000>;
144 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
145 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
146 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
150 nfc0: nand-controller@0,0 {
152 reg = <0 0 0x1000000>;
[all …]
/openbmc/u-boot/arch/riscv/dts/
H A Dae350_64.dts21 #size-cells = <0>;
23 CPU0: cpu@0 {
25 reg = <0>;
31 d-cache-size = <0x8000>;
41 memory@0 {
43 reg = <0x0 0x00000000 0x0 0x40000000>;
57 reg = <0x0 0xe4000000 0x0 0x2000000>;
67 reg = <0x0 0xe6400000 0x0 0x400000>;
75 reg = <0x0 0xe6000000 0x0 0x100000>;
80 #clock-cells = <0>;
[all …]
H A Dae350_32.dts21 #size-cells = <0>;
23 CPU0: cpu@0 {
25 reg = <0>;
31 d-cache-size = <0x8000>;
41 memory@0 {
43 reg = <0x00000000 0x40000000>;
57 reg = <0xe4000000 0x2000000>;
67 reg = <0xe6400000 0x400000>;
75 reg = <0xe6000000 0x100000>;
80 #clock-cells = <0>;
[all …]
/openbmc/linux/tools/testing/selftests/powerpc/include/
H A Dinstructions.h10 (0x7c00060c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10))
16 asm volatile(str(COPY(0, %0, 0))";" in copy()
25 asm volatile(str(COPY(0, %0, 1))";" in copy_first()
34 (0x7c00070c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10) | (RC) << (31-31))
42 asm volatile(str(PASTE(0, %1, 0, 0))";" in paste()
43 "mfcr %0;" in paste()
55 asm volatile(str(PASTE(0, %1, 1, 1))";" in paste_last()
56 "mfcr %0;" in paste_last()
64 #define PPC_INST_COPY __COPY(0, 0, 0)
65 #define PPC_INST_COPY_FIRST __COPY(0, 0, 1)
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dspear13xx.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
36 reg = < 0xec801000 0x1000 >,
37 < 0xec800100 0x0100 >;
42 interrupts = <0 6 0x04>,
43 <0 7 0x04>;
48 reg = <0xed000000 0x1000>;
56 reg = <0 0x40000000>;
79 ranges = <0x50000000 0x50000000 0x10000000
[all …]
/openbmc/linux/drivers/usb/misc/sisusbvga/
H A Dsisusb.h45 #define SISUSB_VERSION 0
46 #define SISUSB_REVISION 0
59 #define SISUSB_IBUF_SIZE 0x01000
60 #define SISUSB_OBUF_SIZE 0x10000 /* fixed */
86 } while(0)
107 int isopen; /* !=0 if open */
108 int present; /* !=0 if device is present on the bus */
109 int ready; /* !=0 if device is ready for userland */
140 #define SISUSB_EP_GFX_IN 0x0e /* gfx std packet out(0e)/in(8e) */
141 #define SISUSB_EP_GFX_OUT 0x0e
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Drk3399-sdram-ddr3-1866.dtsi8 0x1
9 0xa
10 0x3
11 0x2
12 0x1
13 0x0
14 0xf
15 0xf
17 0x80181219
18 0x17050a03
[all …]
H A Drk3399-sdram-ddr3-1333.dtsi8 0x1
9 0xa
10 0x3
11 0x2
12 0x1
13 0x0
14 0xf
15 0xf
17 0x80120e12
18 0x11030802
[all …]
H A Drk3399-sdram-ddr3-1600.dtsi8 0x1
9 0xa
10 0x3
11 0x2
12 0x1
13 0x0
14 0xf
15 0xf
17 0x80151015
18 0x14040902
[all …]
H A Drk3399-sdram-lpddr3-4GB-1600.dtsi8 0x2
9 0xa
10 0x3
11 0x2
12 0x2
13 0x0
14 0xf
15 0xf
17 0x1d191519
18 0x14040808
[all …]
H A Drk3399-sdram-lpddr3-2GB-1600.dtsi9 0x1
10 0xa
11 0x3
12 0x2
13 0x2
14 0x0
15 0xf
16 0xf
18 0x1d191519
19 0x14040808
[all …]
/openbmc/u-boot/board/samsung/goni/
H A Dlowlevel_init.S18 * r7 has S5PC100 GPIO base, 0xE0300000
19 * r8 has real GPIO base, 0xE0300000, 0xE0200000 at S5PC100, S5PC110 repectively
28 mov r5, #0
35 mov r1, #0x00010000
47 and r1, r1, #0x000D0000
48 cmp r1, #(0x1 << 19) @ DEEPIDLE_WAKEUP
53 addeq r0, r8, #0x280 @ S5PC100_GPIO_J4
54 addne r0, r8, #0x2C0 @ S5PC110_GPIO_J4
55 ldr r1, [r0, #0x0] @ GPIO_CON_OFFSET
56 bic r1, r1, #(0xf << 4) @ 1 * 4-bit
[all …]
/openbmc/linux/drivers/mtd/nand/raw/
H A DKconfig499 default "0"
502 DiskOnChip at every multiple of 0x2000 between 0xC8000 and 0xEE000.
508 0xE4000000.)
518 DiskOnChip at every multiple of 0x2000 between 0xC8000 and 0xEE000.
519 This option changes to make it probe between 0xFFFC8000 and
520 0xFFFEE000. Unless you are using LinuxBIOS, this is unlikely to be
/openbmc/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-7000.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
18 reg = <0>;
47 interrupts = <0 5 4>, <0 6 4>;
49 reg = <0xf8891000 0x1000>,
50 <0xf8893000 0x1000>;
69 #size-cells = <0>;
72 port@0 {
73 reg = <0>;
104 reg = <0xf8007100 0x20>;
[all …]
/openbmc/u-boot/include/configs/
H A DMPC8610HPCD.h14 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
20 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000)
26 #define CONFIG_SYS_DIAG_ADDR 0xff800000
33 #define CONFIG_SYS_SCRATCH_VA 0xc0000000
53 #define L2_INIT 0
54 #define L2_ENABLE (L2CR_L2E |0x00100000 )
57 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
60 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
61 #define CONFIG_SYS_MEMTEST_END 0x00400000
67 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
[all …]
/openbmc/qemu/target/sh4/
H A Dhelper.c32 #define MMU_OK 0
52 return !(addr & 0x80000000); in cpu_sh4_is_cached()
69 if (do_exp && cs->exception_index != 0x1e0) { in superh_cpu_do_interrupt()
83 env->in_sleep = 0; in superh_cpu_do_interrupt()
87 (env->sr >> 4) & 0xf); in superh_cpu_do_interrupt()
96 case 0x0e0: in superh_cpu_do_interrupt()
99 case 0x040: in superh_cpu_do_interrupt()
102 case 0x0a0: in superh_cpu_do_interrupt()
105 case 0x180: in superh_cpu_do_interrupt()
108 case 0x1a0: in superh_cpu_do_interrupt()
[all …]
/openbmc/linux/crypto/
H A Daes_generic.c67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]
/openbmc/linux/arch/powerpc/kernel/
H A Dmodule_64.c36 unsigned long abi_level = hdr->e_flags & 0x3; in module_elf_check_arch()
76 return 0; in local_entry_offset()
99 #define STUB_MAGIC 0x73747562 /* stub */
103 jump, actually, to reset r2 (TOC+0x8000). */
143 PPC_RAW_ADDIS(_R11, _R2, 0),
144 PPC_RAW_ADDI(_R11, _R11, 0),
167 _count_relocs = 0; in count_relocs()
168 r_info = 0; in count_relocs()
169 r_addend = 0; in count_relocs()
170 for (i = 0; i < num; i++) in count_relocs()
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dppc-opcode.h13 #define __REG_R0 0
46 #define __REGA0_0 0
80 #define _R0 0
113 #define IMM_L(i) ((uintptr_t)(i) & 0xffff)
114 #define IMM_DS(i) ((uintptr_t)(i) & 0xfffc)
115 #define IMM_DQ(i) ((uintptr_t)(i) & 0xfff0)
116 #define IMM_D0(i) (((uintptr_t)(i) >> 16) & 0x3ffff)
122 * top half to negate the effect (i.e. 0xffff + 1 = 0x(1)0000).
128 (((uintptr_t)(i) & 0x8000) >> 15))
133 #define IMM_H18(i) (((uintptr_t)(i)>>16) & 0x3ffff)
[all …]

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