/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/ |
H A D | table.c | 6 0x800, 0x80040000, 7 0x804, 0x00000003, 8 0x808, 0x0000FC00, 9 0x80C, 0x0000000A, 10 0x810, 0x10001331, 11 0x814, 0x020C3D10, 12 0x818, 0x02200385, 13 0x81C, 0x00000000, 14 0x820, 0x01000100, 15 0x824, 0x00390204, [all …]
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H A D | dm.h | 7 #define MAIN_ANT 0 10 #define AUX_ANT_CG_TRX 0 11 #define MAIN_ANT_CGCS_RX 0 15 #define DM_REG_RF_MODE_11N 0x00 16 #define DM_REG_RF_0B_11N 0x0B 17 #define DM_REG_CHNBW_11N 0x18 18 #define DM_REG_T_METER_11N 0x24 19 #define DM_REG_RF_25_11N 0x25 20 #define DM_REG_RF_26_11N 0x26 21 #define DM_REG_RF_27_11N 0x27 [all …]
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/openbmc/linux/Documentation/devicetree/bindings/net/ |
H A D | brcm,bcmgenet.yaml | 56 "^mdio@[0-9a-f]+$": 82 reg = <0xf0b60000 0xfc4c>; 83 interrupts = <0x0 0x14 0x0>, <0x0 0x15 0x0>; 90 #size-cells = <0>; 91 reg = <0xe14 0x8>; 104 fixed-link = <1 0 1000 0 0>; 109 reg = <0xf0b80000 0xfc4c>; 110 interrupts = <0x0 0x16 0x0>, <0x0 0x17 0x0>; 115 #size-cells = <0>; 116 reg = <0xe14 0x8>; [all …]
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/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/ |
H A D | table.c | 7 0x800, 0x80040000, 8 0x804, 0x00000003, 9 0x808, 0x0000fc00, 10 0x80c, 0x0000000a, 11 0x810, 0x10005388, 12 0x814, 0x020c3d10, 13 0x818, 0x02200385, 14 0x81c, 0x00000000, 15 0x820, 0x01000100, 16 0x824, 0x00390004, [all …]
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/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/ |
H A D | table.c | 7 0x024, 0x0011800f, 8 0x028, 0x00ffdb83, 9 0x800, 0x80040002, 10 0x804, 0x00000003, 11 0x808, 0x0000fc00, 12 0x80c, 0x0000000a, 13 0x810, 0x10000330, 14 0x814, 0x020c3d10, 15 0x818, 0x02200385, 16 0x81c, 0x00000000, [all …]
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/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192de/ |
H A D | table.c | 9 0x024, 0x0011800d, 10 0x028, 0x00ffdb83, 11 0x014, 0x088ba955, 12 0x010, 0x49022b03, 13 0x800, 0x80040002, 14 0x804, 0x00000003, 15 0x808, 0x0000fc00, 16 0x80c, 0x0000000a, 17 0x810, 0x80706388, 18 0x814, 0x020c3d10, [all …]
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/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192se/ |
H A D | table.c | 7 0x01c, 0x07000000, 8 0x800, 0x00040000, 9 0x804, 0x00008003, 10 0x808, 0x0000fc00, 11 0x80c, 0x0000000a, 12 0x810, 0x10005088, 13 0x814, 0x020c3d10, 14 0x818, 0x00200185, 15 0x81c, 0x00000000, 16 0x820, 0x01000000, [all …]
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/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/ |
H A D | table.c | 7 0x024, 0x0011800f, 8 0x028, 0x00ffdb83, 9 0x800, 0x80040002, 10 0x804, 0x00000003, 11 0x808, 0x0000fc00, 12 0x80c, 0x0000000a, 13 0x810, 0x10005388, 14 0x814, 0x020c3d10, 15 0x818, 0x02200385, 16 0x81c, 0x00000000, [all …]
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/openbmc/linux/drivers/staging/rtl8723bs/hal/ |
H A D | odm_reg.h | 16 #define ODM_BB_RESET 0x002 17 #define ODM_DUMMY 0x4fe 18 #define RF_T_METER_OLD 0x24 19 #define RF_T_METER_NEW 0x42 21 #define ODM_EDCA_VO_PARAM 0x500 22 #define ODM_EDCA_VI_PARAM 0x504 23 #define ODM_EDCA_BE_PARAM 0x508 24 #define ODM_EDCA_BK_PARAM 0x50C 25 #define ODM_TXPAUSE 0x522 28 #define ODM_FPGA_PHY0_PAGE8 0x800 [all …]
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H A D | odm_RegDefine11N.h | 13 #define ODM_REG_RF_MODE_11N 0x00 14 #define ODM_REG_RF_0B_11N 0x0B 15 #define ODM_REG_CHNBW_11N 0x18 16 #define ODM_REG_T_METER_11N 0x24 17 #define ODM_REG_RF_25_11N 0x25 18 #define ODM_REG_RF_26_11N 0x26 19 #define ODM_REG_RF_27_11N 0x27 20 #define ODM_REG_RF_2B_11N 0x2B 21 #define ODM_REG_RF_2C_11N 0x2C 22 #define ODM_REG_RXRF_A3_11N 0x3C [all …]
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/openbmc/linux/drivers/staging/rtl8192u/ |
H A D | r819xU_phyreg.h | 5 #define RF_DATA 0x1d4 /* FW will write RF data in the register.*/ 8 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ 9 #define rFPGA0_TxGainStage 0x80c 10 #define rFPGA0_XA_HSSIParameter1 0x820 11 #define rFPGA0_XA_HSSIParameter2 0x824 12 #define rFPGA0_XB_HSSIParameter1 0x828 13 #define rFPGA0_XB_HSSIParameter2 0x82c 14 #define rFPGA0_XC_HSSIParameter1 0x830 15 #define rFPGA0_XC_HSSIParameter2 0x834 16 #define rFPGA0_XD_HSSIParameter1 0x838 [all …]
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H A D | r819xU_firmware_img.c | 7 0x0, }; 10 0x800, 0x00000000, 11 0x804, 0x00000001, 12 0x808, 0x0000fc00, 13 0x80c, 0x0000001c, 14 0x810, 0x801010aa, 15 0x814, 0x008514d0, 16 0x818, 0x00000040, 17 0x81c, 0x00000000, 18 0x820, 0x00000004, [all …]
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H A D | r8190_rtl8256.c | 39 for (eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++) { in phy_set_rf8256_bandwidth() 50 0x0b, bMask12Bits, 0x100); /* phy para:1ba */ in phy_set_rf8256_bandwidth() 53 0x2c, bMask12Bits, 0x3d7); in phy_set_rf8256_bandwidth() 56 0x0e, bMask12Bits, 0x021); in phy_set_rf8256_bandwidth() 59 0x14, bMask12Bits, 0x5ab); in phy_set_rf8256_bandwidth() 66 …rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path_e)eRFPath, 0x0b, bMask12Bits, 0x300); /* phy para:… in phy_set_rf8256_bandwidth() 67 rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path_e)eRFPath, 0x2c, bMask12Bits, 0x3df); in phy_set_rf8256_bandwidth() 68 rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path_e)eRFPath, 0x0e, bMask12Bits, 0x0a1); in phy_set_rf8256_bandwidth() 72 rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path_e)eRFPath, 0x14, bMask12Bits, 0x59b); in phy_set_rf8256_bandwidth() 74 rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path_e)eRFPath, 0x14, bMask12Bits, 0x5ab); in phy_set_rf8256_bandwidth() [all …]
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/openbmc/linux/drivers/net/ethernet/intel/igb/ |
H A D | e1000_phy.h | 8 e1000_ms_hw_default = 0, 15 e1000_smart_speed_default = 0, 60 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ 61 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */ 62 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ 63 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ 64 #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ 65 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ 66 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 67 #define IGP01E1000_PHY_POLARITY_MASK 0x0078 [all …]
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/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/ |
H A D | dm.h | 11 #define MF_USC_LSC 0 14 #define MAIN_ANT 0 17 #define AUX_ANT_CG_TRX 0 18 #define MAIN_ANT_CGCS_RX 0 22 #define DM_REG_RF_MODE_11N 0x00 23 #define DM_REG_RF_0B_11N 0x0B 24 #define DM_REG_CHNBW_11N 0x18 25 #define DM_REG_T_METER_11N 0x24 26 #define DM_REG_RF_25_11N 0x25 27 #define DM_REG_RF_26_11N 0x26 [all …]
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/openbmc/linux/drivers/staging/rtl8192e/rtl8192e/ |
H A D | table.c | 10 0x800, 0x00000000, 11 0x804, 0x00000001, 12 0x808, 0x0000fc00, 13 0x80c, 0x0000001c, 14 0x810, 0x801010aa, 15 0x814, 0x008514d0, 16 0x818, 0x00000040, 17 0x81c, 0x00000000, 18 0x820, 0x00000004, 19 0x824, 0x00690000, [all …]
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H A D | r8190P_rtl8256.c | 24 for (eRFPath = 0; eRFPath < priv->num_total_rf_path; eRFPath++) { in rtl92e_set_bandwidth() 28 0x0b, bMask12Bits, 0x100); in rtl92e_set_bandwidth() 30 0x2c, bMask12Bits, 0x3d7); in rtl92e_set_bandwidth() 32 0x0e, bMask12Bits, 0x021); in rtl92e_set_bandwidth() 36 0x0b, bMask12Bits, 0x300); in rtl92e_set_bandwidth() 38 0x2c, bMask12Bits, 0x3ff); in rtl92e_set_bandwidth() 40 0x0e, bMask12Bits, 0x0e1); in rtl92e_set_bandwidth() 52 u32 u4RegValue = 0; in rtl92e_config_rf() 57 u32 RegOffSetToBeCheck = 0x3; in rtl92e_config_rf() 58 u32 RegValueToBeCheck = 0x7f1; in rtl92e_config_rf() [all …]
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/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723be/ |
H A D | dm.h | 7 #define MAIN_ANT 0 10 #define AUX_ANT_CG_TRX 0 11 #define MAIN_ANT_CGCS_RX 0 17 #define DM_REG_RF_MODE_11N 0x00 18 #define DM_REG_RF_0B_11N 0x0B 19 #define DM_REG_CHNBW_11N 0x18 20 #define DM_REG_T_METER_11N 0x24 21 #define DM_REG_RF_25_11N 0x25 22 #define DM_REG_RF_26_11N 0x26 23 #define DM_REG_RF_27_11N 0x27 [all …]
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/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/ |
H A D | dm.h | 7 #define MAIN_ANT 0 10 #define AUX_ANT_CG_TRX 0 11 #define MAIN_ANT_CGCS_RX 0 17 #define DM_REG_RF_MODE_11N 0x00 18 #define DM_REG_RF_0B_11N 0x0B 19 #define DM_REG_CHNBW_11N 0x18 20 #define DM_REG_T_METER_11N 0x24 21 #define DM_REG_RF_25_11N 0x25 22 #define DM_REG_RF_26_11N 0x26 23 #define DM_REG_RF_27_11N 0x27 [all …]
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/openbmc/linux/arch/mips/boot/dts/brcm/ |
H A D | bcm7420.dtsi | 9 #size-cells = <0>; 13 cpu@0 { 16 reg = <0>; 31 #address-cells = <0>; 41 #clock-cells = <0>; 47 #clock-cells = <0>; 57 ranges = <0 0x10000000 0x01000000>; 61 reg = <0x441400 0x30>, <0x441600 0x30>; 72 reg = <0x401800 0x30>; 81 reg = <0x400000 0xdc>; [all …]
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H A D | bcm7358.dtsi | 9 #size-cells = <0>; 13 cpu@0 { 16 reg = <0>; 25 #address-cells = <0>; 35 #clock-cells = <0>; 41 #clock-cells = <0>; 51 ranges = <0 0x10000000 0x01000000>; 55 reg = <0x411400 0x30>; 66 reg = <0x403000 0x30>; 75 reg = <0x400000 0xdc>; [all …]
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H A D | bcm7362.dtsi | 9 #size-cells = <0>; 13 cpu@0 { 16 reg = <0>; 31 #address-cells = <0>; 41 #clock-cells = <0>; 47 #clock-cells = <0>; 57 ranges = <0 0x10000000 0x01000000>; 61 reg = <0x411400 0x30>, <0x411600 0x30>; 72 reg = <0x403000 0x30>; 81 reg = <0x400000 0xdc>; [all …]
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H A D | bcm7360.dtsi | 9 #size-cells = <0>; 13 cpu@0 { 16 reg = <0>; 25 #address-cells = <0>; 35 #clock-cells = <0>; 41 #clock-cells = <0>; 51 ranges = <0 0x10000000 0x01000000>; 55 reg = <0x411400 0x30>; 66 reg = <0x403000 0x30>; 75 reg = <0x400000 0xdc>; [all …]
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/openbmc/u-boot/arch/powerpc/include/asm/ |
H A D | fsl_pci.h | 13 #define PEX_IP_BLK_REV_2_2 0x02080202 14 #define PEX_IP_BLK_REV_2_3 0x02080203 15 #define PEX_IP_BLK_REV_3_0 0x02080300 18 #define FSL_PCI_PBFR 0x44 20 #define FSL_PCIE_CFG_RDY 0x4b0 21 #define FSL_PCIE_V3_CFG_RDY 0x1 22 #define FSL_PROG_IF_AGENT 0x1 24 #define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */ 25 #define PCI_LTSSM_L0 0x16 /* L0 state */ 40 u32 potar; /* 0x00 - Address */ [all …]
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/openbmc/qemu/hw/net/fsl_etsec/ |
H A D | registers.h | 49 #define DMACTRL_WOP (1 << 0) 51 #define IEVENT_PERR (1 << 0) 94 #define MACCFG1_TX_EN (1 << 0) 100 #define MIIMCOM_READ (1 << 0) 103 #define RCTRL_PRSDEP_MASK (0x3) 109 #define TSEC_ID (0x000 / 4) 110 #define TSEC_ID2 (0x004 / 4) 111 #define IEVENT (0x010 / 4) 112 #define IMASK (0x014 / 4) 113 #define EDIS (0x018 / 4) [all …]
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