Searched +full:0 +full:xe1100000 (Results 1 – 3 of 3) sorted by relevance
| /openbmc/u-boot/arch/arm/include/asm/arch-spear/ |
| H A D | hardware.h | 10 #define CONFIG_SYS_USBD_BASE 0xE1100000
11 #define CONFIG_SYS_PLUG_BASE 0xE1200000
12 #define CONFIG_SYS_FIFO_BASE 0xE1000800
13 #define CONFIG_SYS_UHC0_EHCI_BASE 0xE1800000
14 #define CONFIG_SYS_UHC1_EHCI_BASE 0xE2000000
15 #define CONFIG_SYS_SMI_BASE 0xFC000000
16 #define CONFIG_SPEAR_SYSCNTLBASE 0xFCA00000
17 #define CONFIG_SPEAR_TIMERBASE 0xFC800000
18 #define CONFIG_SPEAR_MISCBASE 0xFCA80000
19 #define CONFIG_SPEAR_ETHBASE 0xE0800000
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| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | arm,gic.yaml | 67 enum: [ 0, 1, 2 ]
74 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
78 SPI interrupts are in the range [0-987]. PPI interrupts are in the
79 range [0-15].
82 bits[3:0] trigger type and level flags.
150 "^v2m@[0-9a-f]+$":
197 reg = <0xfff11000 0x1000>,
198 <0xfff10100 0x100>;
207 reg = <0x2c001000 0x1000>,
208 <0x2c002000 0x2000>,
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| /openbmc/linux/arch/arm64/boot/dts/amd/ |
| H A D | amd-seattle-soc.dtsi | 20 reg = <0x0 0xe1110000 0 0x1000>,
21 <0x0 0xe112f000 0 0x2000>,
22 <0x0 0xe1140000 0 0x2000>,
23 <0x0 0xe1160000 0 0x2000>;
24 interrupts = <1 9 0xf04>;
25 ranges = <0 0 0 0xe1100000 0 0x100000>;
29 reg = <0x0 0x00080000 0 0x1000>;
35 interrupts = <1 13 0xff04>,
36 <1 14 0xff04>,
37 <1 11 0xff04>,
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