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12

/openbmc/u-boot/doc/device-tree-bindings/spi/
H A Dspi-zynq-qspi.txt23 interrupts = <0 19 4>;
25 reg = <0xe000d000 0x1000>;
/openbmc/u-boot/board/topic/zynq/zynq-topic-miamilite/
H A Dps7_regs.txt1 0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 433 MHz (?)
2 0xf8000700 0x202
3 0xf8000704 0x202
4 0xf8000708 0x202
5 0xf800070c 0x202
6 0xf8000710 0x202
7 0xf8000714 0x202
8 0xf8000718 0x202
9 0xf800071c 0x200
10 0xf8000720 0x202
[all …]
H A Dps7_init_gpl.c10 EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
11 EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
12 EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
13 EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
14 EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
15 EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
16 EMIT_MASKPOLL(0xF800010C, 0x00000001U),
17 EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
18 EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
19 EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
[all …]
/openbmc/u-boot/board/topic/zynq/zynq-topic-miamiplus/
H A Dps7_regs.txt1 0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 (433 MHz)
2 0xf8000700 0x1202 // MIO configuration
3 0xf8000704 0x1202
4 0xf8000708 0x202
5 0xf800070c 0x202
6 0xf8000710 0x202
7 0xf8000714 0x202
8 0xf8000718 0x202
9 0xf800071c 0x200
10 0xf8000720 0x202
[all …]
H A Dps7_init_gpl.c10 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
11 EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA240U),
12 EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00030000U),
13 EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
14 EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
15 EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
16 EMIT_MASKPOLL(0XF800010C, 0x00000001U),
17 EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
18 EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
19 EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
[all …]
/openbmc/u-boot/board/topic/zynq/zynq-topic-miami/
H A Dps7_regs.txt1 0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 433 MHz (?)
2 0xf8000700 0x1210 // MIO configuration
3 0xf8000704 0x202
4 0xf8000708 0x202
5 0xf800070c 0x202
6 0xf8000710 0x202
7 0xf8000714 0x202
8 0xf8000718 0x202
9 0xf800071c 0x210
10 0xf8000720 0x202
[all …]
H A Dps7_init_gpl.c10 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
11 EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
12 EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
13 EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
14 EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
15 EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
16 EMIT_MASKPOLL(0XF800010C, 0x00000001U),
17 EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
18 EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
19 EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
[all …]
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dxlnx,zynq-qspi.yaml53 reg = <0xe000d000 0x1000>;
55 interrupts = <0 19 4>;
/openbmc/u-boot/arch/arm/dts/
H A Dzynq-cse-qspi.dtsi22 reg = <0xFFFC0000 0x40000>;
47 reg = <0xF8F01000 0x1000>,
48 <0xF8F00100 0x100>;
57 interrupts = <0 19 4>;
58 reg = <0xe000d000 0x1000>;
60 #size-cells = <0>;
62 flash0: flash@0 {
64 reg = <0x0>;
72 reg = <0x0 0x100000>;
76 reg = <0x100000 0x500000>;
[all …]
H A Dzynq-7000.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0>;
50 interrupts = <0 5 4>, <0 6 4>;
52 reg = <0xf8891000 0x1000>,
53 <0xf8893000 0x1000>;
75 reg = <0xf8007100 0x20>;
76 interrupts = <0 7 4>;
86 reg = <0xe0008000 0x1000>;
87 interrupts = <0 28 4>;
[all …]
/openbmc/u-boot/arch/arm/mach-zynq/include/mach/
H A Dhardware.h9 #define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000
10 #define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000
11 #define ZYNQ_SCU_BASEADDR 0xF8F00000
12 #define ZYNQ_QSPI_BASEADDR 0xE000D000
13 #define ZYNQ_SMC_BASEADDR 0xE000E000
14 #define ZYNQ_NAND_BASEADDR 0xE1000000
15 #define ZYNQ_DDRC_BASEADDR 0xF8006000
16 #define ZYNQ_EFUSE_BASEADDR 0xF800D000
17 #define ZYNQ_USB_BASEADDR0 0xE0002000
18 #define ZYNQ_USB_BASEADDR1 0xE0003000
[all …]
/openbmc/linux/arch/mips/include/asm/
H A Djazz.h15 * but many hardware register are accessible at 0xb9000000 in
16 * instead of 0xe0000000.
19 #define JAZZ_LOCAL_IO_SPACE 0xe0000000
24 * 0xf0000000 - Rev1
25 * 0xf0000001 - Rev2
26 * 0xf0000002 - Rev3
28 #define PICA_ASIC_REVISION 0xe0000008
43 * --------- . (0)
45 #define PICA_LED 0xe000f000
54 #define LED_DOT 0x01
[all …]
/openbmc/u-boot/board/xilinx/zynq/zynq-zc770-xm011-x16/
H A Dps7_init_gpl.c9 EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
10 EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
11 EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
12 EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
13 EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
14 EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
15 EMIT_MASKPOLL(0xF800010C, 0x00000001U),
16 EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
17 EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
18 EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
[all …]
/openbmc/u-boot/board/xilinx/zynq/zynq-zc770-xm011/
H A Dps7_init_gpl.c9 EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
10 EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
11 EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
12 EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
13 EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
14 EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
15 EMIT_MASKPOLL(0xF800010C, 0x00000001U),
16 EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
17 EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
18 EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
[all …]
/openbmc/u-boot/board/xilinx/zynq/zynq-zc770-xm013/
H A Dps7_init_gpl.c9 EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
10 EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
11 EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
12 EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
13 EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
14 EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
15 EMIT_MASKPOLL(0xF800010C, 0x00000001U),
16 EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
17 EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
18 EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
[all …]
/openbmc/u-boot/board/xilinx/zynq/zynq-zc770-xm012/
H A Dps7_init_gpl.c9 EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
10 EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
11 EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
12 EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
13 EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
14 EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
15 EMIT_MASKPOLL(0xF800010C, 0x00000001U),
16 EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
17 EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
18 EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
[all …]
/openbmc/u-boot/board/xilinx/zynq/zynq-cc108/
H A Dps7_init_gpl.c9 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
10 EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
11 EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
12 EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
13 EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
14 EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
15 EMIT_MASKPOLL(0XF800010C, 0x00000001U),
16 EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
17 EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
18 EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
[all …]
/openbmc/u-boot/board/xilinx/zynq/zynq-zc770-xm010/
H A Dps7_init_gpl.c9 EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
10 EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
11 EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
12 EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
13 EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
14 EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
15 EMIT_MASKPOLL(0xF800010C, 0x00000001U),
16 EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
17 EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
18 EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
[all …]
/openbmc/u-boot/board/xilinx/zynq/zynq-dlc20-rev1.0/
H A Dps7_init_gpl.c9 EMIT_WRITE(0xF8000008, 0x0000DF0DU),
10 EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
11 EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
12 EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
13 EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
14 EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
15 EMIT_MASKPOLL(0xF800010C, 0x00000001U),
16 EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
17 EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
18 EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
[all …]
/openbmc/u-boot/board/bitmain/antminer_s9/bitmain-antminer-s9/
H A Dps7_init_gpl.c9 EMIT_MASKWRITE(0xf8000008, 0x0000ffff, 0x0000df0d),
10 EMIT_MASKWRITE(0xf8000110, 0x003ffff0, 0x000fa220),
11 EMIT_MASKWRITE(0xf8000100, 0x0007f000, 0x00028000),
12 EMIT_MASKWRITE(0xf8000100, 0x00000010, 0x00000010),
13 EMIT_MASKWRITE(0xf8000100, 0x00000001, 0x00000001),
14 EMIT_MASKWRITE(0xf8000100, 0x00000001, 0x00000000),
15 EMIT_MASKPOLL(0xf800010c, 0x00000001),
16 EMIT_MASKWRITE(0xf8000100, 0x00000010, 0x00000000),
17 EMIT_MASKWRITE(0xf8000120, 0x1f003f30, 0x1f000200),
18 EMIT_MASKWRITE(0xf8000114, 0x003ffff0, 0x0012c220),
[all …]
/openbmc/u-boot/board/opalkelly/zynq/zynq-syzygy-hub/
H A Dps7_init_gpl.c10 EMIT_WRITE(0XF8000008, 0x0000DF0DU),
11 EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
12 EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
13 EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
14 EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
15 EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
16 EMIT_MASKPOLL(0XF800010C, 0x00000001U),
17 EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
18 EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
19 EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
[all …]
/openbmc/u-boot/board/xilinx/zynq/zynq-zybo-z7/
H A Dps7_init_gpl.c25 EMIT_WRITE(0xF8000008, 0x0000DF0DU),
26 EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
27 EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
28 EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
29 EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
30 EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
31 EMIT_MASKPOLL(0xF800010C, 0x00000001U),
32 EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
33 EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
34 EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
[all …]
/openbmc/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-7000.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
18 reg = <0>;
47 interrupts = <0 5 4>, <0 6 4>;
49 reg = <0xf8891000 0x1000>,
50 <0xf8893000 0x1000>;
69 #size-cells = <0>;
72 port@0 {
73 reg = <0>;
104 reg = <0xf8007100 0x20>;
[all …]
/openbmc/qemu/hw/arm/
H A Dxilinx_zynq.c59 #define MPCORE_PERIPHBASE 0xF8F00000
60 #define ZYNQ_BOARD_MIDR 0x413FC090
66 #define BOARD_SETUP_ADDR 0x100
68 #define SLCR_LOCK_OFFSET 0x004
69 #define SLCR_UNLOCK_OFFSET 0x008
70 #define SLCR_ARM_PLL_OFFSET 0x100
72 #define SLCR_XILINX_UNLOCK_KEY 0xdf0d
73 #define SLCR_XILINX_LOCK_KEY 0x767b
75 #define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080 /* Datasheet: UG585 (v1.12.1) */
77 #define ARMV7_IMM16(x) (extract32((x), 0, 12) | \
[all …]
/openbmc/u-boot/board/xilinx/zynq/zynq-zc702/
H A Dps7_init_gpl.c19 // .. UNLOCK_KEY = 0XDF0D
20 // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
21 // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
23 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
27 // .. .. PLL_RES = 0x2
28 // .. .. ==> 0XF8000110[7:4] = 0x00000002U
29 // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
30 // .. .. PLL_CP = 0x2
31 // .. .. ==> 0XF8000110[11:8] = 0x00000002U
32 // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
[all …]

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