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/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dmmp-dma.txt30 * For example, pxa688 icu register 0x128, bit 0~15 is PDMA channel irq,
35 reg = <0xd4000000 0x10000>;
36 interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
48 reg = <0xd4000000 0x10000>;
71 reg = <0xd42a0800 0x100>;
79 reg = <0xd42a0800 0x100>;
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dintel-gw-pcie.yaml96 reg = <0xd0e00000 0x1000>,
97 <0xd2000000 0x800000>,
98 <0xd0a41000 0x1000>;
100 linux,pci-domain = <0>;
102 bus-range = <0x00 0x08>;
104 interrupt-map-mask = <0 0 0 0x7>;
105 interrupt-map = <0 0 0 1 &ioapic1 27 1>,
106 <0 0 0 2 &ioapic1 28 1>,
107 <0 0 0 3 &ioapic1 29 1>,
108 <0 0 0 4 &ioapic1 30 1>;
[all …]
/openbmc/linux/arch/arm/mach-mmp/
H A Daddr-map.h15 #define APB_PHYS_BASE 0xd4000000
16 #define APB_VIRT_BASE IOMEM(0xfe000000)
17 #define APB_PHYS_SIZE 0x00200000
19 #define AXI_PHYS_BASE 0xd4200000
20 #define AXI_VIRT_BASE IOMEM(0xfe200000)
21 #define AXI_PHYS_SIZE 0x00200000
23 #define PGU_PHYS_BASE 0xe0000000
24 #define PGU_VIRT_BASE IOMEM(0xfe400000)
25 #define PGU_PHYS_SIZE 0x00100000
27 /* Static Memory Controller - Chip Select 0 and 1 */
[all …]
/openbmc/u-boot/include/configs/
H A D3c120_devboard.h29 #define CONFIG_SYS_RX_ETH_BUFFER 0
48 #define CONFIG_SYS_SDRAM_BASE 0xD0000000
49 #define CONFIG_SYS_SDRAM_SIZE 0x08000000
51 #define CONFIG_SYS_MONITOR_LEN 0x80000 /* Reserve 512k */
55 #define CONFIG_SYS_MALLOC_LEN 0x20000
65 #define CONFIG_ENV_SIZE 0x20000 /* 128k, 1 sector */
67 #define CONFIG_ENV_ADDR (0xe2800000 + CONFIG_SYS_MONITOR_LEN)
72 #define CONFIG_SYS_LOAD_ADDR 0xd4000000 /* Half of RAM */
78 0x10000)
/openbmc/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs-sev-kit.dts42 reg = <0x0 0x80000000 0x0 0x2000000>;
47 reg = <0x0 0xc4000000 0x0 0x4000000>;
52 reg = <0x0 0xd4000000 0x0 0x4000000>;
58 reg = <0x10 0x0 0x0 0x76000000>;
/openbmc/qemu/hw/tricore/
H A Dtricore_testboard.c45 NULL, NULL, 0, in tricore_load_kernel()
46 EM_TRICORE, 1, 0); in tricore_load_kernel()
47 if (kernel_size <= 0) { in tricore_load_kernel()
85 memory_region_add_subregion(sysmem, 0x80000000, ext_cram); in tricore_testboard_init()
86 memory_region_add_subregion(sysmem, 0xa1000000, ext_dram); in tricore_testboard_init()
87 memory_region_add_subregion(sysmem, 0xd4000000, int_cram); in tricore_testboard_init()
88 memory_region_add_subregion(sysmem, 0xd0000000, int_dram); in tricore_testboard_init()
89 memory_region_add_subregion(sysmem, 0xf0050000, pcp_data); in tricore_testboard_init()
90 memory_region_add_subregion(sysmem, 0xf0060000, pcp_text); in tricore_testboard_init()
93 memory_region_add_subregion(sysmem, 0xf0000000, &test_dev->iomem); in tricore_testboard_init()
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Dpxa910.dtsi30 marvell,tauros2-cache-features = <0x3>;
37 reg = <0xd4200000 0x00200000>;
44 reg = <0xd4282000 0x1000>;
54 reg = <0xd4000000 0x00200000>;
59 reg = <0xd4014000 0x100>;
65 reg = <0xd4016000 0x100>;
72 reg = <0xd4017000 0x1000>;
82 reg = <0xd4018000 0x1000>;
92 reg = <0xd4036000 0x1000>;
104 reg = <0xd4019000 0x1000>;
[all …]
H A Dpxa168.dtsi32 reg = <0xd4200000 0x00200000>;
39 reg = <0xd4282000 0x1000>;
49 reg = <0xd4000000 0x00200000>;
54 reg = <0xd4014000 0x100>;
62 reg = <0xd4017000 0x1000>;
72 reg = <0xd4018000 0x1000>;
82 reg = <0xd4026000 0x1000>;
94 reg = <0xd4019000 0x1000>;
106 reg = <0xd4019000 0x4>;
110 reg = <0xd4019004 0x4>;
[all …]
H A Dmmp2.dtsi33 marvell,tauros2-cache-features = <0x3>;
40 reg = <0xd4200000 0x00200000>;
45 reg = <0xd420d000 0x4000>;
58 reg = <0xd4282000 0x1000>;
67 reg = <0x150 0x4>, <0x168 0x4>;
77 reg = <0x154 0x4>, <0x16c 0x4>;
88 reg = <0x180 0x4>, <0x17c 0x4>;
98 reg = <0x158 0x4>, <0x170 0x4>;
108 reg = <0x15c 0x4>, <0x174 0x4>;
118 reg = <0x160 0x4>, <0x178 0x4>;
[all …]
H A Dmmp3.dtsi16 #size-cells = <0>;
19 cpu@0 {
23 reg = <0>;
45 reg = <0xd4200000 0x00200000>;
52 reg = <0xd4282000 0x1000>,
53 <0xd4284000 0x100>;
62 reg = <0x150 0x4>, <0x168 0x4>;
72 reg = <0x154 0x4>, <0x16c 0x4>;
82 reg = <0x1bc 0x4>, <0x1a4 0x4>;
92 reg = <0x1c0 0x4>, <0x1a8 0x4>;
[all …]
/openbmc/linux/arch/nios2/boot/dts/
H A D10m50_devboard.dts16 #size-cells = <0>;
18 cpu: cpu@0 {
21 reg = <0x00000000>;
24 altr,exception-addr = <0xc8000120>;
25 altr,fast-tlb-miss-addr = <0xc0000100>;
32 altr,reset-addr = <0xd4000000>;
46 reg = <0x08000000 0x08000000>,
47 <0x00000000 0x00000400>;
50 sopc0: sopc@0 {
60 reg = <0x18001530 0x00000008>;
[all …]
/openbmc/u-boot/arch/nios2/dts/
H A D10m50_devboard.dts18 #size-cells = <0>;
20 cpu: cpu@0 {
24 reg = <0x00000000>;
27 altr,exception-addr = <0xc8000120>;
28 altr,fast-tlb-miss-addr = <0xc0000100>;
35 altr,reset-addr = <0xd4000000>;
49 reg = <0x08000000 0x08000000>,
50 <0x00000000 0x00000400>;
53 sopc0: sopc@0 {
63 reg = <0x18001530 0x00000008>;
[all …]
/openbmc/qemu/contrib/plugins/
H A Dhowvec.c25 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
62 * 31..28 27..24 23..20 19..16 15..12 11..8 7..4 3..0
66 { " UDEF", "udef", 0xffff0000, 0x00000000, COUNT_NONE},
67 { " SVE", "sve", 0x1e000000, 0x04000000, COUNT_CLASS},
68 { "Reserved", "res", 0x1e000000, 0x00000000, COUNT_CLASS},
70 { " PCrel addr", "pcrel", 0x1f000000, 0x10000000, COUNT_CLASS},
71 { " Add/Sub (imm,tags)", "asit", 0x1f800000, 0x11800000, COUNT_CLASS},
72 { " Add/Sub (imm)", "asi", 0x1f000000, 0x11000000, COUNT_CLASS},
73 { " Logical (imm)", "logi", 0x1f800000, 0x12000000, COUNT_CLASS},
74 { " Move Wide (imm)", "movwi", 0x1f800000, 0x12800000, COUNT_CLASS},
[all …]
/openbmc/linux/arch/arm64/include/asm/
H A Dinsn.h18 AARCH64_INSN_HINT_NOP = 0x0 << 5,
19 AARCH64_INSN_HINT_YIELD = 0x1 << 5,
20 AARCH64_INSN_HINT_WFE = 0x2 << 5,
21 AARCH64_INSN_HINT_WFI = 0x3 << 5,
22 AARCH64_INSN_HINT_SEV = 0x4 << 5,
23 AARCH64_INSN_HINT_SEVL = 0x5 << 5,
25 AARCH64_INSN_HINT_XPACLRI = 0x07 << 5,
26 AARCH64_INSN_HINT_PACIA_1716 = 0x08 << 5,
27 AARCH64_INSN_HINT_PACIB_1716 = 0x0A << 5,
28 AARCH64_INSN_HINT_AUTIA_1716 = 0x0C << 5,
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx27.dtsi47 reg = <0x10040000 0x1000>;
53 #clock-cells = <0>;
59 #size-cells = <0>;
62 cpu: cpu@0 {
64 reg = <0>;
88 reg = <0x10000000 0x20000>;
93 reg = <0x10001000 0x1000>;
104 reg = <0x10002000 0x1000>;
111 reg = <0x10003000 0x1000>;
120 reg = <0x10004000 0x1000>;
[all …]
/openbmc/linux/crypto/
H A Daes_generic.c67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]
/openbmc/qemu/disas/
H A Dmicroblaze.c137 /* gen purpose regs go from 0 to 31 */
140 #define REG_PC_MASK 0x8000
141 #define REG_MSR_MASK 0x8001
142 #define REG_EAR_MASK 0x8003
143 #define REG_ESR_MASK 0x8005
144 #define REG_FSR_MASK 0x8007
145 #define REG_BTR_MASK 0x800b
146 #define REG_EDR_MASK 0x800d
147 #define REG_PVR_MASK 0xa000
149 #define REG_PID_MASK 0x9000
[all …]
H A Dhppa.c50 #define PA_PAGESIZE 0x1000
59 R_HPPA_FSEL = 0x0,
60 R_HPPA_LSSEL = 0x1,
61 R_HPPA_RSSEL = 0x2,
62 R_HPPA_LSEL = 0x3,
63 R_HPPA_RSEL = 0x4,
64 R_HPPA_LDSEL = 0x5,
65 R_HPPA_RDSEL = 0x6,
66 R_HPPA_LRSEL = 0x7,
67 R_HPPA_RRSEL = 0x8,
[all …]
H A Dmips.c82 #define OP_MASK_OP 0x3f
84 #define OP_MASK_RS 0x1f
86 #define OP_MASK_FR 0x1f
88 #define OP_MASK_FMT 0x1f
90 #define OP_MASK_BCC 0x7
92 #define OP_MASK_CODE 0x3ff
94 #define OP_MASK_CODE2 0x3ff
96 #define OP_MASK_RT 0x1f
98 #define OP_MASK_FT 0x1f
100 #define OP_MASK_CACHE 0x1f
[all …]
/openbmc/linux/arch/mips/kernel/
H A Dtraps.c185 i = 0; in show_stacktrace()
187 if (i && ((i % (64 / field)) == 0)) { in show_stacktrace()
201 pr_cont(" %0*lx", field, stackdata); in show_stacktrace()
215 regs.regs[31] = 0; in show_stack()
216 regs.cp0_epc = 0; in show_stack()
220 regs.regs[31] = 0; in show_stack()
275 for (i = 0; i < 32; ) { in __show_regs()
276 if ((i % 4) == 0) in __show_regs()
278 if (i == 0) in __show_regs()
279 pr_cont(" %0*lx", field, 0UL); in __show_regs()
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_hsi.h17 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
23 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
24 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
25 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
31 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
32 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0
33 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
42 #define PIN_CFG_NA 0x00000000
43 #define PIN_CFG_GPIO0_P0 0x00000001
44 #define PIN_CFG_GPIO1_P0 0x00000002
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_enum.h28 NUMBER_UNORM = 0x0,
29 NUMBER_SNORM = 0x1,
30 NUMBER_USCALED = 0x2,
31 NUMBER_SSCALED = 0x3,
32 NUMBER_UINT = 0x4,
33 NUMBER_SINT = 0x5,
34 NUMBER_SRGB = 0x6,
35 NUMBER_FLOAT = 0x7,
38 SWAP_STD = 0x0,
39 SWAP_ALT = 0x1,
[all …]
H A Dgfx_8_1_enum.h28 NUMBER_UNORM = 0x0,
29 NUMBER_SNORM = 0x1,
30 NUMBER_USCALED = 0x2,
31 NUMBER_SSCALED = 0x3,
32 NUMBER_UINT = 0x4,
33 NUMBER_SINT = 0x5,
34 NUMBER_SRGB = 0x6,
35 NUMBER_FLOAT = 0x7,
38 SWAP_STD = 0x0,
39 SWAP_ALT = 0x1,
[all …]
/openbmc/linux/drivers/accel/habanalabs/gaudi2/
H A Dgaudi2.c54 #define GAUDI2_TPC_FULL_MASK 0x1FFFFFF
55 #define GAUDI2_HIF_HMMU_FULL_MASK 0xFFFF
56 #define GAUDI2_DECODER_FULL_MASK 0x3FF
58 #define GAUDI2_NA_EVENT_CAUSE 0xFF
83 #define GAUDI2_ARB_WDT_TIMEOUT (0x1000000)
105 #define PCIE_DEC_EN_MASK 0x300
106 #define DEC_WORK_STATE_IDLE 0
115 #define GAUDI2_HBM_MMU_SCRM_MOD_SHIFT 0
120 #define MMU_RANGE_INV_EN_SHIFT 0
127 #define GAUDI2_PMMU_SPI_SEI_ENABLE_MASK GENMASK(GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE - 2, 0)
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/
H A Dvega10_enum.h51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
184 NO_FORCE_REQUEST = 0x00000000,
185 FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
186 FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
187 FORCE_SHUT_DOWN_REQUEST = 0x00000003,
195 NO_FORCE_REQ = 0x00000000,
196 FORCE_LIGHT_SLEEP_REQ = 0x00000001,
204 ENABLE_MEM_PWR_CTRL = 0x00000000,
205 DISABLE_MEM_PWR_CTRL = 0x00000001,
213 DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000,
[all …]