Searched +full:0 +full:xd0100000 (Results 1 – 13 of 13) sorted by relevance
10 #define CONFIG_SYS_USBD_BASE 0xE110000011 #define CONFIG_SYS_PLUG_BASE 0xE120000012 #define CONFIG_SYS_FIFO_BASE 0xE100080013 #define CONFIG_SYS_UHC0_EHCI_BASE 0xE180000014 #define CONFIG_SYS_UHC1_EHCI_BASE 0xE200000015 #define CONFIG_SYS_SMI_BASE 0xFC00000016 #define CONFIG_SPEAR_SYSCNTLBASE 0xFCA0000017 #define CONFIG_SPEAR_TIMERBASE 0xFC80000018 #define CONFIG_SPEAR_MISCBASE 0xFCA8000019 #define CONFIG_SPEAR_ETHBASE 0xE0800000[all …]
18 #define SPEAR_ICM1_2_BASE UL(0xD0000000)19 #define VA_SPEAR_ICM1_2_BASE IOMEM(0xFD000000)20 #define SPEAR_ICM1_UART_BASE UL(0xD0000000)22 #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)25 #define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000)26 #define VA_SPEAR6XX_ML_CPU_BASE IOMEM(0xF0000000)29 #define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000)30 #define VA_SPEAR_ICM3_SMI_CTRL_BASE IOMEM(0xFC000000)31 #define SPEAR_ICM3_DMA_BASE UL(0xFC400000)32 #define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000)[all …]
14 #address-cells = <0>;15 #size-cells = <0>;25 reg = <0 0x40000000>;32 ranges = <0xd0000000 0xd0000000 0x30000000>;37 reg = <0xf1100000 0x1000>;43 reg = <0xfc400000 0x1000>;51 reg = <0xe0800000 0x8000>;62 reg = <0xfc000000 0x1000>;69 reg = <0xd0100000 0x1000>;72 #size-cells = <0>;[all …]
17 reg = <0xe0700000 0x1000>;18 st-spics,peripcfg-reg = <0x42c>;30 reg = <0xeb800000 0x4000>;38 reg = <0xb1000000 0x10000>;39 interrupts = <0 72 0x4>;40 phys = <&miphy0 0>;47 reg = <0xb1000000 0x4000>, <0x80000000 0x20000>;49 interrupts = <0 68 0x4>;56 ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */57 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */[all …]
12 #address-cells = <0>;13 #size-cells = <0>;23 reg = <0 0x40000000>;30 ranges = <0xd0000000 0xd0000000 0x30000000>;35 reg = <0xf1100000 0x1000>;42 reg = <0xf1000000 0x1000>;48 reg = <0xfc200000 0x1000>;56 reg = <0xfc400000 0x1000>;64 reg = <0xe0800000 0x8000>;76 reg = <0xd1800000 0x1000 /* FSMC Register */[all …]
89 port@0:108 const: 0114 - port@0126 reg = <0xd0100000 0x100000>, <0xc883c000 0x1000>;130 #size-cells = <0>;134 port@0 {135 reg = <0>;
15 #define SDRAM_CS_SIZE 0xfffffff /* FIXME: implement a function for cs size for each platform */18 #define AP_INT_REG_START_ADDR 0xd000000019 #define AP_INT_REG_END_ADDR 0xd010000026 #define TUNE_TRAINING_PARAMS_PHYREG3VAL 0xA35 #define TUNE_TRAINING_PARAMS_DIC 0x236 #define TUNE_TRAINING_PARAMS_ODT_CONFIG_2CS 0x12001237 #define TUNE_TRAINING_PARAMS_ODT_CONFIG_1CS 0x1000038 #define TUNE_TRAINING_PARAMS_RTT_NOM 0x4440 #define TUNE_TRAINING_PARAMS_RTT_WR_1CS 0x0 /*off*/41 #define TUNE_TRAINING_PARAMS_RTT_WR_2CS 0x0 /*off*/[all …]
27 hwrom_reserved: hwrom@0 {28 reg = <0x0 0x0 0x0 0x1000000>;34 reg = <0x0 0x10000000 0x0 0x200000>;40 reg = <0x0 0x05000000 0x0 0x300000>;47 size = <0x0 0x10000000>;48 alignment = <0x0 0x400000>;54 #address-cells = <0x2>;55 #size-cells = <0x0>;57 cpu0: cpu@0 {60 reg = <0x0 0x0>;[all …]
35 hwrom_reserved: hwrom@0 {36 reg = <0x0 0x0 0x0 0x1000000>;42 reg = <0x0 0x10000000 0x0 0x200000>;48 reg = <0x0 0x05000000 0x0 0x300000>;54 reg = <0x0 0x05300000 0x0 0x2000000>;61 size = <0x0 0x10000000>;62 alignment = <0x0 0x400000>;90 #address-cells = <0x2>;91 #size-cells = <0x0>;93 cpu0: cpu@0 {[all …]
27 // base address: 0x028 …BIF_BX_PF_MM_INDEX 0x000029 …ne mmBIF_BX_PF_MM_INDEX_BASE_IDX 030 …BIF_BX_PF_MM_DATA 0x000131 …ne mmBIF_BX_PF_MM_DATA_BASE_IDX 032 …BIF_BX_PF_MM_INDEX_HI 0x000633 …ne mmBIF_BX_PF_MM_INDEX_HI_BASE_IDX 037 // base address: 0x038 …SYSHUB_INDEX_OVLP 0x000839 …ne mmSYSHUB_INDEX_OVLP_BASE_IDX 0[all …]
29 // base address: 0x030 …BIF_BX0_PCIE_INDEX 0x000c31 …e regBIF_BX0_PCIE_INDEX_BASE_IDX 032 …BIF_BX0_PCIE_DATA 0x000d33 …e regBIF_BX0_PCIE_DATA_BASE_IDX 034 …BIF_BX0_PCIE_INDEX2 0x000e35 …e regBIF_BX0_PCIE_INDEX2_BASE_IDX 036 …BIF_BX0_PCIE_DATA2 0x000f37 …e regBIF_BX0_PCIE_DATA2_BASE_IDX 038 …BIF_BX0_PCIE_INDEX_HI 0x0010[all …]
25 #clock-cells = <0>;30 #clock-cells = <0>;36 #size-cells = <0>;38 CPU0: cpu@0 {41 reg = <0x0 0x0>;43 qcom,freq-domain = <&cpufreq_hw 0>;61 reg = <0x0 0x100>;63 qcom,freq-domain = <&cpufreq_hw 0>;76 reg = <0x0 0x200>;78 qcom,freq-domain = <&cpufreq_hw 0>;[all …]
17 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e23 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF24 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 025 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF000031 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF32 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 033 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF000042 #define PIN_CFG_NA 0x0000000043 #define PIN_CFG_GPIO0_P0 0x0000000144 #define PIN_CFG_GPIO1_P0 0x00000002[all …]