Lines Matching +full:0 +full:xd0100000
15 #define SDRAM_CS_SIZE 0xfffffff /* FIXME: implement a function for cs size for each platform */
18 #define AP_INT_REG_START_ADDR 0xd0000000
19 #define AP_INT_REG_END_ADDR 0xd0100000
26 #define TUNE_TRAINING_PARAMS_PHYREG3VAL 0xA
35 #define TUNE_TRAINING_PARAMS_DIC 0x2
36 #define TUNE_TRAINING_PARAMS_ODT_CONFIG_2CS 0x120012
37 #define TUNE_TRAINING_PARAMS_ODT_CONFIG_1CS 0x10000
38 #define TUNE_TRAINING_PARAMS_RTT_NOM 0x44
40 #define TUNE_TRAINING_PARAMS_RTT_WR_1CS 0x0 /*off*/
41 #define TUNE_TRAINING_PARAMS_RTT_WR_2CS 0x0 /*off*/
46 #define REG_DEVICE_SAR1_ADDR 0xe4204
48 #define RST2_CPU_DDR_CLOCK_SELECT_IN_MASK 0x1f
49 #define DEVICE_SAMPLE_AT_RESET2_REG 0x18604
51 #define DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_OFFSET 0
52 #define DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_25MHZ 0
56 #define REG_XBAR_WIN_5_CTRL_ADDR 0x20050
57 #define REG_XBAR_WIN_5_BASE_ADDR 0x20054
60 #define REG_XBAR_WIN_4_CTRL_ADDR 0x20040
61 #define REG_XBAR_WIN_4_BASE_ADDR 0x20044
62 #define REG_XBAR_WIN_4_REMAP_ADDR 0x20048
63 #define REG_XBAR_WIN_7_REMAP_ADDR 0x20078
64 #define REG_XBAR_WIN_16_CTRL_ADDR 0x200d0
65 #define REG_XBAR_WIN_16_BASE_ADDR 0x200d4
66 #define REG_XBAR_WIN_16_REMAP_ADDR 0x200dc
67 #define REG_XBAR_WIN_19_CTRL_ADDR 0x200e8
69 #define REG_FASTPATH_WIN_BASE_ADDR(win) (0x20180 + (0x8 * win))
70 #define REG_FASTPATH_WIN_CTRL_ADDR(win) (0x20184 + (0x8 * win))
72 #define CPU_CONFIGURATION_REG(id) (0x21800 + (id * 0x100))
73 #define CPU_MRVL_ID_OFFSET 0x10
74 #define SAR1_CPU_CORE_MASK 0x00000018
78 #define DDR_SATR_CONFIG_MASK_WIDTH 0x8
79 #define DDR_SATR_CONFIG_MASK_ECC 0x10
80 #define DDR_SATR_CONFIG_MASK_ECC_PUP 0x20
82 #define REG_SAMPLE_RESET_HIGH_ADDR 0x18600
90 #define DLB_CTRL_REG 0x1700
91 #define DLB_EN_OFFS 0
92 #define DLB_EN_MASK 0x1
94 #define DLB_EN_DIS 0
96 #define WR_COALESCE_EN_MASK 0x1
98 #define WR_COALESCE_EN_DIS 0
100 #define AXI_PREFETCH_EN_MASK 0x1
102 #define AXI_PREFETCH_EN_DIS 0
104 #define MBUS_PREFETCH_EN_MASK 0x1
106 #define MBUS_PREFETCH_EN_DIS 0
108 #define PREFETCH_NXT_LN_SZ_TRIG_MASK 0x1
110 #define PREFETCH_NXT_LN_SZ_TRIG_DIS 0
112 #define DLB_BUS_OPT_WT_REG 0x1704
113 #define DLB_AGING_REG 0x1708
114 #define DLB_EVICTION_CTRL_REG 0x170c
115 #define DLB_EVICTION_TIMERS_REG 0x1710
116 #define DLB_USER_CMD_REG 0x1714
117 #define DLB_WTS_DIFF_CS_REG 0x1770
118 #define DLB_WTS_DIFF_BG_REG 0x1774
119 #define DLB_WTS_SAME_BG_REG 0x1778
120 #define DLB_WTS_CMDS_REG 0x177c
121 #define DLB_WTS_ATTR_PRIO_REG 0x1780
122 #define DLB_QUEUE_MAP_REG 0x1784
123 #define DLB_SPLIT_REG 0x1788
129 #define RESULT_CONTROL_BYTE_PUP_0_REG 0x1830
130 #define RESULT_CONTROL_BYTE_PUP_1_REG 0x1834
131 #define RESULT_CONTROL_BYTE_PUP_2_REG 0x1838
132 #define RESULT_CONTROL_BYTE_PUP_3_REG 0x183c
133 #define RESULT_CONTROL_BYTE_PUP_4_REG 0x18b0
136 #define RESULT_CONTROL_PUP_0_BIT_0_REG 0x18b4
137 #define RESULT_CONTROL_PUP_0_BIT_1_REG 0x18b8
138 #define RESULT_CONTROL_PUP_0_BIT_2_REG 0x18bc
139 #define RESULT_CONTROL_PUP_0_BIT_3_REG 0x18c0
140 #define RESULT_CONTROL_PUP_0_BIT_4_REG 0x18c4
141 #define RESULT_CONTROL_PUP_0_BIT_5_REG 0x18c8
142 #define RESULT_CONTROL_PUP_0_BIT_6_REG 0x18cc
143 #define RESULT_CONTROL_PUP_0_BIT_7_REG 0x18f0
145 #define RESULT_CONTROL_PUP_1_BIT_0_REG 0x18f4
146 #define RESULT_CONTROL_PUP_1_BIT_1_REG 0x18f8
147 #define RESULT_CONTROL_PUP_1_BIT_2_REG 0x18fc
148 #define RESULT_CONTROL_PUP_1_BIT_3_REG 0x1930
149 #define RESULT_CONTROL_PUP_1_BIT_4_REG 0x1934
150 #define RESULT_CONTROL_PUP_1_BIT_5_REG 0x1938
151 #define RESULT_CONTROL_PUP_1_BIT_6_REG 0x193c
152 #define RESULT_CONTROL_PUP_1_BIT_7_REG 0x19b0
154 #define RESULT_CONTROL_PUP_2_BIT_0_REG 0x19b4
155 #define RESULT_CONTROL_PUP_2_BIT_1_REG 0x19b8
156 #define RESULT_CONTROL_PUP_2_BIT_2_REG 0x19bc
157 #define RESULT_CONTROL_PUP_2_BIT_3_REG 0x19c0
158 #define RESULT_CONTROL_PUP_2_BIT_4_REG 0x19c4
159 #define RESULT_CONTROL_PUP_2_BIT_5_REG 0x19c8
160 #define RESULT_CONTROL_PUP_2_BIT_6_REG 0x19cc
161 #define RESULT_CONTROL_PUP_2_BIT_7_REG 0x19f0
163 #define RESULT_CONTROL_PUP_3_BIT_0_REG 0x19f4
164 #define RESULT_CONTROL_PUP_3_BIT_1_REG 0x19f8
165 #define RESULT_CONTROL_PUP_3_BIT_2_REG 0x19fc
166 #define RESULT_CONTROL_PUP_3_BIT_3_REG 0x1a30
167 #define RESULT_CONTROL_PUP_3_BIT_4_REG 0x1a34
168 #define RESULT_CONTROL_PUP_3_BIT_5_REG 0x1a38
169 #define RESULT_CONTROL_PUP_3_BIT_6_REG 0x1a3c
170 #define RESULT_CONTROL_PUP_3_BIT_7_REG 0x1ab0
172 #define RESULT_CONTROL_PUP_4_BIT_0_REG 0x1ab4
173 #define RESULT_CONTROL_PUP_4_BIT_1_REG 0x1ab8
174 #define RESULT_CONTROL_PUP_4_BIT_2_REG 0x1abc
175 #define RESULT_CONTROL_PUP_4_BIT_3_REG 0x1ac0
176 #define RESULT_CONTROL_PUP_4_BIT_4_REG 0x1ac4
177 #define RESULT_CONTROL_PUP_4_BIT_5_REG 0x1ac8
178 #define RESULT_CONTROL_PUP_4_BIT_6_REG 0x1acc
179 #define RESULT_CONTROL_PUP_4_BIT_7_REG 0x1af0
182 #define REG_BOOTROM_ROUTINE_ADDR 0x182d0
186 #define TOPOLOGY_UPDATE_32BIT 0
195 {1, 0, 1, 0, 1}, /* RD_AP_68XX_ID */ \
196 {1, 0, 1, 0, 1}, /* DB_AP_68XX_ID */ \
197 {1, 0, 1, 0, 1}, /* DB_GP_68XX_ID */ \
198 {0, 0, 1, 1, 0}, /* DB_BP_6821_ID */ \
219 #define ACTIVE_INTERFACE_MASK 0x1