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Searched +full:0 +full:xc4000000 (Results 1 – 22 of 22) sorted by relevance

/openbmc/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp43x.dtsi13 /* Uses at least up to 0x230 */
14 reg = <0xc4000000 0x1000>;
H A Dintel-ixp42x.dtsi12 reg = <0xc4000000 0x30>;
29 reg = <0xc800b000 0x1000>;
H A Dintel-ixp45x-ixp46x.dtsi14 /* Uses at least up to 0x124 */
15 reg = <0xc4000000 0x1000>;
20 reg = <0x70002100 4>;
33 reg = <0xc800b000 0x1000>;
40 reg = <0xc8011000 0x18>;
48 reg = <0xc800d000 0x1000>;
52 queue-rx = <&qmgr 0>;
53 queue-txready = <&qmgr 0>;
59 reg = <0xc800e000 0x1000>;
63 queue-rx = <&qmgr 0>;
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/
H A Dpsci.S71 PSCI_TABLE(0, 0)
97 PSCI_TABLE(0, 0)
103 ldr x15, =0x3C0
137 ubfx x10, x10, #0, #32
151 ldr x0, =0xFFFFFFFF
155 /* SMC function ID 0x84000000-0x8400001F: 32 bits PSCI */
156 ldr w9, =0x8400001F
159 ldr w9, =0x84000000
171 /* SMC function ID 0xC4000000-0xC400001F: 64 bits PSCI */
172 ldr x9, =0xC400001F
[all …]
/openbmc/u-boot/include/configs/
H A Dstm32mp1.h59 #define CONFIG_SPL_TEXT_BASE 0x2FFC2500
61 #define CONFIG_SPL_BSS_START_ADDR 0xC0200000
62 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
63 #define CONFIG_SYS_SPL_MALLOC_START 0xC0300000
64 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
67 #define CONFIG_SPL_MAX_SIZE 0x00020000
80 func(MMC, mmc, 0) \
92 "scriptaddr=0xC0000000\0" \
93 "pxefile_addr_r=0xC0000000\0" \
94 "kernel_addr_r=0xC1000000\0" \
[all …]
H A Ds32v234evb.h17 #define GICD_BASE 0x7D001000
18 #define GICC_BASE 0x7D002000
28 #define DDR_BASE_ADDR 0x80000000
30 #define DDR_BASE_ADDR 0xC0000000
46 #define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
75 #if 0
82 #define CONFIG_FEC_MXC_PHYADDR 0
85 #if 0 /* Disable until the FLASH will be implemented */
94 #define CONFIG_SYS_NAND_BASE 0x400E0000
101 #define CONFIG_LOADADDR 0xC307FFC0
[all …]
/openbmc/linux/Documentation/devicetree/bindings/ata/
H A Dintel,ixp4xx-compact-flash.yaml48 reg = <0xc4000000 0x1000>;
52 ranges = <0 0x0 0x50000000 0x01000000>, <1 0x0 0x51000000 0x01000000>;
53 dma-ranges = <0 0x0 0x50000000 0x01000000>, <1 0x0 0x51000000 0x01000000>;
54 ide@1,0 {
56 reg = <1 0x00000000 0x1000>, <1 0x00040000 0x1000>;
/openbmc/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs-sev-kit.dts42 reg = <0x0 0x80000000 0x0 0x2000000>;
47 reg = <0x0 0xc4000000 0x0 0x4000000>;
52 reg = <0x0 0xd4000000 0x0 0x4000000>;
58 reg = <0x10 0x0 0x0 0x76000000>;
/openbmc/u-boot/arch/arm/include/asm/
H A Dpsci.h21 #define ARM_PSCI_VER_1_0 (0x00010000)
22 #define ARM_PSCI_VER_0_2 (0x00000002)
25 #define ARM_PSCI_FN_BASE 0x95c1ba5e
28 #define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(0)
33 #define ARM_PSCI_RET_SUCCESS 0
45 #define ARM_PSCI_0_2_FN_BASE 0x84000000
48 #define ARM_PSCI_0_2_FN64_BASE 0xC4000000
51 #define ARM_PSCI_0_2_FN_PSCI_VERSION ARM_PSCI_0_2_FN(0)
89 #define PSCI_AFFINITY_LEVEL_ON 0
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dintel,ixp4xx-expansion-bus-controller.yaml19 pattern: '^bus@[0-9a-f]+$'
55 "^.*@[0-7],[0-9a-f]+$":
78 reg = <0xc4000000 0x28>;
82 ranges = <0 0x0 0x50000000 0x01000000>,
83 <1 0x0 0x51000000 0x01000000>;
84 dma-ranges = <0 0x0 0x50000000 0x01000000>,
85 <1 0x0 0x51000000 0x01000000>;
86 flash@0,0 {
89 reg = <0 0x00000000 0x1000000>;
91 intel,ixp4xx-eb-cycle-type = <0>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/infiniband/
H A Dhisilicon-hns-roce.txt25 - hns-roce-comp-0 ~ hns-roce-comp-31: 32 complete event irq
31 reg = <0x0 0xc4000000 0x0 0x100000>;
74 interrupt-names = "hns-roce-comp-0",
/openbmc/qemu/hw/arm/
H A Dkzm.c31 * 0x00000000-0x7fffffff See i.MX31 SOC for support
32 * 0x80000000-0x8fffffff RAM EMULATED
33 * 0x90000000-0x9fffffff RAM EMULATED
34 * 0xa0000000-0xafffffff Flash IGNORED
35 * 0xb0000000-0xb3ffffff Unavailable IGNORED
36 * 0xb4000000-0xb4000fff 8-bit free space IGNORED
37 * 0xb4001000-0xb400100f Board control IGNORED
38 * 0xb4001003 DIP switch
39 * 0xb4001010-0xb400101f 7-segment LED IGNORED
40 * 0xb4001020-0xb400102f LED IGNORED
[all …]
/openbmc/linux/arch/arm/boot/dts/nspire/
H A Dnspire.dtsi13 #size-cells = <0>;
15 cpu@0 {
18 reg = <0>;
22 bootrom: bootrom@0 {
23 reg = <0x00000000 0x80000>;
28 reg = <0xa4000000 0x20000>; /* 128k */
31 ranges = <0 0xa4000000 0x20000>;
33 sram@0 {
34 reg = <0x0 0x20000>;
39 #clock-cells = <0>;
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dcpu_init.c101 u32 temp = 0; in fsl_erratum_a006261_workaround()
140 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { in config_qe_ioports()
156 for (portnum = 0; portnum < 4; portnum++) { in config_8560_ioports()
157 uint pmsk = 0, in config_8560_ioports()
158 ppar = 0, in config_8560_ioports()
159 psor = 0, in config_8560_ioports()
160 pdir = 0, in config_8560_ioports()
161 podr = 0, in config_8560_ioports()
162 pdat = 0; in config_8560_ioports()
163 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; in config_8560_ioports()
[all …]
/openbmc/linux/crypto/
H A Daes_generic.c67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]
/openbmc/qemu/disas/
H A Dmicroblaze.c137 /* gen purpose regs go from 0 to 31 */
140 #define REG_PC_MASK 0x8000
141 #define REG_MSR_MASK 0x8001
142 #define REG_EAR_MASK 0x8003
143 #define REG_ESR_MASK 0x8005
144 #define REG_FSR_MASK 0x8007
145 #define REG_BTR_MASK 0x800b
146 #define REG_EDR_MASK 0x800d
147 #define REG_PVR_MASK 0xa000
149 #define REG_PID_MASK 0x9000
[all …]
H A Dmips.c82 #define OP_MASK_OP 0x3f
84 #define OP_MASK_RS 0x1f
86 #define OP_MASK_FR 0x1f
88 #define OP_MASK_FMT 0x1f
90 #define OP_MASK_BCC 0x7
92 #define OP_MASK_CODE 0x3ff
94 #define OP_MASK_CODE2 0x3ff
96 #define OP_MASK_RT 0x1f
98 #define OP_MASK_FT 0x1f
100 #define OP_MASK_CACHE 0x1f
[all …]
H A Dnanomips.c62 return g_strdup_printf("0x%" PRIx64, a); in to_string()
97 * 1 0
98 * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
107 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
108 * 3 2 1 0
123 sizeof(register_list) / sizeof(register_list[0]), info); in decode_gpr_gpr4()
132 * 1 0
133 * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
142 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
143 * 3 2 1 0
[all …]
/openbmc/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip07.dtsi23 #size-cells = <0>;
270 reg = <0x10000>;
273 numa-node-id = <0>;
279 reg = <0x10001>;
282 numa-node-id = <0>;
288 reg = <0x10002>;
291 numa-node-id = <0>;
297 reg = <0x10003>;
300 numa-node-id = <0>;
306 reg = <0x10100>;
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_enum.h28 NUMBER_UNORM = 0x0,
29 NUMBER_SNORM = 0x1,
30 NUMBER_USCALED = 0x2,
31 NUMBER_SSCALED = 0x3,
32 NUMBER_UINT = 0x4,
33 NUMBER_SINT = 0x5,
34 NUMBER_SRGB = 0x6,
35 NUMBER_FLOAT = 0x7,
38 SWAP_STD = 0x0,
39 SWAP_ALT = 0x1,
[all …]
H A Dgfx_8_1_enum.h28 NUMBER_UNORM = 0x0,
29 NUMBER_SNORM = 0x1,
30 NUMBER_USCALED = 0x2,
31 NUMBER_SSCALED = 0x3,
32 NUMBER_UINT = 0x4,
33 NUMBER_SINT = 0x5,
34 NUMBER_SRGB = 0x6,
35 NUMBER_FLOAT = 0x7,
38 SWAP_STD = 0x0,
39 SWAP_ALT = 0x1,
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/
H A Dvega10_enum.h51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
184 NO_FORCE_REQUEST = 0x00000000,
185 FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
186 FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
187 FORCE_SHUT_DOWN_REQUEST = 0x00000003,
195 NO_FORCE_REQ = 0x00000000,
196 FORCE_LIGHT_SLEEP_REQ = 0x00000001,
204 ENABLE_MEM_PWR_CTRL = 0x00000000,
205 DISABLE_MEM_PWR_CTRL = 0x00000001,
213 DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000,
[all …]