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/openbmc/u-boot/fs/yaffs2/
H A Dyaffs_nameval.c32 static int nval_find(const char *xb, int xb_size, const YCHAR *name, in nval_find() argument
35 int pos = 0; in nval_find()
38 memcpy(&size, xb, sizeof(int)); in nval_find()
39 while (size > 0 && (size < xb_size) && (pos + size < xb_size)) { in nval_find()
40 if (!yaffs_strncmp((YCHAR *) (xb + pos + sizeof(int)), in nval_find()
48 memcpy(&size, xb + pos, sizeof(int)); in nval_find()
50 size = 0; in nval_find()
53 *exist_size = 0; in nval_find()
57 static int nval_used(const char *xb, int xb_size) in nval_used() argument
59 int pos = 0; in nval_used()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/thm/
H A Dthm_13_0_2_sh_mask.h30 …ON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0
31 …ON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5
32 …ON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7
33 …ON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8
34 …N_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10
35 …N_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12
36 …N_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13
37 …N_CUR_TMP__MCM_EN__SHIFT 0x14
38 …N_CUR_TMP__CUR_TEMP__SHIFT 0x15
39 …MP__PER_STEP_TIME_UP_MASK 0x0000001FL
[all …]
H A Dthm_9_0_sh_mask.h27 …ON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0
28 …ON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5
29 …ON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7
30 …ON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8
31 …N_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10
32 …N_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12
33 …N_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13
34 …N_CUR_TMP__MCM_EN__SHIFT 0x14
35 …N_CUR_TMP__CUR_TEMP__SHIFT 0x15
36 …MP__PER_STEP_TIME_UP_MASK 0x0000001FL
[all …]
H A Dthm_10_0_sh_mask.h27 …ON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0
28 …ON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5
29 …ON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7
30 …ON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8
31 …N_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10
32 …N_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12
33 …N_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13
34 …N_CUR_TMP__MCM_EN__SHIFT 0x14
35 …N_CUR_TMP__CUR_TEMP__SHIFT 0x15
36 …MP__PER_STEP_TIME_UP_MASK 0x0000001FL
[all …]
/openbmc/qemu/target/ppc/translate/
H A Dvsx-impl.c.inc150 TCGv_i64 mask = tcg_constant_i64(0x00FF00FF00FF00FF);
544 tcg_gen_movi_i64(t0, 0);
582 #define SGN_MASK_DP 0x8000000000000000ull
583 #define SGN_MASK_SP 0x8000000080000000ull
584 #define EXP_MASK_DP 0x7FF0000000000000ull
585 #define EXP_MASK_SP 0x7F8000007F800000ull
592 TCGv_i64 xb, sgm; \
597 xb = tcg_temp_new_i64(); \
599 get_cpu_vsr(xb, xB(ctx->opcode), true); \
603 tcg_gen_andc_i64(xb, xb, sgm); \
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
/openbmc/qemu/target/ppc/
H A Dfpu_helper.c30 r.high = x.high | 0x0000800000000000; in float128_snan_to_qnan()
35 #define float64_snan_to_qnan(x) ((x) | 0x0008000000000000ULL)
36 #define float32_snan_to_qnan(x) ((x) | 0x00400000)
37 #define float16_snan_to_qnan(x) ((x) | 0x0200)
53 return (env->msr & ((1U << MSR_FE0) | (1U << MSR_FE1))) != 0; in fp_exceptions_enabled()
66 uint32_t abs_arg = arg & 0x7fffffff; in helper_todouble()
69 if (likely(abs_arg >= 0x00800000)) { in helper_todouble()
70 if (unlikely(extract32(arg, 23, 8) == 0xff)) { in helper_todouble()
73 ret |= (uint64_t)0x7ff << 52; in helper_todouble()
74 ret |= (uint64_t)extract32(arg, 0, 23) << 29; in helper_todouble()
[all …]
/openbmc/linux/drivers/ata/pata_parport/
H A Dktti.c20 #define j44(a, b) (((a >> 4) & 0x0f) | (b & 0xf0))
23 * cont = 0 - access the IDE register file
26 static int cont_map[2] = { 0x10, 0x08 };
32 w0(r); w2(0xb); w2(0xa); w2(3); w2(6); in ktti_write_regr()
33 w0(val); w2(3); w0(0); w2(6); w2(0xb); in ktti_write_regr()
42 w0(r); w2(0xb); w2(0xa); w2(9); w2(0xc); w2(9); in ktti_read_regr()
43 a = r1(); w2(0xc); b = r1(); w2(9); w2(0xc); w2(9); in ktti_read_regr()
51 for (k = 0; k < count / 2; k++) { in ktti_read_block()
52 w0(0x10); w2(0xb); w2(0xa); w2(9); w2(0xc); w2(9); in ktti_read_block()
53 a = r1(); w2(0xc); b = r1(); w2(9); in ktti_read_block()
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-benchmark/libhugetlbfs/files/
H A D0002-libhugetlbfs-avoid-search-host-library-path-for-cros.patch11 ldscripts/elf32ppclinux.xB | 2 +-
13 ldscripts/elf64ppc.xB | 2 +-
15 ldscripts/elf_x86_64.xB | 2 +-
19 diff --git a/ldscripts/elf32ppclinux.xB b/ldscripts/elf32ppclinux.xB
21 --- a/ldscripts/elf32ppclinux.xB
22 +++ b/ldscripts/elf32ppclinux.xB
45 diff --git a/ldscripts/elf64ppc.xB b/ldscripts/elf64ppc.xB
47 --- a/ldscripts/elf64ppc.xB
48 +++ b/ldscripts/elf64ppc.xB
71 diff --git a/ldscripts/elf_x86_64.xB b/ldscripts/elf_x86_64.xB
[all …]
H A D0005-libhugetlbfs-elf_i386-avoid-search-host-library-path.patch11 ldscripts/elf_i386.xB | 1 -
15 diff --git a/ldscripts/elf_i386.xB b/ldscripts/elf_i386.xB
17 --- a/ldscripts/elf_i386.xB
18 +++ b/ldscripts/elf_i386.xB
26 __DYNAMIC = 0; */
38 __DYNAMIC = 0; */
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_1_3_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define GCK_MCLK_FUSES__StartupMClkDid_MASK 0x7f
32 #define GCK_MCLK_FUSES__StartupMClkDid__SHIFT 0x0
33 #define GCK_MCLK_FUSES__MClkADCA_MASK 0x780
34 #define GCK_MCLK_FUSES__MClkADCA__SHIFT 0x7
35 #define GCK_MCLK_FUSES__MClkDDCA_MASK 0x1800
36 #define GCK_MCLK_FUSES__MClkDDCA__SHIFT 0xb
[all …]
H A Dsmu_7_1_0_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
H A Dsmu_7_1_2_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
/openbmc/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-kirkwood.c20 ((f6180 << 0) | (f6190 << 1) | (f6192 << 2) | \
25 VARIANT_MV88F6180 = V(1, 0, 0, 0, 0, 0, 0),
26 VARIANT_MV88F6190 = V(0, 1, 0, 0, 0, 0, 0),
27 VARIANT_MV88F6192 = V(0, 0, 1, 0, 0, 0, 0),
28 VARIANT_MV88F6281 = V(0, 0, 0, 1, 0, 0, 0),
29 VARIANT_MV88F6282 = V(0, 0, 0, 0, 1, 0, 0),
30 VARIANT_MV98DX4122 = V(0, 0, 0, 0, 0, 1, 0),
31 VARIANT_MV98DX1135 = V(0, 0, 0, 0, 0, 0, 1),
35 MPP_MODE(0,
36 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1, 1)),
[all …]
/openbmc/linux/arch/powerpc/math-emu/
H A Dmath_efp.c32 #define EFAPU 0x4
34 #define VCT 0x4
35 #define SPFP 0x6
36 #define DPFP 0x7
38 #define EFSADD 0x2c0
39 #define EFSSUB 0x2c1
40 #define EFSABS 0x2c4
41 #define EFSNABS 0x2c5
42 #define EFSNEG 0x2c6
43 #define EFSMUL 0x2c8
[all …]
H A Dmath.c29 void *op4) { return 0; }
80 #define OP31 0x1f /* 31 */
81 #define LFS 0x30 /* 48 */
82 #define LFSU 0x31 /* 49 */
83 #define LFD 0x32 /* 50 */
84 #define LFDU 0x33 /* 51 */
85 #define STFS 0x34 /* 52 */
86 #define STFSU 0x35 /* 53 */
87 #define STFD 0x36 /* 54 */
88 #define STFDU 0x37 /* 55 */
[all …]
/openbmc/qemu/tests/tcg/i386/
H A Dtest-i386-f2xm1.c14 { 0x4.1481697ac693aa6p-4L, 0x3.17ec9f8454896518p-4L, 0x3.17ec9f845489651cp-4L },
15 { -0xd.84a873b14b9c0e2p-4L, -0x7.1788c46ac260d948p-4L, -0x7.1788c46ac260d94p-4L },
16 { 0xa.a3dc18b1eff7e8ap-188L, 0x7.6009241b9e21523p-188L, 0x7.6009241b9e215238p-188L },
17 { -0xe.846aeb6f58174d5p-92L, -0xa.1006405817acc33p-92L, -0xa.1006405817acc32p-92L },
18 { 0x5.4459f2ac77bb0978p-4L, 0x4.19d3ce7fd5b90ac8p-4L, 0x4.19d3ce7fd5b90adp-4L },
19 { -0xb.79bece734a62216p-4L, -0x6.4489a7fc150c0fp-4L, -0x6.4489a7fc150c0ef8p-4L },
20 { 0xa.ab48f9ef732f5c4p-4L, 0x9.66acd7d4b7cf015p-4L, 0x9.66acd7d4b7cf016p-4L },
21 { -0xb.8204e63359a46e6p-4L, -0x6.48060f0a504e3488p-4L, -0x6.48060f0a504e348p-4L },
22 { 0xd.c732865701ae935p-4L, 0xd.103bc1a15cd9f71p-4L, 0xd.103bc1a15cd9f72p-4L },
23 { -0x1.6296e8ff499827a2p-4L, -0xe.e8dc973f0bce9d1p-8L, -0xe.e8dc973f0bce9dp-8L },
[all …]
H A Dtest-i386-fpatan.c10 { -__builtin_infl(), -__builtin_infl(), -0x2.5b2f8fe6643a46ap+0L, -0x2.5b2f8fe6643a469cp+0L },
11 { -__builtin_infl(), -1.0L, -0x3.243f6a8885a308d4p+0L, -0x3.243f6a8885a308dp+0L },
12 { -__builtin_infl(), -0.0L, -0x3.243f6a8885a308d4p+0L, -0x3.243f6a8885a308dp+0L },
13 { -__builtin_infl(), 0.0L, 0x3.243f6a8885a308dp+0L, 0x3.243f6a8885a308d4p+0L },
14 { -__builtin_infl(), 1.0L, 0x3.243f6a8885a308dp+0L, 0x3.243f6a8885a308d4p+0L },
15 { -__builtin_infl(), __builtin_infl(), 0x2.5b2f8fe6643a469cp+0L, 0x2.5b2f8fe6643a46ap+0L },
16 { -1.0L, -__builtin_infl(), -0x1.921fb54442d1846ap+0L, -0x1.921fb54442d18468p+0L },
17 { -1.0L, -0.0L, -0x3.243f6a8885a308d4p+0L, -0x3.243f6a8885a308dp+0L },
18 { -1.0L, 0.0L, 0x3.243f6a8885a308dp+0L, 0x3.243f6a8885a308d4p+0L },
19 { -1.0L, __builtin_infl(), 0x1.921fb54442d18468p+0L, 0x1.921fb54442d1846ap+0L },
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7ulp-pinfunc.h15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_4_2_3_sh_mask.h31 …S_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
32 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
34 …S_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
35 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
40 …S_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
41 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
43 …S_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
44 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
49 …S_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
50 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_0_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x30
36 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_8_2_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
/openbmc/linux/drivers/char/xillybus/
H A Dxillyusb.c55 #define USB_VENDOR_ID_XILINX 0x03fd
56 #define USB_VENDOR_ID_ALTERA 0x09fb
58 #define USB_PRODUCT_ID_XILLYUSB 0xebbe
198 OPCODE_DATA = 0,
207 OPCODE_QUIESCE = 0,
228 unsigned int done = 0; in fifo_write()
242 if (n == 0) { in fifo_write()
268 writepos = 0; in fifo_write()
272 writebuf = 0; in fifo_write()
281 unsigned int done = 0; in fifo_read()
[all …]
/openbmc/qemu/tests/qemu-iotests/
H A D05827 seq=`basename $0`
48 trap "_cleanup; exit \$status" 0 1 2 3 15
62 _unsupported_imgopts 'refcount_bits=1[^0-9]' data_file
74 $QEMU_IO -c 'write -P 0xa 0x1000 0x1000' "$TEST_IMG" | _filter_qemu_io
75 $QEMU_IO -c 'write -P 0xb 0x2000 0x1000' "$TEST_IMG" | _filter_qemu_io
77 $QEMU_IO -c 'write -P 0xc 0x1000 0x1000' "$TEST_IMG" | _filter_qemu_io
78 $QEMU_IO -c 'write -P 0xd 0x2000 0x1000' "$TEST_IMG" | _filter_qemu_io
83 $QEMU_IO -c 'read -P 0xc 0x1000 0x1000' "$TEST_IMG" | _filter_qemu_io
84 $QEMU_IO -c 'read -P 0xd 0x2000 0x1000' "$TEST_IMG" | _filter_qemu_io
90 $QEMU_IO_NBD -r -c 'read -P 0xa 0x1000 0x1000' "$nbd_snapshot_img" | _filter_qemu_io
[all …]
/openbmc/linux/drivers/gpio/
H A Dgpio-104-dio-48e.c32 module_param_hw_array(base, uint, ioport, &num_dio48e, 0);
37 module_param_hw_array(irq, uint, irq, &num_irq, 0);
40 #define DIO48E_ENABLE_INTERRUPT 0xB
42 #define DIO48E_ENABLE_COUNTER_TIMER_ADDRESSING 0xD
44 #define DIO48E_CLEAR_INTERRUPT 0xF
49 regmap_reg_range(0x0, 0x9), regmap_reg_range(0xB, 0xB),
50 regmap_reg_range(0xD, 0xD), regmap_reg_range(0xF, 0xF),
53 regmap_reg_range(0x0, 0x2), regmap_reg_range(0x4, 0x6),
54 regmap_reg_range(0xB, 0xB), regmap_reg_range(0xD, 0xD),
55 regmap_reg_range(0xF, 0xF),
[all …]

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