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/openbmc/u-boot/include/configs/
H A Dcolibri_pxa270.h17 #define CONFIG_BOARD_SIZE_LIMIT 0x40000
29 "if fatload mmc 0 0xa0000000 uImage; then " \
30 "bootm 0xa0000000; " \
32 "if usb reset && fatload usb 0 0xa0000000 uImage; then " \
33 "bootm 0xa0000000; " \
35 "bootm 0xc0000;"
69 #define CONFIG_DM9000_BASE 0x08000000
82 #define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
87 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
88 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
[all …]
H A Dls1088aqds.h18 #define CONFIG_SYS_MMC_ENV_DEV 0
20 #define CONFIG_ENV_SIZE 0x20000
21 #define CONFIG_ENV_OFFSET 0x500000
24 #define CONFIG_ENV_SECT_SIZE 0x40000
27 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
28 #define CONFIG_ENV_SECT_SIZE 0x40000
31 #define CONFIG_SYS_MMC_ENV_DEV 0
32 #define CONFIG_ENV_SIZE 0x2000
34 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
35 #define CONFIG_ENV_SECT_SIZE 0x20000
[all …]
H A Dls2080aqds.h20 #define CONFIG_SYS_I2C_IFDR_DIV 0x7e
23 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
31 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
32 #define SPD_EEPROM_ADDRESS1 0x51
33 #define SPD_EEPROM_ADDRESS2 0x52
34 #define SPD_EEPROM_ADDRESS3 0x53
35 #define SPD_EEPROM_ADDRESS4 0x54
36 #define SPD_EEPROM_ADDRESS5 0x55
37 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
39 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
[all …]
H A Dzipitz2.h23 #define CONFIG_ENV_ADDR 0x40000
24 #define CONFIG_ENV_SIZE 0x10000
30 "if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\
32 "source 0xa0000000; " \
34 "bootm 0x50000; " \
55 #define CONFIG_SYS_MMC_BASE 0xF0000000
83 #define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=System…
88 #define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */
89 #define PHYS_SRAM_SIZE 0x00040000 /* 256k */
94 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
[all …]
H A Dapf27.h30 #define CONFIG_SPL_TEXT_BASE 0xA0000000
34 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
36 #define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN - 0x800
54 #define PHYS_SDRAM_1 0xA0000000
55 #define PHYS_SDRAM_2 0xB0000000
58 #define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest test area */
59 #define CONFIG_SYS_MEMTEST_END 0xA0300000 /* 3 MiB RAM test */
62 + PHYS_SDRAM_1_SIZE - 0x0100000)
67 #define ACFG_MONITOR_OFFSET 0x00000000
68 #define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */
[all …]
/openbmc/u-boot/drivers/dma/
H A DMCD_tasks.c66 0x00000000,
67 0x00000000,
68 (u32) MCD_varTab0, /* Task 0 Variable Table */
69 (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
70 0x00000000,
71 0x00000000,
72 (u32) MCD_contextSave0, /* Task 0 context save space */
73 0x00000000,
74 0x00000000,
75 0x00000000,
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dp1020rdb.dts18 reg = <0 0xffe05000 0 0x1000>;
21 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
22 0x1 0x0 0x0 0xffa00000 0x00040000
23 0x2 0x0 0x0 0xffb00000 0x00020000>;
27 ranges = <0x0 0x0 0xffe00000 0x100000>;
31 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
32 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
33 reg = <0 0xffe09000 0 0x1000>;
34 pcie@0 {
35 ranges = <0x2000000 0x0 0xa0000000
[all …]
H A Dp2020ds.dts19 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
20 0x1 0x0 0x0 0xe0000000 0x08000000
21 0x2 0x0 0x0 0xffa00000 0x00040000
22 0x3 0x0 0x0 0xffdf0000 0x00008000
23 0x4 0x0 0x0 0xffa40000 0x00040000
24 0x5 0x0 0x0 0xffa80000 0x00040000
25 0x6 0x0 0x0 0xffac0000 0x00040000>;
26 reg = <0 0xffe05000 0 0x1000>;
30 ranges = <0x0 0x0 0xffe00000 0x100000>;
34 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
[all …]
H A Dmpc8572ds.dts19 reg = <0 0xffe05000 0 0x1000>;
21 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
22 0x1 0x0 0x0 0xe0000000 0x08000000
23 0x2 0x0 0x0 0xffa00000 0x00040000
24 0x3 0x0 0x0 0xffdf0000 0x00008000
25 0x4 0x0 0x0 0xffa40000 0x00040000
26 0x5 0x0 0x0 0xffa80000 0x00040000
27 0x6 0x0 0x0 0xffac0000 0x00040000>;
31 ranges = <0x0 0 0xffe00000 0x100000>;
35 reg = <0 0xffe08000 0 0x1000>;
[all …]
H A Dmpc8536ds.dts17 #size-cells = <0>;
19 PowerPC,8536@0 {
21 reg = <0>;
28 reg = <0 0 0 0>; // Filled by U-Boot
32 reg = <0 0xffe05000 0 0x1000>;
34 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
35 0x2 0x0 0x0 0xffa00000 0x00040000
36 0x3 0x0 0x0 0xffdf0000 0x00008000>;
40 ranges = <0x0 0 0xffe00000 0x100000>;
44 reg = <0 0xffe08000 0 0x1000>;
[all …]
H A Dp1010rdb_32b.dtsi41 ranges = <0x0 0x0 0x0 0xee000000 0x02000000
42 0x1 0x0 0x0 0xff800000 0x00010000
43 0x3 0x0 0x0 0xffb00000 0x00000020>;
44 reg = <0x0 0xffe1e000 0 0x2000>;
48 ranges = <0x0 0x0 0xffe00000 0x100000>;
52 reg = <0 0xffe09000 0 0x1000>;
53 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
54 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
55 pcie@0 {
56 ranges = <0x2000000 0x0 0xa0000000
[all …]
H A Dmpc8544ds.dts16 reg = <0 0 0 0>; // Filled by U-Boot
20 reg = <0 0xe0005000 0 0x1000>;
22 ranges = <0x0 0x0 0x0 0xff800000 0x800000>;
26 ranges = <0x0 0x0 0xe0000000 0x100000>;
30 reg = <0 0xe0008000 0 0x1000>;
31 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
32 0x1000000 0x0 0x00000000 0 0xe1000000 0x0 0x10000>;
34 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
37 /* IDSEL 0x11 J17 Slot 1 */
38 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
[all …]
H A Dp1021rdb-pc_32b.dts45 reg = <0 0xffe05000 0 0x1000>;
48 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
49 0x1 0x0 0x0 0xff800000 0x00040000
50 0x2 0x0 0x0 0xffb00000 0x00020000>;
54 ranges = <0x0 0x0 0xffe00000 0x100000>;
58 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
59 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
60 reg = <0 0xffe09000 0 0x1000>;
61 pcie@0 {
62 ranges = <0x2000000 0x0 0xa0000000
[all …]
H A Dp1025twr.dts45 reg = <0 0xffe05000 0 0x1000>;
48 ranges = <0x0 0x0 0x0 0xec000000 0x04000000
49 0x2 0x0 0x0 0xe0000000 0x00020000>;
53 ranges = <0x0 0x0 0xffe00000 0x100000>;
57 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
58 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
59 reg = <0 0xffe09000 0 0x1000>;
60 pcie@0 {
61 ranges = <0x2000000 0x0 0xa0000000
62 0x2000000 0x0 0xa0000000
[all …]
H A Dp1020rdb-pc_32b.dts45 reg = <0 0xffe05000 0 0x1000>;
48 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
49 0x1 0x0 0x0 0xff800000 0x00040000
50 0x2 0x0 0x0 0xffb00000 0x00020000
51 0x3 0x0 0x0 0xffa00000 0x00020000>;
55 ranges = <0x0 0x0 0xffe00000 0x100000>;
59 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
60 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
61 reg = <0 0xffe09000 0 0x1000>;
62 pcie@0 {
[all …]
H A Dge_imp3a.dts22 reg = <0 0xfef05000 0 0x1000>;
24 ranges = <0x0 0x0 0x0 0xff000000 0x01000000
25 0x1 0x0 0x0 0xe0000000 0x08000000
26 0x2 0x0 0x0 0xe8000000 0x08000000
27 0x3 0x0 0x0 0xfc100000 0x00020000
28 0x4 0x0 0x0 0xfc000000 0x00008000
29 0x5 0x0 0x0 0xfc008000 0x00008000
30 0x6 0x0 0x0 0xfee00000 0x00040000
31 0x7 0x0 0x0 0xfee80000 0x00040000>;
33 /* nor@0,0 is a mirror of part of the memory in nor@1,0
[all …]
H A Dmvme2500.dts29 ranges = <0x0 0 0xffe00000 0x100000>;
34 reg = <0x4c>;
39 reg = <0x68>;
40 interrupts = <8 1 0 0>;
45 reg = <0x54>;
50 reg = <0x52>;
55 reg = <0x53>;
60 reg = <0x50>;
68 flash@0 {
70 reg = <0>;
[all …]
H A Dp2020rdb.dts29 reg = <0 0xffe05000 0 0x1000>;
32 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
33 0x1 0x0 0x0 0xffa00000 0x00040000
34 0x2 0x0 0x0 0xffb00000 0x00020000>;
36 nor@0,0 {
40 reg = <0x0 0x0 0x1000000>;
44 partition@0 {
47 reg = <0x0 0x00040000>;
54 reg = <0x00040000 0x00040000>;
61 reg = <0x00080000 0x00380000>;
[all …]
H A Dp1023rdb.dts56 size = <0 0x1000000>;
57 alignment = <0 0x1000000>;
60 size = <0 0x400000>;
61 alignment = <0 0x400000>;
64 size = <0 0x2000000>;
65 alignment = <0 0x2000000>;
70 ranges = <0x0 0xf 0xff000000 0x200000>;
74 ranges = <0x0 0xf 0xff200000 0x200000>;
78 ranges = <0x0 0x0 0xff600000 0x200000>;
83 reg = <0x53>;
[all …]
H A Dp1020rdb-pd.dts45 reg = <0x0 0xffe05000 0x0 0x1000>;
48 ranges = <0x0 0x0 0x0 0xec000000 0x04000000
49 0x1 0x0 0x0 0xff800000 0x00040000
50 0x2 0x0 0x0 0xffa00000 0x00020000
51 0x3 0x0 0x0 0xffb00000 0x00020000>;
53 nor@0,0 {
57 reg = <0x0 0x0 0x4000000>;
61 partition@0 {
63 reg = <0x0 0x00020000>;
69 reg = <0x00020000 0x003e0000>;
[all …]
/openbmc/u-boot/doc/uImage.FIT/
H A Dmulti-with-loadables.its20 load = <0xa0000000>;
21 entry = <0xa0000000>;
33 load = <0xb0000000>;
45 load = <0xb0400000>;
58 load = <0xa0000000>;
59 entry = <0xa0000000>;
/openbmc/linux/arch/arm/boot/dts/st/
H A Dspear300.dtsi15 ranges = <0x60000000 0x60000000 0x50000000
16 0xd0000000 0xd0000000 0x30000000>;
20 reg = <0x99000000 0x1000>;
25 reg = <0x60000000 0x1000>;
34 reg = <0x94000000 0x1000 /* FSMC Register */
35 0x80000000 0x0010 /* NAND Base DATA */
36 0x80020000 0x0010 /* NAND Base ADDR */
37 0x80010000 0x0010>; /* NAND Base CMD */
44 reg = <0x70000000 0x100>;
51 reg = <0x50000000 0x1000>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/bluetooth/
H A Dbrcm,bcm4377-bluetooth.yaml70 reg = <0xa0000000 0x1000000>;
72 ranges = <0x43000000 0x6 0xa0000000 0xa0000000 0x0 0x20000000>;
74 bluetooth@0,1 {
76 reg = <0x100 0x0 0x0 0x0 0x0>;
/openbmc/u-boot/arch/arm/mach-uniphier/bcu/
H A Dbcu-ld4.c13 #define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
19 writel(0x44444444, BCSCR0); /* 0x20000000-0x3fffffff: ASM bus */ in uniphier_ld4_bcu_init()
20 writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */ in uniphier_ld4_bcu_init()
21 writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */ in uniphier_ld4_bcu_init()
22 writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */ in uniphier_ld4_bcu_init()
23 writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */ in uniphier_ld4_bcu_init()
26 shift = bd->dram_ch[0].size / 0x04000000 * 4; in uniphier_ld4_bcu_init()
27 writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */ in uniphier_ld4_bcu_init()
30 writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */ in uniphier_ld4_bcu_init()
33 writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */ in uniphier_ld4_bcu_init()
/openbmc/linux/arch/arm/boot/dts/sigmastar/
H A Dmstar-v7.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg = <0x0>;
55 #clock-cells = <0>;
61 #clock-cells = <0>;
68 #clock-cells = <0>;
80 ranges = <0x16001000 0x16001000 0x00007000>,
81 <0x1f000000 0x1f000000 0x00400000>,
82 <0xa0000000 0xa0000000 0x20000>;
86 reg = <0x16001000 0x1000>,
[all …]

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