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/openbmc/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt8516.c18 /* 0E4E8SR 4/8/12/16 */
20 /* 0E2E4SR 2/4/6/8 */
23 MTK_DRV_GRP(2, 16, 0, 2, 2)
27 MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
28 MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
29 MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
30 MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
31 MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
33 MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
34 MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
[all …]
H A Dpinctrl-mt8167.c18 /* 0E4E8SR 4/8/12/16 */
20 /* 0E2E4SR 2/4/6/8 */
23 MTK_DRV_GRP(2, 16, 0, 2, 2)
27 MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
28 MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
29 MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
30 MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
31 MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
33 MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
34 MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dpm8550vs.dtsi13 polling-delay = <0>;
20 hysteresis = <0>;
26 hysteresis = <0>;
34 polling-delay = <0>;
41 hysteresis = <0>;
47 hysteresis = <0>;
55 polling-delay = <0>;
62 hysteresis = <0>;
68 hysteresis = <0>;
76 polling-delay = <0>;
[all …]
H A Dsa8775p-pmics.dtsi11 pmm8654au_0_thermal: pm8775-0-thermal {
13 polling-delay = <0>;
19 hysteresis = <0>;
25 hysteresis = <0>;
33 polling-delay = <0>;
39 hysteresis = <0>;
45 hysteresis = <0>;
53 polling-delay = <0>;
59 hysteresis = <0>;
65 hysteresis = <0>;
[all …]
H A Dpmr735d.dtsi13 polling-delay = <0>;
20 hysteresis = <0>;
26 hysteresis = <0>;
34 polling-delay = <0>;
41 hysteresis = <0>;
47 hysteresis = <0>;
59 reg = <0xa SPMI_USID>;
61 #size-cells = <0>;
65 reg = <0xa00>;
66 interrupts = <0xa 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
[all …]
H A Dsc8280xp-pmics.dtsi14 polling-delay = <0>;
20 hysteresis = <0>;
26 hysteresis = <0>;
34 polling-delay = <0>;
40 hysteresis = <0>;
46 hysteresis = <0>;
55 pmk8280: pmic@0 {
57 reg = <0x0 SPMI_USID>;
59 #size-cells = <0>;
63 reg = <0x1300>, <0x800>;
[all …]
H A Dpm8550ve.dtsi13 polling-delay = <0>;
20 hysteresis = <0>;
26 hysteresis = <0>;
38 reg = <0x5 SPMI_USID>;
40 #size-cells = <0>;
44 reg = <0xa00>;
45 interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
46 #thermal-sensor-cells = <0>;
51 reg = <0x8800>;
53 gpio-ranges = <&pm8550ve_gpios 0 0 8>;
H A Dpm8450.dtsi13 polling-delay = <0>;
20 hysteresis = <0>;
26 hysteresis = <0>;
38 reg = <0x7 SPMI_USID>;
40 #size-cells = <0>;
44 reg = <0xa00>;
45 interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
46 #thermal-sensor-cells = <0>;
51 reg = <0x8800>;
53 gpio-ranges = <&pm8450_gpios 0 0 4>;
H A Dpm8550b.dtsi13 polling-delay = <0>;
20 hysteresis = <0>;
26 hysteresis = <0>;
38 reg = <0x7 SPMI_USID>;
40 #size-cells = <0>;
44 reg = <0xa00>;
45 interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
46 #thermal-sensor-cells = <0>;
51 reg = <0x8800>;
53 gpio-ranges = <&pm8550b_gpios 0 0 12>;
[all …]
H A Dpm8350.dtsi13 polling-delay = <0>;
19 hysteresis = <0>;
25 hysteresis = <0>;
36 reg = <0x1 SPMI_USID>;
38 #size-cells = <0>;
42 reg = <0xa00>;
43 interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
44 #thermal-sensor-cells = <0>;
49 reg = <0x8800>;
51 gpio-ranges = <&pm8350_gpios 0 0 10>;
H A Dpmr735b.dtsi13 polling-delay = <0>;
19 hysteresis = <0>;
25 hysteresis = <0>;
36 reg = <0x5 SPMI_USID>;
38 #size-cells = <0>;
42 reg = <0xa00>;
43 interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
44 #thermal-sensor-cells = <0>;
49 reg = <0x8800>;
51 gpio-ranges = <&pmr735b_gpios 0 0 4>;
H A Dpm7325.dtsi12 reg = <0x1 SPMI_USID>;
14 #size-cells = <0>;
18 reg = <0xa00>;
19 interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
20 #thermal-sensor-cells = <0>;
25 reg = <0x8800>;
27 gpio-ranges = <&pm7325_gpios 0 0 10>;
38 polling-delay = <0>;
44 hysteresis = <0>;
50 hysteresis = <0>;
H A Dpmx75.dtsi13 polling-delay = <0>;
20 hysteresis = <0>;
26 hysteresis = <0>;
32 hysteresis = <0>;
45 #size-cells = <0>;
49 reg = <0xa00>;
50 interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
51 #thermal-sensor-cells = <0>;
56 reg = <0x8800>;
58 gpio-ranges = <&pmx75_gpios 0 0 16>;
H A Dpm8350b.dtsi13 polling-delay = <0>;
19 hysteresis = <0>;
25 hysteresis = <0>;
36 reg = <0x3 SPMI_USID>;
38 #size-cells = <0>;
42 reg = <0xa00>;
43 interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
44 #thermal-sensor-cells = <0>;
49 reg = <0x8800>;
51 gpio-ranges = <&pm8350b_gpios 0 0 8>;
H A Dpmr735a.dtsi12 reg = <0x4 SPMI_USID>;
14 #size-cells = <0>;
18 reg = <0xa00>;
19 interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
20 #thermal-sensor-cells = <0>;
25 reg = <0x8800>;
27 gpio-ranges = <&pmr735a_gpios 0 0 4>;
39 polling-delay = <0>;
45 hysteresis = <0>;
51 hysteresis = <0>;
H A Dpm8350c.dtsi12 reg = <0x2 SPMI_USID>;
14 #size-cells = <0>;
18 reg = <0xa00>;
19 interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
20 #thermal-sensor-cells = <0>;
25 reg = <0x8800>;
27 gpio-ranges = <&pm8350c_gpios 0 0 9>;
45 polling-delay = <0>;
51 hysteresis = <0>;
57 hysteresis = <0>;
/openbmc/linux/drivers/pinctrl/samsung/
H A Dpinctrl-exynos.h20 #define EXYNOS_PIN_CON_FUNC_EINT 0xf
23 #define EXYNOS_GPIO_ECON_OFFSET 0x700
24 #define EXYNOS_GPIO_EFLTCON_OFFSET 0x800
25 #define EXYNOS_GPIO_EMASK_OFFSET 0x900
26 #define EXYNOS_GPIO_EPEND_OFFSET 0xA00
27 #define EXYNOS_WKUP_ECON_OFFSET 0xE00
28 #define EXYNOS_WKUP_EMASK_OFFSET 0xF00
29 #define EXYNOS_WKUP_EPEND_OFFSET 0xF40
30 #define EXYNOS7_WKUP_ECON_OFFSET 0x700
31 #define EXYNOS7_WKUP_EMASK_OFFSET 0x900
[all …]
/openbmc/u-boot/arch/mips/dts/
H A Dpic32mzda.dtsi29 cpu@0 {
36 reg = <0x1f801200 0x1000>;
42 reg = <0x1f822000 0x50>;
50 reg = <0x1f822200 0x50>;
58 reg = <0x1f822a00 0x50>;
68 reg = <0x1f810000 0x1000>;
73 reg = <0x1f801400 0x100>, /* in */
74 <0x1f801500 0x200>, /* out */
75 <0x1f860000 0xa00>; /* port */
79 ranges = <0 0x1f860000 0xa00>;
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-ls102xa/
H A Dimmap_ls102xa.h10 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
11 #define SVR_MIN(svr) (((svr) >> 0) & 0xf)
12 #define SVR_SOC_VER(svr) (((svr) >> 8) & 0x7ff)
13 #define IS_E_PROCESSOR(svr) (svr & 0x80000)
17 #define SOC_VER_SLS1020 0x00
18 #define SOC_VER_LS1020 0x10
19 #define SOC_VER_LS1021 0x11
20 #define SOC_VER_LS1022 0x12
22 #define SOC_MAJOR_VER_1_0 0x1
23 #define SOC_MAJOR_VER_2_0 0x2
[all …]
/openbmc/qemu/tests/qemu-iotests/
H A D07725 seq=`basename $0`
34 trap "_cleanup; exit \$status" 0 1 2 3 15
57 aio_write -P 10 0x200 0x200
62 off=0x1000
66 aio_write -P 10 $((off + 0x200)) 0x200
68 aio_write -P 11 $((off + 0x400)) 0x200
73 off=$((off + 0x1000))
79 aio_write -P 10 0x5000 0x200
81 aio_write -P 11 0x5200 0x200
82 aio_write -P 12 0x5400 0x200
[all …]
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dpmx65.dtsi14 #size-cells = <0>;
18 reg = <0xa00>;
19 interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
20 #thermal-sensor-cells = <0>;
25 reg = <0x8800>;
27 gpio-ranges = <&pmx65_gpios 0 0 16>;
/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dimmap_lsch3.h12 #define CONFIG_SYS_IMMR 0x01000000
13 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
14 #define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
15 #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
16 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
17 #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
19 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180)
21 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
23 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
24 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
[all …]
/openbmc/qemu/docs/specs/
H A Dacpi_mem_hotplug.rst7 Memory hot-plug interface (IO port 0xa00-0xa17, 1-4 byte access)
13 [0x0-0x3]
15 [0x4-0x7]
17 [0x8-0xb]
19 [0xc-0xf]
21 [0x10-0x13]
23 [0x14]
28 0:
40 [0x15-0x17]
47 [0x0-0x3]
[all …]
/openbmc/linux/drivers/clk/rockchip/
H A Dclk.h29 #define BOOST_PLL_H_CON(x) ((x) * 0x4)
30 #define BOOST_CLK_CON 0x0008
31 #define BOOST_BOOST_CON 0x000c
32 #define BOOST_SWITCH_CNT 0x0010
33 #define BOOST_HIGH_PERF_CNT0 0x0014
34 #define BOOST_HIGH_PERF_CNT1 0x0018
35 #define BOOST_STATIS_THRESHOLD 0x001c
36 #define BOOST_SHORT_SWITCH_CNT 0x0020
37 #define BOOST_SWITCH_THRESHOLD 0x0024
38 #define BOOST_FSM_STATUS 0x0028
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/ls102xa/
H A Dfsl_epu.h15 #define EPU_BLOCK_OFFSET 0x00000000
18 #define EPGCR 0x000
21 #define EPEVTCR0 0x050
22 #define EPEVTCR9 0x074
26 #define EPXTRIGCR 0x090
29 #define EPIMCR0 0x100
30 #define EPIMCR31 0x17C
34 #define EPSMCR0 0x200
35 #define EPSMCR15 0x278
39 #define EPECR0 0x300
[all …]

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